Lines Matching +full:sens +full:-
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 MediaTek Inc.
22 #include "mtk-eint.h"
36 .sens = 0x140,
58 if (eint_num >= eint->hw->ap_num) in mtk_eint_get_offset()
59 eint_base = eint->hw->ap_num; in mtk_eint_get_offset()
61 reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4; in mtk_eint_get_offset()
69 unsigned int sens; in mtk_eint_can_en_debounce() local
72 eint->regs->sens); in mtk_eint_can_en_debounce()
75 sens = MTK_EINT_LEVEL_SENSITIVE; in mtk_eint_can_en_debounce()
77 sens = MTK_EINT_EDGE_SENSITIVE; in mtk_eint_can_en_debounce()
79 if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE) in mtk_eint_can_en_debounce()
90 u32 port = (hwirq >> 5) & eint->hw->port_mask; in mtk_eint_flip_edge()
91 void __iomem *reg = eint->base + (port << 2); in mtk_eint_flip_edge()
93 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq); in mtk_eint_flip_edge()
98 reg_offset = eint->regs->pol_clr; in mtk_eint_flip_edge()
100 reg_offset = eint->regs->pol_set; in mtk_eint_flip_edge()
103 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, in mtk_eint_flip_edge()
113 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_mask()
114 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_mask()
115 eint->regs->mask_set); in mtk_eint_mask()
117 eint->cur_mask[d->hwirq >> 5] &= ~mask; in mtk_eint_mask()
125 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_unmask()
126 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_unmask()
127 eint->regs->mask_clr); in mtk_eint_unmask()
129 eint->cur_mask[d->hwirq >> 5] |= mask; in mtk_eint_unmask()
133 if (eint->dual_edge[d->hwirq]) in mtk_eint_unmask()
134 mtk_eint_flip_edge(eint, d->hwirq); in mtk_eint_unmask()
142 eint->regs->mask); in mtk_eint_get_mask()
150 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_ack()
151 void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, in mtk_eint_ack()
152 eint->regs->ack); in mtk_eint_ack()
160 u32 mask = BIT(d->hwirq & 0x1f); in mtk_eint_set_type()
165 dev_err(eint->dev, in mtk_eint_set_type()
167 d->irq, d->hwirq, type); in mtk_eint_set_type()
168 return -EINVAL; in mtk_eint_set_type()
172 eint->dual_edge[d->hwirq] = 1; in mtk_eint_set_type()
174 eint->dual_edge[d->hwirq] = 0; in mtk_eint_set_type()
177 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr); in mtk_eint_set_type()
180 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set); in mtk_eint_set_type()
185 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr); in mtk_eint_set_type()
188 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set); in mtk_eint_set_type()
192 if (eint->dual_edge[d->hwirq]) in mtk_eint_set_type()
193 mtk_eint_flip_edge(eint, d->hwirq); in mtk_eint_set_type()
201 int shift = d->hwirq & 0x1f; in mtk_eint_irq_set_wake()
202 int reg = d->hwirq >> 5; in mtk_eint_irq_set_wake()
205 eint->wake_mask[reg] |= BIT(shift); in mtk_eint_irq_set_wake()
207 eint->wake_mask[reg] &= ~BIT(shift); in mtk_eint_irq_set_wake()
218 for (port = 0; port < eint->hw->ports; port++) { in mtk_eint_chip_write_mask()
220 writel_relaxed(~buf[port], reg + eint->regs->mask_set); in mtk_eint_chip_write_mask()
221 writel_relaxed(buf[port], reg + eint->regs->mask_clr); in mtk_eint_chip_write_mask()
232 err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, in mtk_eint_irq_request_resources()
235 dev_err(eint->dev, "Can not find pin\n"); in mtk_eint_irq_request_resources()
241 dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n", in mtk_eint_irq_request_resources()
246 err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq); in mtk_eint_irq_request_resources()
248 dev_err(eint->dev, "Can not eint mode\n"); in mtk_eint_irq_request_resources()
261 eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n, in mtk_eint_irq_release_resources()
268 .name = "mt-eint",
281 void __iomem *dom_en = eint->base + eint->regs->dom_en; in mtk_eint_hw_init()
282 void __iomem *mask_set = eint->base + eint->regs->mask_set; in mtk_eint_hw_init()
285 for (i = 0; i < eint->hw->ap_num; i += 32) { in mtk_eint_hw_init()
301 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl; in mtk_eint_debounce_process()
302 dbnc = readl(eint->base + ctrl_offset); in mtk_eint_debounce_process()
305 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set; in mtk_eint_debounce_process()
307 writel(rst, eint->base + ctrl_offset); in mtk_eint_debounce_process()
317 void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat); in mtk_eint_irq_handler()
321 for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32, in mtk_eint_irq_handler()
328 virq = irq_find_mapping(eint->domain, index); in mtk_eint_irq_handler()
337 if (eint->wake_mask[mask_offset] & BIT(offset) && in mtk_eint_irq_handler()
338 !(eint->cur_mask[mask_offset] & BIT(offset))) { in mtk_eint_irq_handler()
339 writel_relaxed(BIT(offset), reg - in mtk_eint_irq_handler()
340 eint->regs->stat + in mtk_eint_irq_handler()
341 eint->regs->mask_set); in mtk_eint_irq_handler()
344 dual_edge = eint->dual_edge[index]; in mtk_eint_irq_handler()
347 * Clear soft-irq in case we raised it last in mtk_eint_irq_handler()
350 writel(BIT(offset), reg - eint->regs->stat + in mtk_eint_irq_handler()
351 eint->regs->soft_clr); in mtk_eint_irq_handler()
354 eint->gpio_xlate->get_gpio_state(eint->pctl, in mtk_eint_irq_handler()
365 * interrupt, raised it through soft-irq. in mtk_eint_irq_handler()
368 writel(BIT(offset), reg - in mtk_eint_irq_handler()
369 eint->regs->stat + in mtk_eint_irq_handler()
370 eint->regs->soft_set); in mtk_eint_irq_handler()
373 if (index < eint->hw->db_cnt) in mtk_eint_irq_handler()
382 mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask); in mtk_eint_do_suspend()
390 mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask); in mtk_eint_do_resume()
406 virq = irq_find_mapping(eint->domain, eint_num); in mtk_eint_set_debounce()
410 set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set; in mtk_eint_set_debounce()
411 clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr; in mtk_eint_set_debounce()
414 return -EINVAL; in mtk_eint_set_debounce()
432 writel(clr_bit, eint->base + clr_offset); in mtk_eint_set_debounce()
437 writel(rst | bit, eint->base + set_offset); in mtk_eint_set_debounce()
455 irq = irq_find_mapping(eint->domain, eint_n); in mtk_eint_find_irq()
457 return -EINVAL; in mtk_eint_find_irq()
468 if (!eint->regs) in mtk_eint_do_init()
469 eint->regs = &mtk_generic_eint_regs; in mtk_eint_do_init()
471 eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports, in mtk_eint_do_init()
472 sizeof(*eint->wake_mask), GFP_KERNEL); in mtk_eint_do_init()
473 if (!eint->wake_mask) in mtk_eint_do_init()
474 return -ENOMEM; in mtk_eint_do_init()
476 eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports, in mtk_eint_do_init()
477 sizeof(*eint->cur_mask), GFP_KERNEL); in mtk_eint_do_init()
478 if (!eint->cur_mask) in mtk_eint_do_init()
479 return -ENOMEM; in mtk_eint_do_init()
481 eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num, in mtk_eint_do_init()
483 if (!eint->dual_edge) in mtk_eint_do_init()
484 return -ENOMEM; in mtk_eint_do_init()
486 eint->domain = irq_domain_add_linear(eint->dev->of_node, in mtk_eint_do_init()
487 eint->hw->ap_num, in mtk_eint_do_init()
489 if (!eint->domain) in mtk_eint_do_init()
490 return -ENOMEM; in mtk_eint_do_init()
493 for (i = 0; i < eint->hw->ap_num; i++) { in mtk_eint_do_init()
494 int virq = irq_create_mapping(eint->domain, i); in mtk_eint_do_init()
501 irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler, in mtk_eint_do_init()