Lines Matching refs:pin_reg
42 u32 pin_reg; in amd_gpio_get_direction() local
46 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_direction()
49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) in amd_gpio_get_direction()
58 u32 pin_reg; in amd_gpio_direction_input() local
62 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_input()
64 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()
73 u32 pin_reg; in amd_gpio_direction_output() local
78 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
79 pin_reg |= BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_output()
81 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
84 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_output()
92 u32 pin_reg; in amd_gpio_get_value() local
97 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
100 return !!(pin_reg & BIT(PIN_STS_OFF)); in amd_gpio_get_value()
105 u32 pin_reg; in amd_gpio_set_value() local
110 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
112 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
115 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_value()
123 u32 pin_reg; in amd_gpio_set_debounce() local
129 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
132 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_set_debounce()
133 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
145 pin_reg |= 1; in amd_gpio_set_debounce()
146 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
147 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
150 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
155 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
156 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
160 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
162 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
165 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
166 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
167 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
169 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_set_debounce()
173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
174 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
175 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
176 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_set_debounce()
178 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
199 u32 pin_reg; in amd_gpio_dbg_show() local
245 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_dbg_show()
248 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { in amd_gpio_dbg_show()
249 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & in amd_gpio_dbg_show()
257 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && in amd_gpio_dbg_show()
263 if (pin_reg & BIT(LEVEL_TRIG_OFF)) in amd_gpio_dbg_show()
275 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) in amd_gpio_dbg_show()
282 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) in amd_gpio_dbg_show()
287 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) in amd_gpio_dbg_show()
292 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) in amd_gpio_dbg_show()
297 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { in amd_gpio_dbg_show()
299 if (pin_reg & BIT(PULL_UP_SEL_OFF)) in amd_gpio_dbg_show()
308 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) in amd_gpio_dbg_show()
313 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { in amd_gpio_dbg_show()
316 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) in amd_gpio_dbg_show()
324 if (pin_reg & BIT(PIN_STS_OFF)) in amd_gpio_dbg_show()
336 output_value, output_enable, pin_reg); in amd_gpio_dbg_show()
346 u32 pin_reg; in amd_gpio_irq_enable() local
352 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
353 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_enable()
354 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_enable()
355 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
361 u32 pin_reg; in amd_gpio_irq_disable() local
367 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
368 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_disable()
369 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_disable()
370 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
376 u32 pin_reg; in amd_gpio_irq_mask() local
382 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
383 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_mask()
384 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
390 u32 pin_reg; in amd_gpio_irq_unmask() local
396 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
397 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_unmask()
398 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
419 u32 pin_reg, pin_reg_irq_en, mask; in amd_gpio_irq_set_type() local
425 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
429 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
430 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
431 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
436 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
437 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
438 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
443 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
444 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
445 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
450 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
451 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
452 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
457 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
458 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
459 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
471 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; in amd_gpio_irq_set_type()
488 pin_reg_irq_en = pin_reg; in amd_gpio_irq_set_type()
494 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
632 u32 pin_reg; in amd_pinconf_get() local
639 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_get()
643 arg = pin_reg & DB_TMR_OUT_MASK; in amd_pinconf_get()
647 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); in amd_pinconf_get()
651 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); in amd_pinconf_get()
655 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; in amd_pinconf_get()
675 u32 pin_reg; in amd_pinconf_set() local
684 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_set()
688 pin_reg &= ~DB_TMR_OUT_MASK; in amd_pinconf_set()
689 pin_reg |= arg & DB_TMR_OUT_MASK; in amd_pinconf_set()
693 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); in amd_pinconf_set()
694 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; in amd_pinconf_set()
698 pin_reg &= ~BIT(PULL_UP_SEL_OFF); in amd_pinconf_set()
699 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; in amd_pinconf_set()
700 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); in amd_pinconf_set()
701 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; in amd_pinconf_set()
705 pin_reg &= ~(DRV_STRENGTH_SEL_MASK in amd_pinconf_set()
707 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) in amd_pinconf_set()
717 writel(pin_reg, gpio_dev->base + pin*4); in amd_pinconf_set()
771 u32 pin_reg, mask; in amd_gpio_irq_init() local
787 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_irq_init()
788 pin_reg &= ~mask; in amd_gpio_irq_init()
789 writel(pin_reg, gpio_dev->base + i * 4); in amd_gpio_irq_init()