Lines Matching full:bank
125 * @reg_base: register base of the gpio bank
127 * @clk: clock of the gpio bank
128 * @irq: interrupt of the gpio bank
131 * @nr_pins: number of pins in this bank
132 * @name: name of the bank
133 * @bank_num: number of the bank, to account for holes
134 * @iomux: array describing the 4 iomux sources of the bank
135 * @drv: array describing the 4 drive strength sources of the bank
136 * @pull_type: array describing the 4 pull type sources of the bank
138 * @of_node: dt node of this bank
140 * @domain: irqdomain of the gpio bank
143 * @slock: spinlock for the gpio bank
146 * @route_mask: bits describing the routing pins of per bank
295 * @num: bank number.
317 * @bank_num: bank number.
348 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
351 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
354 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
427 * given a pin number that is local to a pin controller, find out the pin bank
428 * and the register base of the pin bank.
795 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
798 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
805 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1412 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1415 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1422 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1437 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
1439 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1449 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1454 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1457 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1461 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1462 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1478 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1479 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_get_mux()
1488 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, in rockchip_verify_mux() argument
1491 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
1497 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1502 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1522 * @bank: pin bank to change
1526 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) in rockchip_set_mux() argument
1528 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
1535 ret = rockchip_verify_mux(bank, pin, mux); in rockchip_set_mux()
1539 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1543 bank->bank_num, pin, mux); in rockchip_set_mux()
1545 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1549 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1550 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1566 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1567 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); in rockchip_set_mux()
1569 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1570 if (rockchip_get_mux_route(bank, pin, mux, &route_location, in rockchip_set_mux()
1604 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_pull_reg_and_bit() argument
1608 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
1610 /* The first 32 pins of the first bank are located in PMU */ in px30_calc_pull_reg_and_bit()
1611 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1618 /* correct the offset, as we're starting with the 2nd bank */ in px30_calc_pull_reg_and_bit()
1620 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1634 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_drv_reg_and_bit() argument
1638 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1640 /* The first 32 pins of the first bank are located in PMU */ in px30_calc_drv_reg_and_bit()
1641 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1648 /* correct the offset, as we're starting with the 2nd bank */ in px30_calc_drv_reg_and_bit()
1650 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1664 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in px30_calc_schmitt_reg_and_bit() argument
1669 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1672 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1680 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1695 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_pull_reg_and_bit() argument
1699 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1701 /* The first 24 pins of the first bank are located in PMU */ in rv1108_calc_pull_reg_and_bit()
1702 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1708 /* correct the offset, as we're starting with the 2nd bank */ in rv1108_calc_pull_reg_and_bit()
1710 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1724 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_drv_reg_and_bit() argument
1728 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1730 /* The first 24 pins of the first bank are located in PMU */ in rv1108_calc_drv_reg_and_bit()
1731 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1738 /* correct the offset, as we're starting with the 2nd bank */ in rv1108_calc_drv_reg_and_bit()
1740 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1754 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rv1108_calc_schmitt_reg_and_bit() argument
1759 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1762 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1770 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1782 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rk3308_calc_schmitt_reg_and_bit() argument
1786 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1791 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1802 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk2928_calc_pull_reg_and_bit() argument
1806 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1810 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1818 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3128_calc_pull_reg_and_bit() argument
1822 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1826 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1838 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3188_calc_pull_reg_and_bit() argument
1842 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1844 /* The first 12 pins of the first bank are located elsewhere */ in rk3188_calc_pull_reg_and_bit()
1845 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1847 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1859 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1873 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3288_calc_pull_reg_and_bit() argument
1877 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1879 /* The first 24 pins of the first bank are located in PMU */ in rk3288_calc_pull_reg_and_bit()
1880 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1891 /* correct the offset, as we're starting with the 2nd bank */ in rk3288_calc_pull_reg_and_bit()
1893 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1907 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3288_calc_drv_reg_and_bit() argument
1911 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1913 /* The first 24 pins of the first bank are located in PMU */ in rk3288_calc_drv_reg_and_bit()
1914 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1925 /* correct the offset, as we're starting with the 2nd bank */ in rk3288_calc_drv_reg_and_bit()
1927 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1937 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3228_calc_pull_reg_and_bit() argument
1941 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1945 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1954 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3228_calc_drv_reg_and_bit() argument
1958 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1962 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1971 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3308_calc_pull_reg_and_bit() argument
1975 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1979 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1988 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3308_calc_drv_reg_and_bit() argument
1992 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1996 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
2006 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3368_calc_pull_reg_and_bit() argument
2010 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
2012 /* The first 32 pins of the first bank are located in PMU */ in rk3368_calc_pull_reg_and_bit()
2013 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
2024 /* correct the offset, as we're starting with the 2nd bank */ in rk3368_calc_pull_reg_and_bit()
2026 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
2037 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3368_calc_drv_reg_and_bit() argument
2041 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
2043 /* The first 32 pins of the first bank are located in PMU */ in rk3368_calc_drv_reg_and_bit()
2044 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
2055 /* correct the offset, as we're starting with the 2nd bank */ in rk3368_calc_drv_reg_and_bit()
2057 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
2069 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, in rk3399_calc_pull_reg_and_bit() argument
2073 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
2076 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
2080 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2089 /* correct the offset, as we're starting with the 3rd bank */ in rk3399_calc_pull_reg_and_bit()
2091 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2099 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, in rk3399_calc_drv_reg_and_bit() argument
2103 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
2107 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
2112 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
2113 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
2114 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
2128 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, in rockchip_get_drive_perpin() argument
2131 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
2137 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
2139 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
2205 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, in rockchip_set_drive_perpin() argument
2208 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
2214 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
2217 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
2219 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
2314 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) in rockchip_get_pull() argument
2316 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
2327 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
2346 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
2357 static int rockchip_set_pull(struct rockchip_pin_bank *bank, in rockchip_set_pull() argument
2360 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
2368 bank->bank_num, pin_num, pull); in rockchip_set_pull()
2374 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
2391 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
2427 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, in rk3328_calc_schmitt_reg_and_bit() argument
2432 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
2437 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
2444 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) in rockchip_get_schmitt() argument
2446 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
2453 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
2465 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, in rockchip_set_schmitt() argument
2468 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
2476 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
2478 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
2526 struct rockchip_pin_bank *bank; in rockchip_pmx_set() local
2537 bank = pin_to_bank(info, pins[cnt]); in rockchip_pmx_set()
2538 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
2547 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2557 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); in rockchip_gpio_get_direction() local
2561 ret = clk_enable(bank->clk); in rockchip_gpio_get_direction()
2563 dev_err(bank->drvdata->dev, in rockchip_gpio_get_direction()
2564 "failed to enable clock for bank %s\n", bank->name); in rockchip_gpio_get_direction()
2567 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_gpio_get_direction()
2568 clk_disable(bank->clk); in rockchip_gpio_get_direction()
2584 struct rockchip_pin_bank *bank; in _rockchip_pmx_gpio_set_direction() local
2589 bank = gpiochip_get_data(chip); in _rockchip_pmx_gpio_set_direction()
2591 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); in _rockchip_pmx_gpio_set_direction()
2595 clk_enable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2596 raw_spin_lock_irqsave(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2598 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2604 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2606 raw_spin_unlock_irqrestore(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2607 clk_disable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2672 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); in rockchip_pinconf_set() local
2684 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2699 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2705 rockchip_gpio_set(&bank->gpio_chip, in rockchip_pinconf_set()
2706 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2707 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, in rockchip_pinconf_set()
2708 pin - bank->pin_base, false); in rockchip_pinconf_set()
2717 rc = rockchip_set_drive_perpin(bank, in rockchip_pinconf_set()
2718 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2726 rc = rockchip_set_schmitt(bank, in rockchip_pinconf_set()
2727 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2745 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); in rockchip_pinconf_get() local
2752 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2764 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2770 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2774 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); in rockchip_pinconf_get()
2785 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2795 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2818 { .compatible = "rockchip,gpio-bank" },
2842 struct rockchip_pin_bank *bank; in rockchip_pinctrl_parse_groups() local
2855 * the binding format is rockchip,pins = <bank pin mux CONFIG>, in rockchip_pinctrl_parse_groups()
2882 bank = bank_num_to_bank(info, num); in rockchip_pinctrl_parse_groups()
2883 if (IS_ERR(bank)) in rockchip_pinctrl_parse_groups()
2884 return PTR_ERR(bank); in rockchip_pinctrl_parse_groups()
2886 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2993 int pin, bank, ret; in rockchip_pinctrl_register() local
3012 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
3013 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3032 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { in rockchip_pinctrl_register()
3033 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3035 pin_bank->grange.id = bank; in rockchip_pinctrl_register()
3052 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_set() local
3053 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; in rockchip_gpio_set()
3057 clk_enable(bank->clk); in rockchip_gpio_set()
3058 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set()
3066 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set()
3067 clk_disable(bank->clk); in rockchip_gpio_set()
3076 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_get() local
3079 clk_enable(bank->clk); in rockchip_gpio_get()
3080 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_gpio_get()
3081 clk_disable(bank->clk); in rockchip_gpio_get()
3112 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_set_debounce() local
3113 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; in rockchip_gpio_set_debounce()
3117 clk_enable(bank->clk); in rockchip_gpio_set_debounce()
3118 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set_debounce()
3127 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set_debounce()
3128 clk_disable(bank->clk); in rockchip_gpio_set_debounce()
3167 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_to_irq() local
3170 if (!bank->domain) in rockchip_gpio_to_irq()
3173 clk_enable(bank->clk); in rockchip_gpio_to_irq()
3174 virq = irq_create_mapping(bank->domain, offset); in rockchip_gpio_to_irq()
3175 clk_disable(bank->clk); in rockchip_gpio_to_irq()
3200 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); in rockchip_irq_demux() local
3203 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); in rockchip_irq_demux()
3207 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); in rockchip_irq_demux()
3214 virq = irq_find_mapping(bank->domain, irq); in rockchip_irq_demux()
3217 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); in rockchip_irq_demux()
3221 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); in rockchip_irq_demux()
3227 if (bank->toggle_edge_mode & BIT(irq)) { in rockchip_irq_demux()
3231 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_demux()
3233 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_demux()
3235 polarity = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3242 bank->reg_base + GPIO_INT_POLARITY); in rockchip_irq_demux()
3244 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_demux()
3247 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3261 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_set_type() local
3270 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); in rockchip_irq_set_type()
3274 clk_enable(bank->clk); in rockchip_irq_set_type()
3275 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3277 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3279 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3281 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3288 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3296 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
3303 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_set_type()
3310 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3315 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3320 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3325 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3331 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3332 clk_disable(bank->clk); in rockchip_irq_set_type()
3340 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3341 clk_disable(bank->clk); in rockchip_irq_set_type()
3349 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_suspend() local
3351 clk_enable(bank->clk); in rockchip_irq_suspend()
3352 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); in rockchip_irq_suspend()
3354 clk_disable(bank->clk); in rockchip_irq_suspend()
3360 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_resume() local
3362 clk_enable(bank->clk); in rockchip_irq_resume()
3363 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); in rockchip_irq_resume()
3364 clk_disable(bank->clk); in rockchip_irq_resume()
3370 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_enable() local
3372 clk_enable(bank->clk); in rockchip_irq_enable()
3379 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_disable() local
3382 clk_disable(bank->clk); in rockchip_irq_disable()
3389 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_interrupts_register() local
3395 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_interrupts_register()
3396 if (!bank->valid) { in rockchip_interrupts_register()
3397 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_interrupts_register()
3398 bank->name); in rockchip_interrupts_register()
3402 ret = clk_enable(bank->clk); in rockchip_interrupts_register()
3404 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", in rockchip_interrupts_register()
3405 bank->name); in rockchip_interrupts_register()
3409 bank->domain = irq_domain_add_linear(bank->of_node, 32, in rockchip_interrupts_register()
3411 if (!bank->domain) { in rockchip_interrupts_register()
3412 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", in rockchip_interrupts_register()
3413 bank->name); in rockchip_interrupts_register()
3414 clk_disable(bank->clk); in rockchip_interrupts_register()
3418 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, in rockchip_interrupts_register()
3422 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", in rockchip_interrupts_register()
3423 bank->name); in rockchip_interrupts_register()
3424 irq_domain_remove(bank->domain); in rockchip_interrupts_register()
3425 clk_disable(bank->clk); in rockchip_interrupts_register()
3429 gc = irq_get_domain_generic_chip(bank->domain, 0); in rockchip_interrupts_register()
3430 gc->reg_base = bank->reg_base; in rockchip_interrupts_register()
3431 gc->private = bank; in rockchip_interrupts_register()
3443 gc->wake_enabled = IRQ_MSK(bank->nr_pins); in rockchip_interrupts_register()
3450 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); in rockchip_interrupts_register()
3451 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); in rockchip_interrupts_register()
3454 irq_set_chained_handler_and_data(bank->irq, in rockchip_interrupts_register()
3455 rockchip_irq_demux, bank); in rockchip_interrupts_register()
3456 clk_disable(bank->clk); in rockchip_interrupts_register()
3466 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_register() local
3471 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_register()
3472 if (!bank->valid) { in rockchip_gpiolib_register()
3473 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_gpiolib_register()
3474 bank->name); in rockchip_gpiolib_register()
3478 bank->gpio_chip = rockchip_gpiolib_chip; in rockchip_gpiolib_register()
3480 gc = &bank->gpio_chip; in rockchip_gpiolib_register()
3481 gc->base = bank->pin_base; in rockchip_gpiolib_register()
3482 gc->ngpio = bank->nr_pins; in rockchip_gpiolib_register()
3484 gc->of_node = bank->of_node; in rockchip_gpiolib_register()
3485 gc->label = bank->name; in rockchip_gpiolib_register()
3487 ret = gpiochip_add_data(gc, bank); in rockchip_gpiolib_register()
3500 for (--i, --bank; i >= 0; --i, --bank) { in rockchip_gpiolib_register()
3501 if (!bank->valid) in rockchip_gpiolib_register()
3503 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_register()
3512 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_unregister() local
3515 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_unregister()
3516 if (!bank->valid) in rockchip_gpiolib_unregister()
3518 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_unregister()
3524 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, in rockchip_get_bank_data() argument
3530 if (of_address_to_resource(bank->of_node, 0, &res)) { in rockchip_get_bank_data()
3531 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3535 bank->reg_base = devm_ioremap_resource(info->dev, &res); in rockchip_get_bank_data()
3536 if (IS_ERR(bank->reg_base)) in rockchip_get_bank_data()
3537 return PTR_ERR(bank->reg_base); in rockchip_get_bank_data()
3543 if (of_device_is_compatible(bank->of_node, in rockchip_get_bank_data()
3547 node = of_parse_phandle(bank->of_node->parent, in rockchip_get_bank_data()
3550 if (of_address_to_resource(bank->of_node, 1, &res)) { in rockchip_get_bank_data()
3551 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3562 bank->regmap_pull = devm_regmap_init_mmio(info->dev, in rockchip_get_bank_data()
3569 bank->irq = irq_of_parse_and_map(bank->of_node, 0); in rockchip_get_bank_data()
3571 bank->clk = of_clk_get(bank->of_node, 0); in rockchip_get_bank_data()
3572 if (IS_ERR(bank->clk)) in rockchip_get_bank_data()
3573 return PTR_ERR(bank->clk); in rockchip_get_bank_data()
3575 return clk_prepare(bank->clk); in rockchip_get_bank_data()
3589 struct rockchip_pin_bank *bank; in rockchip_pinctrl_get_soc_data() local
3599 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3600 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3601 if (!strcmp(bank->name, np->name)) { in rockchip_pinctrl_get_soc_data()
3602 bank->of_node = np; in rockchip_pinctrl_get_soc_data()
3604 if (!rockchip_get_bank_data(bank, d)) in rockchip_pinctrl_get_soc_data()
3605 bank->valid = true; in rockchip_pinctrl_get_soc_data()
3616 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3617 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3620 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
3621 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
3622 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
3623 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
3627 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
3628 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
3631 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
3656 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", in rockchip_pinctrl_get_soc_data()
3689 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
3693 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3695 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3699 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
3703 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3705 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()