Lines Matching +full:spi +full:- +full:nand
1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-xway.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
21 #include "pinctrl-lantiq.h"
110 /* --------- DEPRECATED: xr9 related code --------- */
111 /* ---------- use xrx100/xrx200 instead ---------- */
125 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
126 MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE),
127 MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI),
129 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
131 MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE),
132 MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG),
133 MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG),
134 MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG),
138 MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE),
249 GRP_MUX("nand ale", EBU, pins_nand_ale),
250 GRP_MUX("nand cs1", EBU, pins_nand_cs1),
251 GRP_MUX("nand cle", EBU, pins_nand_cle),
252 GRP_MUX("spi", SPI, pins_spi),
253 GRP_MUX("spi_cs1", SPI, pins_spi_cs1),
254 GRP_MUX("spi_cs2", SPI, pins_spi_cs2),
255 GRP_MUX("spi_cs3", SPI, pins_spi_cs3),
256 GRP_MUX("spi_cs4", SPI, pins_spi_cs4),
257 GRP_MUX("spi_cs5", SPI, pins_spi_cs5),
258 GRP_MUX("spi_cs6", SPI, pins_spi_cs6),
277 GRP_MUX("nand rdy", EBU, pins_nand_rdy),
278 GRP_MUX("nand rd", EBU, pins_nand_rd),
296 static const char * const xway_spi_grps[] = {"spi", "spi_cs1",
305 "nand ale", "nand cs1",
306 "nand cle"};
322 "nand ale", "nand cs1",
323 "nand cle", "nand rdy",
324 "nand rd"};
333 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
347 /* --------- ase related code --------- */
359 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
360 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
361 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
362 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
366 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
367 MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
423 GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
424 GRP_MUX("spi_di", SPI, ase_pins_spi_di),
425 GRP_MUX("spi_do", SPI, ase_pins_spi_do),
426 GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
427 GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
428 GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
429 GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
457 static const char * const ase_spi_grps[] = {"spi", /* DEPRECATED */
463 {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
475 /* --------- danube related code --------- */
489 MFP_XWAY(GPIO9, GPIO, ASC, SPI, MII),
490 MFP_XWAY(GPIO10, GPIO, ASC, SPI, MII),
491 MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
493 MFP_XWAY(GPIO13, GPIO, EBU, SPI, MII),
495 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, JTAG),
496 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, JTAG),
497 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, JTAG),
498 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, JTAG),
502 MFP_XWAY(GPIO22, GPIO, SPI, MCD, MII),
578 GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
579 GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
580 GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
581 GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
582 GRP_MUX("spi_di", SPI, danube_pins_spi_di),
583 GRP_MUX("spi_do", SPI, danube_pins_spi_do),
584 GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
585 GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
586 GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
587 GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
588 GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
589 GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
590 GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
615 static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
626 "nand ale", "nand cs1",
627 "nand cle"};
637 {"spi", ARRAY_AND_SIZE(danube_spi_grps)},
650 /* --------- xrx100 related code --------- */
664 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
665 MFP_XWAY(GPIO10, GPIO, ASC, SPI, EXIN),
666 MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
668 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
670 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
671 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
672 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
673 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
677 MFP_XWAY(GPIO22, GPIO, SPI, NONE, EBU),
785 GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
786 GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
787 GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
788 GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
789 GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
790 GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
791 GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
792 GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
793 GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
794 GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
795 GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
796 GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
797 GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
798 GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
837 "nand ale", "nand cs1",
838 "nand cle", "nand rdy",
839 "nand rd"};
850 {"spi", ARRAY_AND_SIZE(xrx100_spi_grps)},
863 /* --------- xrx200 related code --------- */
877 MFP_XWAY(GPIO9, GPIO, USIF, SPI, EXIN),
878 MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
879 MFP_XWAY(GPIO11, GPIO, USIF, CBUS, SPI),
881 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
883 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
884 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
885 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
886 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
890 MFP_XWAY(GPIO22, GPIO, SPI, CGU, EBU),
1013 GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
1014 GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
1015 GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
1016 GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
1017 GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
1018 GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
1019 GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
1020 GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
1021 GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
1022 GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
1023 GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
1024 GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
1025 GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
1026 GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
1083 "nand ale", "nand cs1",
1084 "nand cle", "nand rdy",
1085 "nand rd"};
1105 {"spi", ARRAY_AND_SIZE(xrx200_spi_grps)},
1119 /* --------- xrx300 related code --------- */
1134 MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
1135 MFP_XWAY(GPIO11, GPIO, USIF, WIFI, SPI),
1139 MFP_XWAY(GPIO15, GPIO, SPI, NONE, MCD),
1140 MFP_XWAY(GPIO16, GPIO, SPI, EXIN, NONE),
1141 MFP_XWAY(GPIO17, GPIO, SPI, NONE, NONE),
1142 MFP_XWAY(GPIO18, GPIO, SPI, NONE, NONE),
1256 GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
1257 GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
1258 GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
1259 GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
1260 GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
1261 GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
1262 GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
1263 GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
1264 GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
1265 GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
1266 GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
1267 GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
1268 GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
1269 GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
1270 GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
1271 GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
1272 GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
1273 GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
1274 GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
1275 GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
1276 GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
1277 GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
1278 GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
1300 static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
1301 "nand cle", "nand rdy",
1302 "nand rd", "nand d1",
1303 "nand d0", "nand d2",
1304 "nand d7", "nand d6",
1305 "nand d5", "nand d4",
1306 "nand d3", "nand cs0",
1307 "nand wr", "nand wp",
1308 "nand se"};
1321 {"spi", ARRAY_AND_SIZE(xrx300_spi_grps)},
1332 /* --------- pinconf related code --------- */
1349 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); in xway_pinconf_get()
1357 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { in xway_pinconf_get()
1366 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) in xway_pinconf_get()
1375 gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); in xway_pinconf_get()
1378 dev_err(pctldev->dev, "Invalid config param %04x\n", param); in xway_pinconf_get()
1379 return -ENOTSUPP; in xway_pinconf_get()
1407 gpio_setbit(info->membase[0], in xway_pinconf_set()
1411 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1422 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1427 gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); in xway_pinconf_set()
1434 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1438 gpio_setbit(info->membase[0], in xway_pinconf_set()
1442 dev_err(pctldev->dev, in xway_pinconf_set()
1449 gpio_clearbit(info->membase[0], in xway_pinconf_set()
1453 gpio_setbit(info->membase[0], in xway_pinconf_set()
1459 dev_err(pctldev->dev, in xway_pinconf_set()
1461 return -ENOTSUPP; in xway_pinconf_set()
1476 for (i = 0; i < info->grps[selector].npins && !ret; i++) in xway_pinconf_group_set()
1478 info->grps[selector].pins[i], in xway_pinconf_group_set()
1507 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); in xway_mux_apply()
1509 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin)); in xway_mux_apply()
1512 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin)); in xway_mux_apply()
1514 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin)); in xway_mux_apply()
1521 {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
1532 /* --------- gpio_chip related code --------- */
1535 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_set()
1538 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); in xway_gpio_set()
1540 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin)); in xway_gpio_set()
1545 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_get()
1547 return !!gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin)); in xway_gpio_get()
1552 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_dir_in()
1554 gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); in xway_gpio_dir_in()
1561 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_dir_out()
1564 gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin)); in xway_gpio_dir_out()
1566 gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin)); in xway_gpio_dir_out()
1567 gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); in xway_gpio_dir_out()
1579 struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent); in xway_gpio_to_irq()
1582 for (i = 0; i < info->num_exin; i++) in xway_gpio_to_irq()
1583 if (info->exin[i] == offset) in xway_gpio_to_irq()
1586 return -1; in xway_gpio_to_irq()
1590 .label = "gpio-xway",
1598 .base = -1,
1602 /* --------- register the pinctrl layer --------- */
1692 { .compatible = "lantiq,pinctrl-xway", .data = &danube_pinctrl}, /*DEPRECATED*/
1693 { .compatible = "lantiq,pinctrl-xr9", .data = &xr9_pinctrl}, /*DEPRECATED*/
1694 { .compatible = "lantiq,pinctrl-ase", .data = &ase_pinctrl}, /*DEPRECATED*/
1695 { .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
1696 { .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
1697 { .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
1698 { .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
1699 { .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
1715 match = of_match_device(xway_match, &pdev->dev); in pinmux_xway_probe()
1717 xway_soc = (const struct pinctrl_xway_soc *) match->data; in pinmux_xway_probe()
1722 xway_chip.ngpio = xway_soc->pin_count; in pinmux_xway_probe()
1725 xway_info.pads = devm_kcalloc(&pdev->dev, in pinmux_xway_probe()
1729 return -ENOMEM; in pinmux_xway_probe()
1732 char *name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "io%d", i); in pinmux_xway_probe()
1735 return -ENOMEM; in pinmux_xway_probe()
1743 xway_pctrl_desc.name = dev_name(&pdev->dev); in pinmux_xway_probe()
1748 xway_info.mfp = xway_soc->mfp; in pinmux_xway_probe()
1749 xway_info.grps = xway_soc->grps; in pinmux_xway_probe()
1750 xway_info.num_grps = xway_soc->num_grps; in pinmux_xway_probe()
1751 xway_info.funcs = xway_soc->funcs; in pinmux_xway_probe()
1752 xway_info.num_funcs = xway_soc->num_funcs; in pinmux_xway_probe()
1753 xway_info.exin = xway_soc->exin; in pinmux_xway_probe()
1754 xway_info.num_exin = xway_soc->num_exin; in pinmux_xway_probe()
1759 dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); in pinmux_xway_probe()
1764 xway_chip.parent = &pdev->dev; in pinmux_xway_probe()
1766 xway_chip.of_node = pdev->dev.of_node; in pinmux_xway_probe()
1767 ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL); in pinmux_xway_probe()
1769 dev_err(&pdev->dev, "Failed to register gpio chip\n"); in pinmux_xway_probe()
1774 * For DeviceTree-supported systems, the gpio core checks the in pinmux_xway_probe()
1775 * pinctrl's device node for the "gpio-ranges" property. in pinmux_xway_probe()
1780 * files which don't set the "gpio-ranges" property or systems that in pinmux_xway_probe()
1783 if (!of_property_read_bool(pdev->dev.of_node, "gpio-ranges")) { in pinmux_xway_probe()
1790 dev_info(&pdev->dev, "Init done\n"); in pinmux_xway_probe()
1797 .name = "pinctrl-xway",