Lines Matching full:bank
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
61 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
65 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
67 spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
74 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
75 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
77 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
84 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
85 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_unmask()
100 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_unmask()
102 mask = readl(bank->eint_base + reg_mask); in exynos_irq_unmask()
104 writel(mask, bank->eint_base + reg_mask); in exynos_irq_unmask()
106 spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_unmask()
113 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_set_type() local
116 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; in exynos_irq_set_type()
144 con = readl(bank->eint_base + reg_con); in exynos_irq_set_type()
147 writel(con, bank->eint_base + reg_con); in exynos_irq_set_type()
154 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_request_resources() local
155 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_request_resources()
160 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_request_resources()
162 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
164 bank->name, irqd->hwirq); in exynos_irq_request_resources()
168 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_request_resources()
172 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_request_resources()
174 con = readl(bank->pctl_base + reg_con); in exynos_irq_request_resources()
177 writel(con, bank->pctl_base + reg_con); in exynos_irq_request_resources()
179 spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_request_resources()
186 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_release_resources() local
187 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_release_resources()
191 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_release_resources()
195 spin_lock_irqsave(&bank->slock, flags); in exynos_irq_release_resources()
197 con = readl(bank->pctl_base + reg_con); in exynos_irq_release_resources()
200 writel(con, bank->pctl_base + reg_con); in exynos_irq_release_resources()
202 spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_release_resources()
204 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_release_resources()
248 struct samsung_pin_bank *bank = d->pin_banks; in exynos_eint_gpio_irq() local
251 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); in exynos_eint_gpio_irq()
257 bank += (group - 1); in exynos_eint_gpio_irq()
259 virq = irq_linear_revmap(bank->irq_domain, pin); in exynos_eint_gpio_irq()
279 struct samsung_pin_bank *bank; in exynos_eint_gpio_init() local
296 bank = d->pin_banks; in exynos_eint_gpio_init()
297 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_gpio_init()
298 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
301 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, in exynos_eint_gpio_init()
302 sizeof(*bank->irq_chip), GFP_KERNEL); in exynos_eint_gpio_init()
303 if (!bank->irq_chip) { in exynos_eint_gpio_init()
307 bank->irq_chip->chip.name = bank->name; in exynos_eint_gpio_init()
309 bank->irq_domain = irq_domain_add_linear(bank->of_node, in exynos_eint_gpio_init()
310 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_gpio_init()
311 if (!bank->irq_domain) { in exynos_eint_gpio_init()
317 bank->soc_priv = devm_kzalloc(d->dev, in exynos_eint_gpio_init()
319 if (!bank->soc_priv) { in exynos_eint_gpio_init()
320 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
330 for (--i, --bank; i >= 0; --i, --bank) { in exynos_eint_gpio_init()
331 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
333 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
343 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_wkup_irq_set_wake() local
344 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); in exynos_wkup_irq_set_wake()
364 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in exynos_pinctrl_set_eint_wakeup_mask()
386 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in s5pv210_pinctrl_set_eint_wakeup_mask()
474 struct samsung_pin_bank *bank = eintd->bank; in exynos_irq_eint0_15() local
480 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); in exynos_irq_eint0_15()
530 struct samsung_pin_bank *bank; in exynos_eint_wkup_init() local
551 bank = d->pin_banks; in exynos_eint_wkup_init()
552 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
553 if (bank->eint_type != EINT_TYPE_WKUP) in exynos_eint_wkup_init()
556 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), in exynos_eint_wkup_init()
558 if (!bank->irq_chip) { in exynos_eint_wkup_init()
562 bank->irq_chip->chip.name = bank->name; in exynos_eint_wkup_init()
564 bank->irq_domain = irq_domain_add_linear(bank->of_node, in exynos_eint_wkup_init()
565 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_wkup_init()
566 if (!bank->irq_domain) { in exynos_eint_wkup_init()
572 if (!of_find_property(bank->of_node, "interrupts", NULL)) { in exynos_eint_wkup_init()
573 bank->eint_type = EINT_TYPE_WKUP_MUX; in exynos_eint_wkup_init()
579 bank->nr_pins, sizeof(*weint_data), in exynos_eint_wkup_init()
586 for (idx = 0; idx < bank->nr_pins; ++idx) { in exynos_eint_wkup_init()
587 irq = irq_of_parse_and_map(bank->of_node, idx); in exynos_eint_wkup_init()
590 bank->name, idx); in exynos_eint_wkup_init()
594 weint_data[idx].bank = bank; in exynos_eint_wkup_init()
621 bank = d->pin_banks; in exynos_eint_wkup_init()
623 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
624 if (bank->eint_type != EINT_TYPE_WKUP_MUX) in exynos_eint_wkup_init()
627 muxed_data->banks[idx++] = bank; in exynos_eint_wkup_init()
636 struct samsung_pin_bank *bank) in exynos_pinctrl_suspend_bank() argument
638 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_suspend_bank()
639 void __iomem *regs = bank->eint_base; in exynos_pinctrl_suspend_bank()
642 + bank->eint_offset); in exynos_pinctrl_suspend_bank()
644 + 2 * bank->eint_offset); in exynos_pinctrl_suspend_bank()
646 + 2 * bank->eint_offset + 4); in exynos_pinctrl_suspend_bank()
647 save->eint_mask = readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_suspend_bank()
648 + bank->eint_offset); in exynos_pinctrl_suspend_bank()
650 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); in exynos_pinctrl_suspend_bank()
651 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); in exynos_pinctrl_suspend_bank()
652 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); in exynos_pinctrl_suspend_bank()
653 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); in exynos_pinctrl_suspend_bank()
658 struct samsung_pin_bank *bank = drvdata->pin_banks; in exynos_pinctrl_suspend() local
662 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { in exynos_pinctrl_suspend()
663 if (bank->eint_type == EINT_TYPE_GPIO) in exynos_pinctrl_suspend()
664 exynos_pinctrl_suspend_bank(drvdata, bank); in exynos_pinctrl_suspend()
665 else if (bank->eint_type == EINT_TYPE_WKUP) { in exynos_pinctrl_suspend()
667 irq_chip = bank->irq_chip; in exynos_pinctrl_suspend()
677 struct samsung_pin_bank *bank) in exynos_pinctrl_resume_bank() argument
679 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_resume_bank()
680 void __iomem *regs = bank->eint_base; in exynos_pinctrl_resume_bank()
682 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
684 + bank->eint_offset), save->eint_con); in exynos_pinctrl_resume_bank()
685 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
687 + 2 * bank->eint_offset), save->eint_fltcon0); in exynos_pinctrl_resume_bank()
688 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
690 + 2 * bank->eint_offset + 4), save->eint_fltcon1); in exynos_pinctrl_resume_bank()
691 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
692 readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume_bank()
693 + bank->eint_offset), save->eint_mask); in exynos_pinctrl_resume_bank()
696 + bank->eint_offset); in exynos_pinctrl_resume_bank()
698 + 2 * bank->eint_offset); in exynos_pinctrl_resume_bank()
700 + 2 * bank->eint_offset + 4); in exynos_pinctrl_resume_bank()
701 writel(save->eint_mask, regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume_bank()
702 + bank->eint_offset); in exynos_pinctrl_resume_bank()
707 struct samsung_pin_bank *bank = drvdata->pin_banks; in exynos_pinctrl_resume() local
710 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) in exynos_pinctrl_resume()
711 if (bank->eint_type == EINT_TYPE_GPIO) in exynos_pinctrl_resume()
712 exynos_pinctrl_resume_bank(drvdata, bank); in exynos_pinctrl_resume()