2  * Atmel AT91 SAM9 & SAMA5 SoCs reset code
24 #define AT91_RSTC_CR	0x00		/* Reset Controller Control Register */
25 #define AT91_RSTC_PROCRST	BIT(0)		/* Processor Reset */
26 #define AT91_RSTC_PERRST	BIT(2)		/* Peripheral Reset */
27 #define AT91_RSTC_EXTRST	BIT(3)		/* External Reset */
30 #define AT91_RSTC_SR	0x04		/* Reset Controller Status Register */
31 #define AT91_RSTC_URSTS		BIT(0)		/* User Reset Status */
32 #define AT91_RSTC_RSTTYP	GENMASK(10, 8)	/* Reset Type */
34 #define AT91_RSTC_SRCMP		BIT(17)		/* Software Reset Command in Progress */
36 #define AT91_RSTC_MR	0x08		/* Reset Controller Mode Register */
37 #define AT91_RSTC_URSTEN	BIT(0)		/* User Reset Enable */
38 #define AT91_RSTC_URSTASYNC	BIT(2)		/* User Reset Asynchronous Control */
39 #define AT91_RSTC_URSTIEN	BIT(4)		/* User Reset Interrupt Enable */
40 #define AT91_RSTC_ERSTL		GENMASK(11, 8)	/* External Reset Length */
64 * reset register it can be left driving the data bus and
70 	struct at91_reset *reset = container_of(this, struct at91_reset, nb);  in at91_reset()  local
88 		/* Reset CPU */  in at91_reset()
93 		: "r" (reset->ramc_base[0]),  in at91_reset()
94 		  "r" (reset->ramc_base[1]),  in at91_reset()
95 		  "r" (reset->rstc_base),  in at91_reset()
98 		  "r" (reset->args),  in at91_reset()
99 		  "r" (reset->ramc_lpr)  in at91_reset()
113 		reason = "general reset";  in at91_reset_status()
119 		reason = "watchdog reset";  in at91_reset_status()
122 		reason = "software reset";  in at91_reset_status()
125 		reason = "user reset";  in at91_reset_status()
134 		reason = "ULP2 reset";  in at91_reset_status()
137 		reason = "unknown reset";  in at91_reset_status()
187 	struct at91_reset *reset;  in at91_reset_probe()  local
191 	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);  in at91_reset_probe()
192 	if (!reset)  in at91_reset_probe()
195 	reset->rstc_base = of_iomap(pdev->dev.of_node, 0);  in at91_reset_probe()
196 	if (!reset->rstc_base) {  in at91_reset_probe()
197 		dev_err(&pdev->dev, "Could not map reset controller address\n");  in at91_reset_probe()
204 			reset->ramc_lpr = (u32)match->data;  in at91_reset_probe()
205 			reset->ramc_base[idx] = of_iomap(np, 0);  in at91_reset_probe()
206 			if (!reset->ramc_base[idx]) {  in at91_reset_probe()
216 	reset->nb.notifier_call = at91_reset;  in at91_reset_probe()
217 	reset->nb.priority = 192;  in at91_reset_probe()
218 	reset->args = (u32)match->data;  in at91_reset_probe()
220 	reset->sclk = devm_clk_get(&pdev->dev, NULL);  in at91_reset_probe()
221 	if (IS_ERR(reset->sclk))  in at91_reset_probe()
222 		return PTR_ERR(reset->sclk);  in at91_reset_probe()
224 	ret = clk_prepare_enable(reset->sclk);  in at91_reset_probe()
230 	platform_set_drvdata(pdev, reset);  in at91_reset_probe()
233 		u32 val = readl(reset->rstc_base + AT91_RSTC_MR);  in at91_reset_probe()
236 		       reset->rstc_base + AT91_RSTC_MR);  in at91_reset_probe()
239 	ret = register_restart_handler(&reset->nb);  in at91_reset_probe()
241 		clk_disable_unprepare(reset->sclk);  in at91_reset_probe()
245 	at91_reset_status(pdev, reset->rstc_base);  in at91_reset_probe()
252 	struct at91_reset *reset = platform_get_drvdata(pdev);  in at91_reset_remove()  local
254 	unregister_restart_handler(&reset->nb);  in at91_reset_remove()
255 	clk_disable_unprepare(reset->sclk);  in at91_reset_remove()
263 		.name = "at91-reset",
270 MODULE_DESCRIPTION("Reset driver for Atmel SoCs");