6  * - The TPM counter and period counter are shared between
7  *   multiple channels, so all channels should use same period
10  *   next period start.
11  * - Changing period and duty cycle together isn't atomic,
12  *   with the wrong timing it might happen that a period is
13  *   produced with old duty cycle but new period settings.
97 	tmp = (u64)state->period * rate;  in pwm_imx_tpm_round_state()
111 	/* calculate real period HW can support */  in pwm_imx_tpm_round_state()
114 	real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);  in pwm_imx_tpm_round_state()
127 	p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period);  in pwm_imx_tpm_round_state()
143 	/* get period */  in pwm_imx_tpm_get_state()
144 	state->period = tpm->real_period;  in pwm_imx_tpm_get_state()
182 	if (state->period != tpm->real_period) {  in pwm_imx_tpm_apply_hw()
185 		 * prescale and period can NOT be modified when  in pwm_imx_tpm_apply_hw()
187 		 * period settings.  in pwm_imx_tpm_apply_hw()
204 		 * set period count:  in pwm_imx_tpm_apply_hw()
208 		 * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the period length  in pwm_imx_tpm_apply_hw()
209 		 * is latched into hardware when the next period starts.  in pwm_imx_tpm_apply_hw()
212 		tpm->real_period = state->period;  in pwm_imx_tpm_apply_hw()
229 		 * is latched into hardware when the next period starts.  in pwm_imx_tpm_apply_hw()