42 	unsigned long period;  member
77 	tmp = readl_relaxed(pc->base + pc->data->regs.period);  in rockchip_pwm_get_state()
79 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);  in rockchip_pwm_get_state()
100 	unsigned long period, duty;  in rockchip_pwm_config()  local
107 	 * Since period and duty cycle registers have a width of 32  in rockchip_pwm_config()
108 	 * bits, every possible input period can be obtained using the  in rockchip_pwm_config()
111 	div = clk_rate * state->period;  in rockchip_pwm_config()
112 	period = DIV_ROUND_CLOSEST_ULL(div,  in rockchip_pwm_config()
119 	 * Lock the period and duty of previous configuration, then  in rockchip_pwm_config()
120 	 * change the duty and period, that would not be effective.  in rockchip_pwm_config()
128 	writel(period, pc->base + pc->data->regs.period);  in rockchip_pwm_config()
141 	 * the configuration of duty, period and polarity  in rockchip_pwm_config()
142 	 * would be effective together at next period.  in rockchip_pwm_config()
225 		.period = 0x08,
238 		.period = 0x04,
252 		.period = 0x04,
266 		.period = 0x04,