22  * Returns 0 on success or non-zero value on failure
27 		{ UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
28 		{ UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
29 		{ UIC_ARG_MIB(CDIRECTCTRL6), 0x80, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
30 		{ UIC_ARG_MIB(CBDIVFACTOR), 0x08, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
31 		{ UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
32 		{ UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
33 		{ UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
34 		{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
36 		{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,  in tc_dwc_g210_setup_40bit_rmmi()
38 		{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14,  in tc_dwc_g210_setup_40bit_rmmi()
40 		{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,  in tc_dwc_g210_setup_40bit_rmmi()
42 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
44 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,  in tc_dwc_g210_setup_40bit_rmmi()
48 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_40bit_rmmi()
50 		{ UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
51 		{ UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
52 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_40bit_rmmi()
54 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,  in tc_dwc_g210_setup_40bit_rmmi()
56 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,  in tc_dwc_g210_setup_40bit_rmmi()
58 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,  in tc_dwc_g210_setup_40bit_rmmi()
60 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,  in tc_dwc_g210_setup_40bit_rmmi()
62 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
64 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_40bit_rmmi()
66 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,  in tc_dwc_g210_setup_40bit_rmmi()
68 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,  in tc_dwc_g210_setup_40bit_rmmi()
70 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_40bit_rmmi()
72 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_40bit_rmmi()
74 		{ UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
83  * This function configures Synopsys TC 20-bit RMMI Lane 0
86  * Returns 0 on success or non-zero value on failure
91 		{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
93 		{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
95 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
97 		{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x12,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
99 		{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
101 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
105 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
107 		{ UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi_lane0()
108 		{ UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi_lane0()
109 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
111 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
113 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
115 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
117 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
119 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
121 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
123 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
125 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,  in tc_dwc_g210_setup_20bit_rmmi_lane0()
127 		{ UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi_lane0()
139  * Returns 0 on success or non-zero value on failure
143 	int connected_rx_lanes = 0;  in tc_dwc_g210_setup_20bit_rmmi_lane1()
144 	int connected_tx_lanes = 0;  in tc_dwc_g210_setup_20bit_rmmi_lane1()
145 	int ret = 0;  in tc_dwc_g210_setup_20bit_rmmi_lane1()
148 		{ UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN1_TX), 0x0d,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
150 		{ UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN1_TX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
152 		{ UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN1_TX), 0x12,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
154 		{ UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
159 		{ UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN1_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
161 		{ UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN1_RX), 0x19,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
165 		{ UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN1_RX), 0x80,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
167 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN1_RX), 0x03,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
169 		{ UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN1_RX), 0x16,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
171 		{ UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN1_RX), 0x42,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
173 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN1_RX), 0xa4,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
175 		{ UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN1_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
177 		{ UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN1_RX), 0x01,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
179 		{ UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN1_RX), 0x28,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
181 		{ UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN1_RX), 0x1E,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
183 		{ UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN1_RX), 0x2f,  in tc_dwc_g210_setup_20bit_rmmi_lane1()
216  * Returns 0 on success or non-zero value on failure
220 	int ret = 0;  in tc_dwc_g210_setup_20bit_rmmi()
223 		{ UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
224 		{ UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
225 		{ UIC_ARG_MIB(CDIRECTCTRL6), 0xc0, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
226 		{ UIC_ARG_MIB(CBDIVFACTOR), 0x44, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
227 		{ UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
228 		{ UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
229 		{ UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
237 	/* Lane 0 configuration*/  in tc_dwc_g210_setup_20bit_rmmi()
257  * Returns 0 on success non-zero value on failure
261 	int ret = 0;  in tc_dwc_g210_config_40_bit()
271 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);  in tc_dwc_g210_config_40_bit()
276 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);  in tc_dwc_g210_config_40_bit()
289  * Returns 0 on success non-zero value on failure
293 	int ret = 0;  in tc_dwc_g210_config_20_bit()
303 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);  in tc_dwc_g210_config_20_bit()
308 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);  in tc_dwc_g210_config_20_bit()