Lines Matching refs:hba
153 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link() local
157 exynos_ufs_enable_ov_tm(hba); in exynos7_ufs_pre_link()
159 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); in exynos7_ufs_pre_link()
161 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); in exynos7_ufs_pre_link()
162 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); in exynos7_ufs_pre_link()
164 exynos_ufs_disable_ov_tm(hba); in exynos7_ufs_pre_link()
167 ufshcd_dme_set(hba, in exynos7_ufs_pre_link()
169 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); in exynos7_ufs_pre_link()
171 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12)); in exynos7_ufs_pre_link()
172 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); in exynos7_ufs_pre_link()
173 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); in exynos7_ufs_pre_link()
174 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); in exynos7_ufs_pre_link()
176 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val); in exynos7_ufs_pre_link()
183 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link() local
186 exynos_ufs_enable_ov_tm(hba); in exynos7_ufs_post_link()
188 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); in exynos7_ufs_post_link()
189 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); in exynos7_ufs_post_link()
190 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
193 exynos_ufs_disable_ov_tm(hba); in exynos7_ufs_post_link()
195 exynos_ufs_enable_dbg_mode(hba); in exynos7_ufs_post_link()
196 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8); in exynos7_ufs_post_link()
197 exynos_ufs_disable_dbg_mode(hba); in exynos7_ufs_post_link()
213 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change() local
216 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1); in exynos7_ufs_post_pwr_change()
219 exynos_ufs_enable_dbg_mode(hba); in exynos7_ufs_post_pwr_change()
220 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1); in exynos7_ufs_post_pwr_change()
221 exynos_ufs_disable_dbg_mode(hba); in exynos7_ufs_post_pwr_change()
259 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info() local
260 struct list_head *head = &hba->clk_list_head; in exynos_ufs_get_clk_info()
280 dev_err(hba->dev, "failed to get clk info\n"); in exynos_ufs_get_clk_info()
301 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); in exynos_ufs_get_clk_info()
326 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div() local
329 ufshcd_dme_set(hba, in exynos_ufs_set_pwm_clk_div()
335 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div() local
356 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx); in exynos_ufs_calc_pwm_clk_div()
357 dev_err(hba->dev, in exynos_ufs_calc_pwm_clk_div()
410 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr() local
416 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_phy_time_attr()
419 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), in exynos_ufs_config_phy_time_attr()
421 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), in exynos_ufs_config_phy_time_attr()
423 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
425 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
427 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
429 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
431 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
433 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
438 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), in exynos_ufs_config_phy_time_attr()
440 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), in exynos_ufs_config_phy_time_attr()
442 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), in exynos_ufs_config_phy_time_attr()
444 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
446 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
448 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
450 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
452 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
455 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), in exynos_ufs_config_phy_time_attr()
459 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_phy_time_attr()
464 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr() local
468 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_phy_cap_attr()
471 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
474 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
477 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
480 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
483 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
486 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
493 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
497 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
502 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
509 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
515 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
521 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
528 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_phy_cap_attr()
533 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt() local
542 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE); in exynos_ufs_establish_connt()
545 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID); in exynos_ufs_establish_connt()
546 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), TRUE); in exynos_ufs_establish_connt()
547 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID); in exynos_ufs_establish_connt()
548 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID); in exynos_ufs_establish_connt()
549 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS); in exynos_ufs_establish_connt()
550 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS); in exynos_ufs_establish_connt()
551 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); in exynos_ufs_establish_connt()
574 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask() local
596 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_sync_pattern_mask()
599 ufshcd_dme_set(hba, in exynos_ufs_config_sync_pattern_mask()
602 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_sync_pattern_mask()
605 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, in exynos_ufs_pre_pwr_mode() argument
609 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_pwr_mode()
657 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); in exynos_ufs_pre_pwr_mode()
658 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); in exynos_ufs_pre_pwr_mode()
659 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); in exynos_ufs_pre_pwr_mode()
667 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba, in exynos_ufs_post_pwr_mode() argument
671 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_pwr_mode()
703 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); in exynos_ufs_post_pwr_mode()
708 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba, in exynos_ufs_specify_nexus_t_xfer_req() argument
711 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_xfer_req()
722 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba, in exynos_ufs_specify_nexus_t_tm_req() argument
725 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_tm_req()
746 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init() local
751 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), in exynos_ufs_phy_init()
753 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), in exynos_ufs_phy_init()
763 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in exynos_ufs_phy_init()
778 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro() local
780 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), in exynos_ufs_config_unipro()
782 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), in exynos_ufs_config_unipro()
784 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), in exynos_ufs_config_unipro()
809 static int exynos_ufs_pre_link(struct ufs_hba *hba) in exynos_ufs_pre_link() argument
811 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_link()
841 static int exynos_ufs_post_link(struct ufs_hba *hba) in exynos_ufs_post_link() argument
843 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_link()
853 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
854 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
858 ufshcd_dme_set(hba, in exynos_ufs_post_link()
862 exynos_ufs_enable_dbg_mode(hba); in exynos_ufs_post_link()
863 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY), in exynos_ufs_post_link()
865 exynos_ufs_disable_dbg_mode(hba); in exynos_ufs_post_link()
868 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), in exynos_ufs_post_link()
872 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in exynos_ufs_post_link()
878 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), in exynos_ufs_post_link()
881 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in exynos_ufs_post_link()
886 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0); in exynos_ufs_post_link()
890 dev_warn(hba->dev, in exynos_ufs_post_link()
943 static int exynos_ufs_init(struct ufs_hba *hba) in exynos_ufs_init() argument
945 struct device *dev = hba->dev; in exynos_ufs_init()
992 ufs->hba = hba; in exynos_ufs_init()
997 hba->priv = (void *)ufs; in exynos_ufs_init()
998 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_init()
1017 hba->priv = NULL; in exynos_ufs_init()
1021 static int exynos_ufs_host_reset(struct ufs_hba *hba) in exynos_ufs_host_reset() argument
1023 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_host_reset()
1037 dev_err(hba->dev, "timeout host sw-reset\n"); in exynos_ufs_host_reset()
1045 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba) in exynos_ufs_dev_hw_reset() argument
1047 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_dev_hw_reset()
1054 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter) in exynos_ufs_pre_hibern8() argument
1056 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_hibern8()
1087 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter) in exynos_ufs_post_hibern8() argument
1089 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_hibern8()
1100 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode); in exynos_ufs_post_hibern8()
1102 dev_warn(hba->dev, "%s: power mode change\n", __func__); in exynos_ufs_post_hibern8()
1103 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf; in exynos_ufs_post_hibern8()
1104 hba->pwr_info.pwr_tx = cur_mode & 0xf; in exynos_ufs_post_hibern8()
1105 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); in exynos_ufs_post_hibern8()
1118 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba, in exynos_ufs_hce_enable_notify() argument
1121 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_hce_enable_notify()
1126 ret = exynos_ufs_host_reset(hba); in exynos_ufs_hce_enable_notify()
1129 exynos_ufs_dev_hw_reset(hba); in exynos_ufs_hce_enable_notify()
1141 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, in exynos_ufs_link_startup_notify() argument
1148 ret = exynos_ufs_pre_link(hba); in exynos_ufs_link_startup_notify()
1151 ret = exynos_ufs_post_link(hba); in exynos_ufs_link_startup_notify()
1158 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, in exynos_ufs_pwr_change_notify() argument
1167 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, in exynos_ufs_pwr_change_notify()
1171 ret = exynos_ufs_post_pwr_mode(hba, NULL, dev_req_params); in exynos_ufs_pwr_change_notify()
1178 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba, in exynos_ufs_hibern8_notify() argument
1184 exynos_ufs_pre_hibern8(hba, enter); in exynos_ufs_hibern8_notify()
1187 exynos_ufs_post_hibern8(hba, enter); in exynos_ufs_hibern8_notify()
1192 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) in exynos_ufs_suspend() argument
1194 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_suspend()
1196 if (!ufshcd_is_link_active(hba)) in exynos_ufs_suspend()
1202 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) in exynos_ufs_resume() argument
1204 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_resume()
1206 if (!ufshcd_is_link_active(hba)) in exynos_ufs_resume()
1241 struct ufs_hba *hba = platform_get_drvdata(pdev); in exynos_ufs_remove() local
1244 ufshcd_remove(hba); in exynos_ufs_remove()