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Lines Matching refs:RegValue

4380 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )  in usc_OutDmaReg()  argument
4386 outw( RegValue, info->io_base ); in usc_OutDmaReg()
4435 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutReg() argument
4438 outw( RegValue, info->io_base + CCAR ); in usc_OutReg()
4475 u16 RegValue; in usc_set_sdlc_mode() local
4488 RegValue=usc_InReg(info,TMDR); in usc_set_sdlc_mode()
4489 PreSL1660 = (RegValue == IUSC_PRE_SL1660); in usc_set_sdlc_mode()
4505 RegValue = 0x8e06; in usc_set_sdlc_mode()
4526 RegValue = 0x0001; /* Set Receive mode = external sync */ in usc_set_sdlc_mode()
4543 RegValue |= 0x0400; in usc_set_sdlc_mode()
4547 RegValue = 0x0606; in usc_set_sdlc_mode()
4550 RegValue |= BIT14; in usc_set_sdlc_mode()
4552 RegValue |= BIT15; in usc_set_sdlc_mode()
4554 RegValue |= BIT15 | BIT14; in usc_set_sdlc_mode()
4558 RegValue |= BIT13; in usc_set_sdlc_mode()
4563 RegValue |= BIT12; in usc_set_sdlc_mode()
4569 RegValue |= BIT4; in usc_set_sdlc_mode()
4572 usc_OutReg( info, CMR, RegValue ); in usc_set_sdlc_mode()
4573 info->cmr_value = RegValue; in usc_set_sdlc_mode()
4590 RegValue = 0x0500; in usc_set_sdlc_mode()
4593 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; in usc_set_sdlc_mode()
4594 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; in usc_set_sdlc_mode()
4595 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; in usc_set_sdlc_mode()
4596 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4597 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4598 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4599 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4603 RegValue |= BIT9; in usc_set_sdlc_mode()
4605 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4607 usc_OutReg( info, RMR, RegValue ); in usc_set_sdlc_mode()
4638 RegValue = usc_InReg( info, RICR ) & 0xc0; in usc_set_sdlc_mode()
4640 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); in usc_set_sdlc_mode()
4662 RegValue = 0x0400; in usc_set_sdlc_mode()
4665 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; in usc_set_sdlc_mode()
4666 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; in usc_set_sdlc_mode()
4667 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; in usc_set_sdlc_mode()
4668 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4669 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4670 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
4671 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; in usc_set_sdlc_mode()
4675 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()
4677 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
4679 usc_OutReg( info, TMR, RegValue ); in usc_set_sdlc_mode()
4743 RegValue = 0x0f40; in usc_set_sdlc_mode()
4746 RegValue |= 0x0003; /* RxCLK from DPLL */ in usc_set_sdlc_mode()
4748 RegValue |= 0x0004; /* RxCLK from BRG0 */ in usc_set_sdlc_mode()
4750 RegValue |= 0x0006; /* RxCLK from TXC Input */ in usc_set_sdlc_mode()
4752 RegValue |= 0x0007; /* RxCLK from Port1 */ in usc_set_sdlc_mode()
4755 RegValue |= 0x0018; /* TxCLK from DPLL */ in usc_set_sdlc_mode()
4757 RegValue |= 0x0020; /* TxCLK from BRG0 */ in usc_set_sdlc_mode()
4759 RegValue |= 0x0038; /* RxCLK from TXC Input */ in usc_set_sdlc_mode()
4761 RegValue |= 0x0030; /* TxCLK from Port0 */ in usc_set_sdlc_mode()
4763 usc_OutReg( info, CMCR, RegValue ); in usc_set_sdlc_mode()
4781 RegValue = 0x0000; in usc_set_sdlc_mode()
4795 RegValue |= BIT10; in usc_set_sdlc_mode()
4799 RegValue |= BIT11; in usc_set_sdlc_mode()
4832 RegValue |= BIT4; /* enable BRG1 */ in usc_set_sdlc_mode()
4838 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; in usc_set_sdlc_mode()
4840 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; in usc_set_sdlc_mode()
4842 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
4846 usc_OutReg( info, HCR, RegValue ); in usc_set_sdlc_mode()
4982 RegValue = 0x8080; in usc_set_sdlc_mode()
4985 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; in usc_set_sdlc_mode()
4986 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; in usc_set_sdlc_mode()
4987 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; in usc_set_sdlc_mode()
4991 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break; in usc_set_sdlc_mode()
4992 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break; in usc_set_sdlc_mode()
4993 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break; in usc_set_sdlc_mode()
4994 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()
4997 usc_OutReg( info, CCR, RegValue ); in usc_set_sdlc_mode()
5678 u16 RegValue; in usc_set_async_mode() local
5700 RegValue = 0; in usc_set_async_mode()
5702 RegValue |= BIT14; in usc_set_async_mode()
5703 usc_OutReg( info, CMR, RegValue ); in usc_set_async_mode()
5718 RegValue = 0; in usc_set_async_mode()
5721 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
5724 RegValue |= BIT5; in usc_set_async_mode()
5726 RegValue |= BIT6; in usc_set_async_mode()
5729 usc_OutReg( info, RMR, RegValue ); in usc_set_async_mode()
5775 RegValue = 0; in usc_set_async_mode()
5778 RegValue |= BIT4 | BIT3 | BIT2; in usc_set_async_mode()
5781 RegValue |= BIT5; in usc_set_async_mode()
5783 RegValue |= BIT6; in usc_set_async_mode()
5786 usc_OutReg( info, TMR, RegValue ); in usc_set_async_mode()