Lines Matching refs:BIT5
395 #define IRQ_DCD BIT5
2143 if (status & (BIT5 + BIT4)) { in isr_rdma()
2168 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4079 case 7: val |= BIT5; break; in async_mode()
4080 case 8: val |= BIT5 + BIT4; break; in async_mode()
4119 case 7: val |= BIT5; break; in async_mode()
4120 case 8: val |= BIT5 + BIT4; break; in async_mode()
4243 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; in sync_mode()
4245 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4331 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
4338 val |= BIT5; /* 001, txclk = RXC Input */ in sync_mode()
4416 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; in tx_set_idle()
4421 tcr &= ~(BIT5 + BIT4); in tx_set_idle()
4483 val |= BIT5; /* 0010 */ in msc_set_vcr()
4486 val |= BIT7 + BIT6 + BIT5; /* 1110 */ in msc_set_vcr()
4892 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; in register_test()