Lines Matching +full:0 +full:x0200
23 #define HW_REV_REG 0xC004
29 #define USB_CTL_REG(x) ((x) ? 0xC0AA : 0xC08A)
31 #define LOW_SPEED_PORT(x) ((x) ? 0x0800 : 0x0400)
32 #define HOST_MODE 0x0200
33 #define PORT_RES_EN(x) ((x) ? 0x0100 : 0x0080)
34 #define SOF_EOP_EN(x) ((x) ? 0x0002 : 0x0001)
37 #define USB_STAT_REG(x) ((x) ? 0xC0B0 : 0xC090)
39 #define EP0_IRQ_FLG 0x0001
40 #define EP1_IRQ_FLG 0x0002
41 #define EP2_IRQ_FLG 0x0004
42 #define EP3_IRQ_FLG 0x0008
43 #define EP4_IRQ_FLG 0x0010
44 #define EP5_IRQ_FLG 0x0020
45 #define EP6_IRQ_FLG 0x0040
46 #define EP7_IRQ_FLG 0x0080
47 #define RESET_IRQ_FLG 0x0100
48 #define SOF_EOP_IRQ_FLG 0x0200
49 #define ID_IRQ_FLG 0x4000
50 #define VBUS_IRQ_FLG 0x8000
56 #define HOST_CTL_REG(x) ((x) ? 0xC0A0 : 0xC080)
58 #define PREAMBLE_EN 0x0080 /* Preamble enable */
59 #define SEQ_SEL 0x0040 /* Data Toggle Sequence Bit Select */
60 #define ISO_EN 0x0010 /* Isochronous enable */
61 #define ARM_EN 0x0001 /* Arm operation */
64 #define HOST_IRQ_EN_REG(x) ((x) ? 0xC0AC : 0xC08C)
66 #define SOF_EOP_IRQ_EN 0x0200 /* SOF/EOP Interrupt Enable */
67 #define SOF_EOP_TMOUT_IRQ_EN 0x0800 /* SOF/EOP Timeout Interrupt Enable */
68 #define ID_IRQ_EN 0x4000 /* ID interrupt enable */
69 #define VBUS_IRQ_EN 0x8000 /* VBUS interrupt enable */
70 #define DONE_IRQ_EN 0x0001 /* Done Interrupt Enable */
73 #define HOST_STAT_MASK 0x02FD
74 #define PORT_CONNECT_CHANGE(x) ((x) ? 0x0020 : 0x0010)
75 #define PORT_SE0_STATUS(x) ((x) ? 0x0008 : 0x0004)
78 #define HOST_FRAME_REG(x) ((x) ? 0xC0B6 : 0xC096)
80 #define HOST_FRAME_MASK 0x07FF
86 #define DEVICE_N_PORT_SEL(x) ((x) ? 0xC0A4 : 0xC084)
89 #define DEVICE_N_IRQ_EN_REG(x) ((x) ? 0xC0AC : 0xC08C)
92 ? (0x0280 + (ep << 4)) \
93 : (0x0200 + (ep << 4)))
95 ? (0x0286 + (ep << 4)) \
96 : (0x0206 + (ep << 4)))
98 #define DEVICE_N_ADDRESS(dev) ((dev) ? (0xC0AE) : (0xC08E))
106 #define RESET_FLG(x) ((x) ? 0x0200 : 0x0002)
109 #define MBX_OUT_FLG 0x0001 /* Message out available */
110 #define MBX_IN_FLG 0x0100
111 #define ID_FLG 0x4000
112 #define VBUS_FLG 0x8000
115 #define HPI_IRQ_ROUTING_REG 0x0142
117 #define HPI_SWAP_ENABLE(x) ((x) ? 0x0100 : 0x0001)
118 #define RESET_TO_HPI_ENABLE(x) ((x) ? 0x0200 : 0x0002)
119 #define DONE_TO_HPI_ENABLE(x) ((x) ? 0x0008 : 0x0004)
120 #define RESUME_TO_HPI_ENABLE(x) ((x) ? 0x0080 : 0x0040)
121 #define SOFEOP_TO_HPI_EN(x) ((x) ? 0x2000 : 0x0800)
122 #define SOFEOP_TO_CPU_EN(x) ((x) ? 0x1000 : 0x0400)
123 #define ID_TO_HPI_ENABLE 0x4000
124 #define VBUS_TO_HPI_ENABLE 0x8000
127 #define SIEMSG_REG(x) ((x) ? 0x0148 : 0x0144)
129 #define HUSB_TDListDone 0x1000
131 #define SUSB_EP0_MSG 0x0001
132 #define SUSB_EP1_MSG 0x0002
133 #define SUSB_EP2_MSG 0x0004
134 #define SUSB_EP3_MSG 0x0008
135 #define SUSB_EP4_MSG 0x0010
136 #define SUSB_EP5_MSG 0x0020
137 #define SUSB_EP6_MSG 0x0040
138 #define SUSB_EP7_MSG 0x0080
139 #define SUSB_RST_MSG 0x0100
140 #define SUSB_SOF_MSG 0x0200
141 #define SUSB_CFG_MSG 0x0400
142 #define SUSB_SUS_MSG 0x0800
143 #define SUSB_ID_MSG 0x4000
144 #define SUSB_VBUS_MSG 0x8000
151 #define SUSBx_DEV_DESC_VEC(x) ((x) ? 0x00D4 : 0x00B4)
152 #define SUSBx_CONF_DESC_VEC(x) ((x) ? 0x00D6 : 0x00B6)
153 #define SUSBx_STRING_DESC_VEC(x) ((x) ? 0x00D8 : 0x00B8)
155 #define CY_HCD_BUF_ADDR 0x500 /* Base address for host */
156 #define SIE_TD_SIZE 0x200 /* size of the td list */
157 #define SIE_TD_BUF_SIZE 0x400 /* size of the data buffer */
159 #define SIE_TD_OFFSET(host) ((host) ? (SIE_TD_SIZE+SIE_TD_BUF_SIZE) : 0)
163 #define CY_UDC_REQ_HEADER_BASE 0x1100
171 #define CY_UDC_BIOS_REPLACE_BASE 0x1800
172 #define CY_UDC_REQ_BUFFER_BASE 0x2000
173 #define CY_UDC_REQ_BUFFER_SIZE 0x0400
189 * @sie_num: SIE number on chip, starting from 0