Lines Matching full:12
318 #define RT5677_LOUT2_L_DF (0x1 << 12)
319 #define RT5677_LOUT2_L_DF_SFT (12)
332 #define RT5677_BST_MASK1 (0xf << 12)
333 #define RT5677_BST_SFT1 12
377 #define RT5677_ST_HPF_PATH (0x1 << 12)
378 #define RT5677_ST_HPF_PATH_SFT 12
397 #define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
398 #define RT5677_SEL_DAC4_L_SRC_SFT 12
461 #define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
462 #define RT5677_STO1_ADC_R_BST_SFT 12
481 #define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
482 #define RT5677_MONO_ADC_R_BST_SFT 12
489 #define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
490 #define RT5677_STO3_ADC_R_BST_SFT 12
517 #define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
518 #define RT5677_SEL_STO4_ADC1_SFT 12
533 #define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
534 #define RT5677_SEL_STO3_ADC1_SFT 12
549 #define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
550 #define RT5677_SEL_STO2_ADC1_SFT 12
569 #define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
570 #define RT5677_SEL_STO1_ADC1_SFT 12
585 #define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
586 #define RT5677_SEL_MONO_ADC_L1_SFT 12
621 #define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
622 #define RT5677_DAC1_L_STO_L_VOL_SFT 12
651 #define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
652 #define RT5677_DAC2_L_MONO_L_VOL_SFT 12
683 #define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
684 #define RT5677_MONO_L_DD1_L_VOL_SFT 12
717 #define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
718 #define RT5677_MONO_L_DD2_L_VOL_SFT 12
763 #define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
764 #define RT5677_SEL_PDM1_L_SFT 12
788 #define RT5677_PDM1_I2C_ID (0xf << 12)
800 #define RT5677_IF1_ADC_MODE_MASK (0x1 << 12)
801 #define RT5677_IF1_ADC_MODE_SFT 12
802 #define RT5677_IF1_ADC_MODE_I2S (0x0 << 12)
803 #define RT5677_IF1_ADC_MODE_TDM (0x1 << 12)
826 #define RT5677_IF1_DAC0_MASK (0x7 << 12)
827 #define RT5677_IF1_DAC0_SFT 12
836 #define RT5677_IF1_DAC4_MASK (0x7 << 12)
837 #define RT5677_IF1_DAC4_SFT 12
846 #define RT5677_IF2_ADC_MODE_MASK (0x1 << 12)
847 #define RT5677_IF2_ADC_MODE_SFT 12
848 #define RT5677_IF2_ADC_MODE_I2S (0x0 << 12)
849 #define RT5677_IF2_ADC_MODE_TDM (0x1 << 12)
872 #define RT5677_IF2_DAC0_MASK (0x7 << 12)
873 #define RT5677_IF2_DAC0_SFT 12
882 #define RT5677_IF2_DAC4_MASK (0x7 << 12)
883 #define RT5677_IF2_DAC4_SFT 12
904 #define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
905 #define RT5677_DMIC_R_STO1_LH_SFT 12
906 #define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)
907 #define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
988 #define RT5677_PWR_DAC1 (0x1 << 12)
989 #define RT5677_PWR_DAC1_BIT 12
1016 #define RT5677_PWR_DAC_S1F (0x1 << 12)
1017 #define RT5677_PWR_DAC_S1F_BIT 12
1048 #define RT5677_PWR_LO1 (0x1 << 12)
1049 #define RT5677_PWR_LO1_BIT 12
1072 #define RT5677_PWR_SLIM (0x1 << 12)
1073 #define RT5677_PWR_SLIM_BIT 12
1202 #define RT5677_I2S_PD1_MASK (0x7 << 12)
1203 #define RT5677_I2S_PD1_SFT 12
1204 #define RT5677_I2S_PD1_1 (0x0 << 12)
1205 #define RT5677_I2S_PD1_2 (0x1 << 12)
1206 #define RT5677_I2S_PD1_3 (0x2 << 12)
1207 #define RT5677_I2S_PD1_4 (0x3 << 12)
1208 #define RT5677_I2S_PD1_6 (0x4 << 12)
1209 #define RT5677_I2S_PD1_8 (0x5 << 12)
1210 #define RT5677_I2S_PD1_12 (0x6 << 12)
1211 #define RT5677_I2S_PD1_16 (0x7 << 12)
1256 #define RT5677_I2S_PD5_MASK (0x7 << 12)
1257 #define RT5677_I2S_PD5_SFT 12
1258 #define RT5677_I2S_PD5_1 (0x0 << 12)
1259 #define RT5677_I2S_PD5_2 (0x1 << 12)
1260 #define RT5677_I2S_PD5_3 (0x2 << 12)
1261 #define RT5677_I2S_PD5_4 (0x3 << 12)
1262 #define RT5677_I2S_PD5_6 (0x4 << 12)
1263 #define RT5677_I2S_PD5_8 (0x5 << 12)
1264 #define RT5677_I2S_PD5_12 (0x6 << 12)
1265 #define RT5677_I2S_PD5_16 (0x7 << 12)
1335 #define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)
1336 #define RT5677_PLL_M_SFT 12
1382 #define RT5677_PLL2_SRC_MASK (0x7 << 12)
1383 #define RT5677_PLL2_SRC_SFT 12
1384 #define RT5677_PLL2_SRC_MCLK (0x0 << 12)
1385 #define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
1386 #define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)
1387 #define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
1388 #define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)
1389 #define RT5677_PLL2_SRC_RCCLK (0x5 << 12)
1390 #define RT5677_PLL2_SRC_SLIM (0x6 << 12)
1409 #define RT5677_DA_STO_CLK_SEL_MASK (0xf << 12)
1410 #define RT5677_DA_STO_CLK_SEL_SFT 12
1417 #define RT5677_DA_MONO3L_CLK_SEL_MASK (0xf << 12)
1418 #define RT5677_DA_MONO3L_CLK_SEL_SFT 12
1427 #define RT5677_AD_STO1_CLK_SEL_MASK (0xf << 12)
1428 #define RT5677_AD_STO1_CLK_SEL_SFT 12
1437 #define RT5677_AD_MONOL_CLK_SEL_MASK (0xf << 12)
1438 #define RT5677_AD_MONOL_CLK_SEL_SFT 12
1443 #define RT5677_DSP_OB_0_3_CLK_SEL_MASK (0xf << 12)
1444 #define RT5677_DSP_OB_0_3_CLK_SEL_SFT 12
1449 #define RT5677_I2S1_CLK_SEL_MASK (0xf << 12)
1450 #define RT5677_I2S1_CLK_SEL_SFT 12
1491 #define RT5677_IB01_SRC_MASK (0x7 << 12)
1492 #define RT5677_IB01_SRC_SFT 12
1501 #define RT5677_IB7_SRC_MASK (0x7 << 12)
1502 #define RT5677_IB7_SRC_SFT 12
1523 #define RT5677_SEL_GPIO_JD2_MASK (0x3 << 12)
1524 #define RT5677_SEL_GPIO_JD2_SFT 12
1535 #define RT5677_INV_GPIO_JD1 (0x1 << 12)
1536 #define RT5677_INV_GPIO_JD1_SFT 12
1599 #define RT5677_GPIO5_P_MASK (0x1 << 12)
1600 #define RT5677_GPIO5_P_SFT 12
1601 #define RT5677_GPIO5_P_NOR (0x0 << 12)
1602 #define RT5677_GPIO5_P_INV (0x1 << 12)
1679 #define RT5677_DSP_IB_6_H (0x1 << 12)
1680 #define RT5677_DSP_IB_6_H_SFT 12
1791 RT5677_AD_MONO_R_FILTER = (0x1 << 12),