23 #define BDW_DSP_BAR 0
31 #define IRAM_OFFSET     0xA0000
33 #define DRAM_OFFSET     0x00000
35 #define SHIM_OFFSET     0xFB000
36 #define SHIM_SIZE       0x100
37 #define MBOX_OFFSET     0x9E000
38 #define MBOX_SIZE       0x1000
39 #define MBOX_DUMP_SIZE 0x30
40 #define EXCEPT_OFFSET	0x800
41 #define EXCEPT_MAX_HDR_SIZE	0x400
44 #define DMAC0_OFFSET    0xFE000
45 #define DMAC1_OFFSET    0xFF000
46 #define DMAC_SIZE       0x420
47 #define SSP0_OFFSET     0xFC000
48 #define SSP1_OFFSET     0xFD000
49 #define SSP_SIZE	0x100
53 #define BDW_PANIC_OFFSET(x)	((x) & 0xFFFF)
82 	/* set opportunistic mode on engine 0,1 for all channels */  in bdw_run()
85 				SHIM_HMDC_HDDA_E1_ALLCH, 0);  in bdw_run()
89 					 SHIM_CSR_STALL, 0x0);  in bdw_run()
110 	return 0;  in bdw_reset()
118 	/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */  in bdw_set_dsp_D0()
121 					 PCI_VDRTCL2_DTCGE, 0);  in bdw_set_dsp_D0()
129 					 PCI_PMCS_PS_MASK, 0);  in bdw_set_dsp_D0()
135 		if (reg == 0)  in bdw_set_dsp_D0()
145 	 * select SSP1 19.2MHz base clock, SSP clock 0,  in bdw_set_dsp_D0()
150 					 SHIM_CSR_LPCS, 0x0);  in bdw_set_dsp_D0()
182 					 PCI_VDRTCL2_APLLSE_MASK, 0);  in bdw_set_dsp_D0()
190 					 0xfffffffC, 0x0);  in bdw_set_dsp_D0()
197 	/* set on-demond mode on engine 0,1 for all channels */  in bdw_set_dsp_D0()
206 				(SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0);  in bdw_set_dsp_D0()
209 				SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0);  in bdw_set_dsp_D0()
212 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);  in bdw_set_dsp_D0()
213 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);  in bdw_set_dsp_D0()
214 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);  in bdw_set_dsp_D0()
215 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);  in bdw_set_dsp_D0()
217 	return 0;  in bdw_set_dsp_D0()
234 		dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",  in bdw_get_registers()
265 		"error: ipc host -> DSP: pending %s complete %s raw 0x%8.8x\n",  in bdw_dump()
269 		"error: mask host: pending %s complete %s raw 0x%8.8x\n",  in bdw_dump()
273 		"error: ipc DSP -> host: pending %s complete %s raw 0x%8.8x\n",  in bdw_dump()
277 		"error: mask DSP: pending %s complete %s raw 0x%8.8x\n",  in bdw_dump()
368 	return 0;  in bdw_send_msg()
375 	int ret = 0;  in bdw_get_reply()
390 	if (reply.error < 0) {  in bdw_get_reply()
402 		if (msg->reply_size > 0)  in bdw_get_reply()
429 					 SHIM_IMRX_BUSY, 0);  in bdw_host_done()
436 					 SHIM_IPCX_DONE, 0);  in bdw_dsp_done()
440 					 SHIM_IMRX_DONE, 0);  in bdw_dsp_done()
468 	dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);  in bdw_probe()
472 			"error: failed to ioremap LPE base 0x%x size 0x%x\n",  in bdw_probe()
495 	dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);  in bdw_probe()
499 			"error: failed to ioremap PCI base 0x%x size 0x%x\n",  in bdw_probe()
507 	if (sdev->ipc_irq < 0)  in bdw_probe()
514 	if (ret < 0) {  in bdw_probe()
522 	if (ret < 0) {  in bdw_probe()
529 	if (ret < 0) {  in bdw_probe()
535 	snd_sof_dsp_mailbox_init(sdev, MBOX_OFFSET, MBOX_SIZE, 0, 0);  in bdw_probe()