Lines Matching full:execute
199 P1 loads from flag before loading from buf, since CPUs execute
210 execute before itself, the specified outcome is impossible.
260 important assumption that CPUs execute instructions in the same order
776 First, a fence forces the CPU to execute various instructions in
781 the CPU to execute all po-earlier instructions before any
784 smp_rmb() forces the CPU to execute all po-earlier loads
787 smp_wmb() forces the CPU to execute all po-earlier stores
791 execute the load associated with the fence (e.g., the load
796 execute all po-earlier instructions before the store
962 There are many situations where a CPU is obliged to execute two
970 memory accesses with X ->po Y; then the CPU must execute X before Y if
996 a store W will force the CPU to execute R before W. This is very
1011 To be fair about it, all Linux-supported architectures do execute
1028 this situation we know it is possible for the CPU to execute R' before
1030 cannot execute R' before R, because it cannot forward the value before
1055 access the same location), the CPU is obliged to execute W after R.
1104 to ptr does. And since P1 can't execute its second load
1126 effect of the fence is to cause the CPU not to execute any po-later
1147 share this property: They do not allow the CPU to execute any po-later
1164 execute in a certain order. hb includes the ppo relation and two
1175 execute before W does.
1180 they execute on different CPUs, and W comes before W' in the coherence
1182 execute before W, because the decision as to which store overwrites
1186 doesn't mean that W has to execute after R. All that's necessary is
1281 P1 must execute its second load before the first. Indeed, if the load
1293 Since an instruction can't execute before itself, we are forced to
1335 before P2's load and store execute, P2's smp_store_release()
1341 in the order they execute means that it must not have cycles. This
1373 And because of the hb links, we know that Z will execute before F.
1380 The existence of a pb link from E to F implies that E must execute
1421 cycle in pb, which is not possible since an instruction cannot execute
1426 they execute means that it cannot have cycles. This requirement is
1495 execute an smp_mb() fence after the end of the critical section and
1498 synchronize_rcu() routine will execute an smp_mb() fence at its start
1561 before any instruction po-after F can execute. (However, it does not
1562 imply that E must execute before F; in fact, each synchronize_rcu()
1588 executing and hence before any instruction po-after F can execute.
1614 details; the end result is that E ->rb F implies E must execute
1762 This requires P0 and P2 to execute their loads and stores out of
1818 execute before any instruction po-after the lock-acquire. This would
1846 therefore the load of x must execute before the load of y. Thus we
1999 5. they execute concurrently.
2008 which may execute concurrently; if it does then the LKMM says there is
2015 execute concurrently. The LKMM takes a conservative attitude,
2019 If two memory accesses aren't concurrent then one must execute before
2036 requires not only that X must execute before Y but also that X must
2071 po-after the barrier can execute.
2100 provides an xb link from Z to Y (i.e., it forces Z to execute before
2144 then execute some of those accesses out of program order, but we
2200 therefore any loads among those instructions will execute
2204 executes (assuming V does execute), ruling out the possibility of a
2268 *p; the marked load must execute before any of the machine
2370 before the second can execute. Therefore the two stores cannot be
2475 it is not guaranteed that the load from y will execute after the
2495 for this source code in which W' could execute before R. Just as with