Lines Matching refs:stores
102 device, stores it in a buffer, and sets a flag to indicate the buffer
134 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
140 This pattern of memory accesses, where one CPU stores values to two
197 it, as loads can obtain values only from earlier stores.
202 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
206 P0 stores 1 to buf before storing 1 to flag, since it executes
222 each CPU stores to its own shared location and then loads from the
270 W: P0 stores 1 to flag executes before
273 Z: P0 stores 1 to buf executes before
274 W: P0 stores 1 to flag.
296 Write events correspond to stores to shared memory, such as
398 executed before either of the stores to y. However, a compiler could
399 lift the stores out of the conditional, transforming the code into
549 from both of P0's stores. It is possible to handle mixed-size and
561 shared memory, the stores to that location must form a single global
567 the stores to x is simply the order in which the stores overwrite one
574 stores reach x's location in memory (or if you prefer a more
575 hardware-centric view, the order in which the stores get written to
585 and W' are two stores, then W ->co W'.
672 just like with the rf relation, we distinguish between stores that
673 occur on the same CPU (internal coherence order, or coi) and stores
676 On the other hand, stores to different memory locations are never
707 stores to x, there would also be fr links from the READ_ONCE() to
733 only internal operations. However, loads, stores, and fences involve
758 time to process the stores that it receives, and a store can't be used
760 most architectures, the local caches process stores in
787 smp_wmb() forces the CPU to execute all po-earlier stores
788 before any po-later stores;
801 propagates stores. When a fence instruction is executed on CPU C:
803 For each other CPU C', smp_wmb() forces all po-earlier stores
804 on C to propagate to C' before any po-later stores do.
808 stores executed on C) is forced to propagate to C' before the
812 executed (including all po-earlier stores on C) is forced to
817 affects stores from other CPUs that propagate to CPU C before the
818 fence is executed, as well as stores that are executed on C before the
821 A-cumulative; they only affect the propagation of stores that are
837 E and F are both stores on the same CPU and an smp_wmb() fence
846 The operational model requires that whenever W and W' are both stores
867 operations really are atomic, that is, no other stores can
873 Propagation: This requires that certain stores propagate to
895 According to the principle of cache coherence, the stores to any fixed
935 CPU 0 stores 14 to x;
936 CPU 1 stores 14 to x;
950 there must not be any stores coming between W' and W in the coherence
976 X and Y are both stores and an smp_wmb() fence occurs between
1110 stores do reach P1's local cache in the proper order, it can happen
1119 incoming stores in FIFO order. By contrast, other architectures
1128 the stores it has already received. Thus, if the code was changed to:
1149 outstanding stores have been processed by the local cache. In the
1151 po-earlier stores to propagate to every other CPU in the system; then
1152 it has to wait for the local cache to process all the stores received
1153 as of that time -- not just the stores received when the strong fence
1179 W ->coe W'. This means that W and W' are stores to the same location,
1183 the other is made later by the memory subsystem. When the stores are
1225 read from different stores:
1273 stores. If r1 = 1 and r2 = 0 at the end then there is a prop link
1336 guarantees that the stores to x and y both propagate to P0 before the
1491 In the kernel's implementations of RCU, the requirements for stores
1762 This requires P0 and P2 to execute their loads and stores out of
1876 stores W and W' occur po-before the lock-release and po-after the
2060 cumul-fence memory barriers force stores that are po-before
2061 the barrier to propagate to other CPUs before stores that are
2068 strong-fence memory barriers force stores that are po-before
2220 (i.e., smp_rmb()) and some affect only stores (smp_wmb()); otherwise
2302 stores will propagate to P1 in that order. However, rcu_dereference()
2358 Do the plain stores to y race? Clearly not if P1 reads a non-zero
2370 before the second can execute. Therefore the two stores cannot be
2375 race-candidate stores W and W', where W ->co W', the LKMM says the
2376 stores don't race if W can be linked to W' by a
2559 will self-deadlock in the executions where it stores 36 in y.