Lines Matching +full:0 +full:x10020000
2 index 1877da816..0b45060b7 100644
188 @@ -0,0 +1,240 @@
218 + #size-cells = <0>;
220 + cpu@0 {
223 + reg = <0>;
261 + opp-freq = <0 1 2 3 4>;
271 + reg = <0x80000000 0x40000000>;
309 + spidev@0 {
311 + reg = <0>;
312 + pl022,interface = <0>;
313 + pl022,com-mode = <0>;
322 + spidev@0 {
324 + reg = <0>;
325 + pl022,interface = <0>;
326 + pl022,com-mode = <0>;
333 + pl022,interface = <0>;
334 + pl022,com-mode = <0>;
341 + pl022,interface = <0>;
342 + pl022,com-mode = <0>;
434 @@ -0,0 +1,690 @@
489 + reg = <0x20030000 0x1000>;
495 + #address-cells = <0>;
498 + reg = <0x20301000 0x1000>, <0x20302000 0x100>;
503 + reg = <0x20050000 0x1000>;
510 + offset = <0x4>;
511 + mask = <0xdeadbeef>;
524 + interrupts = <0 32 4>;
535 + reg = <0x20080000 0x1000>;
536 + interrupts = <0 8 4>;
544 + reg = <0x20090000 0x1000>;
545 + interrupts = <0 9 4>;
553 + reg = <0x200a0000 0x1000>;
554 + interrupts = <0 10 4>;
562 + reg = <0x20230000 0x1000>;
563 + interrupts = <0 11 4>;
573 + reg = <0x20030000 0x10000>, <0x20120000 0x10000>,
574 + <0x20050000 0x10000>;
575 + #phy-cells = <0>;
578 + ehci@0x100b0000 {
580 + reg = <0x100b0000 0x10000>;
581 + interrupts = <0 21 4>;
588 + ohci@0x100a0000 {
590 + reg = <0x100a0000 0x10000>;
591 + interrupts = <0 22 4>;
598 + hiudc@0x10080000 {
600 + reg = <0x10080000 0x10000>;
601 + interrupts = <0 23 4>;
609 + interrupts = <0 3 4>;
610 + reg = <0x20000000 0x1000>;
621 + interrupts = <0 4 4>;
622 + reg = <0x20010000 0x1000>;
632 + reg = <0x10060000 0x1000>;
633 + interrupts = <0 5 4>;
636 + resets = <&clock 0xd8 4>;
644 + reg = <0x200d0000 0x100>;
645 + interrupts = <0 14 4>;
648 + io-size = <0x1000>;
649 + id = <0>;
655 + reg = <0x20240000 0x100>;
656 + interrupts = <0 57 4>;
659 + io-size = <0x1000>;
666 + reg = <0x20250000 0x100>;
667 + interrupts = <0 58 4>;
670 + io-size = <0x1000>;
677 + arm,primecell-periphid = <0x00800022>;
678 + reg = <0x200c0000 0x1000>;
679 + interrupts = <0 12 4>;
684 + #size-cells = <0>;
689 + arm,primecell-periphid = <0x00800022>;
690 + reg = <0x200e0000 0x1000>, <0x20120004 0x4>;
691 + interrupts = <0 13 4>;
696 + #size-cells = <0>;
698 + hisi,spi_cs_mask_bit = <0x0c000000>;
703 + interrupts = <0 17 4>;
704 + reg = <0x10010000 0x1000>, <0x58000000 0x1000000>;
710 + #size-cells = <0>;
720 + reg = <0x10040000 0x1000>, <0x54000000 0x10000>;
726 + #size-cells = <0>;
736 + reg = <0x10000000 0x1000>, <0x50000000 0x10000>;
742 + #size-cells = <0>;
752 + reg = <0x20140000 0x10000>;
753 + interrupts = <0 47 4>;
762 + reg = <0x20150000 0x10000>;
763 + interrupts = <0 48 4>;
772 + reg = <0x20160000 0x10000>;
773 + interrupts = <0 49 4>;
782 + reg = <0x20170000 0x10000>;
783 + interrupts = <0 50 4>;
792 + reg = <0x20180000 0x10000>;
793 + interrupts = <0 51 4>;
802 + reg = <0x20190000 0x10000>;
803 + interrupts = <0 52 4>;
812 + reg = <0x201a0000 0x10000>;
813 + interrupts = <0 53 4>;
822 + reg = <0x201b0000 0x10000>;
823 + interrupts = <0 54 4>;
832 + reg = <0x201c0000 0x10000>;
833 + interrupts = <0 55 4>;
842 + reg = <0x201d0000 0x10000>;
843 + interrupts = <0 55 4>;
852 + reg = <0x201e0000 0x10000>;
853 + interrupts = <0 54 4>;
862 + reg = <0x201f0000 0x10000>;
863 + interrupts = <0 53 4>;
872 + reg = <0x20200000 0x10000>;
873 + interrupts = <0 52 4>;
882 + reg = <0x20210000 0x10000>;
883 + interrupts = <0 51 4>;
892 + reg = <0x20220000 0x10000>;
893 + interrupts = <0 50 4>;
902 + reg = <0x20260000 0x10000>;
903 + interrupts = <0 49 4>;
912 + reg = <0x20270000 0x1000>;
921 + reg_offset = <0x4>;
929 + reg_offset = <0xC>;
934 + reg = <0x100903c0 0x20>;
940 + #size-cells = <0>;
945 + reg = <0x10090000 0x1000>,<0x200300ec 0x4>;
946 + interrupts = <0 25 4>;
953 + resets = <&clock 0xcc 0>,
954 + <&clock 0xcc 2>;
961 + mmc0: himci.SD@0x206e0000 {
963 + reg = <0x206e0000 0x1000>;
964 + interrupts = <0 19 4>;
967 + resets = <&clock 0xc4 0>;
976 + devid = <0>;
980 + mmc1: himci.SD@0x206f0000 {
982 + reg = <0x206f0000 0x1000>;
983 + interrupts = <0 20 4>;
986 + resets = <&clock 0xc4 8>;
1009 + reg = <0x20030000 0x10000>, <0x20050000 0x10000>,
1010 + <0x20110000 0x10000>, <0x20120000 0x10000>;
1016 + interrupts = <0 39 4>;
1017 + reg = <0x20650000 0x10000>;
1023 + interrupts = <0 45 4>;
1024 + reg = <0x206a0000 0x10000>;
1029 + interrupts = <0 44 4>;
1030 + reg = <0x206c0000 0x10000>;
1035 + interrupts = <0 34 4>;
1036 + reg = <0x20680000 0x10000>;
1041 + interrupts = <0 35 4>;
1042 + reg = <0x20580000 0x10000>, <0x205a0000 0x20000>;
1048 + interrupts = <0 35 4>;
1049 + reg = <0x20580000 0x40000>;
1054 + interrupts = <0 33 4>;
1055 + reg = <0x205c0000 0x10000>;
1060 + interrupts = <0 38 4>;
1061 + reg = <0x20630000 0x10000>;
1066 + interrupts = <0 36 4>;
1067 + reg = <0x20600000 0x10000>;
1072 + interrupts = <0 43 4>;
1073 + reg = <0x20640000 0x10000>;
1078 + interrupts = <0 40 4>;
1079 + reg = <0x20620000 0x10000>;
1084 + interrupts = <0 41 4>;
1085 + reg = <0x20660000 0x10000>;
1090 + interrupts = <0 37 4>;
1091 + reg = <0x20610000 0x10000>;
1096 + reg = <0x20130000 0x10000>;
1101 + reg = <0x20040000 0x10000>;
1107 + interrupts = <0 7 4>, <0 56 4>;
1109 + reg = <0x20060000 0x10000>;
1114 + interrupts = <0 15 4>;
1115 + reg = <0x20070000 0x10000>;
1120 + interrupts = <0 26 4>;
1121 + reg = <0x100c0000 0x10000>;
1130 @@ -0,0 +1,234 @@
1160 + reg = <0x82000000 0x20000000>;
1212 + spidev@0 {
1214 + reg = <0>;
1215 + pl022,interface = <0>;
1216 + pl022,com-mode = <0>;
1224 + spidev@0 {
1226 + reg = <0>;
1227 + pl022,interface = <0>;
1228 + pl022,com-mode = <0>;
1234 + pl022,interface = <0>;
1235 + pl022,com-mode = <0>;
1243 + spidev@0 {
1245 + reg = <0>;
1246 + pl022,interface = <0>;
1247 + pl022,com-mode = <0>;
1270 + reg = <0>;
1278 + reg = <0>;
1370 @@ -0,0 +1,890 @@
1426 + #size-cells = <0>;
1429 + cpu@0 {
1433 + reg = <0>;
1451 + reg = <0x12010000 0x1000>;
1457 + #address-cells = <0>;
1460 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
1466 + interrupts = <1 13 0xf08>,
1467 + <1 14 0xf08>;
1480 + #clock-cells = <0>;
1486 + #clock-cells = <0>;
1492 + interrupts = <0 54 4>;
1497 + reg = <0x10060000 0x1000>;
1498 + interrupts = <0 28 4>;
1502 + resets = <&clock 0x194 0>;
1506 + devid = <0>;
1514 + reg = <0x10060000 0x1000>;
1515 + interrupts = <0 28 4>;
1519 + resets = <&clock 0x194 0>;
1523 + devid = <0>;
1531 + reg = <0x12020000 0x1000>;
1532 + reboot-offset = <0x4>;
1545 + reg = <0x12000000 0x20>, /* clocksource */
1546 + <0x12000020 0x20>, /* local timer for each cpu */
1547 + <0x12001000 0x20>;
1548 + interrupts = <0 1 4>, /* irq of local timer */
1549 + <0 2 4>;
1559 + interrupts = <0 3 4>;
1560 + reg = <0x12002000 0x1000>;
1568 + arm,primecell-periphid = <0x00141805>;
1569 + reg = <0x12051000 0x1000>;
1577 + reg = <0x12070000 0x10000>;
1579 + resets = <&clock 0x1bc 6>;
1586 + reg = <0x120a0000 0x1000>;
1587 + interrupts = <0 6 4>;
1595 + reg = <0x120a1000 0x1000>;
1596 + interrupts = <0 7 4>;
1608 + reg = <0x120a2000 0x1000>;
1609 + interrupts = <0 8 4>;
1621 + reg = <0x120a4000 0x1000>;
1622 + interrupts = <0 10 4>;
1637 + reg = <0x120b0000 0x1000>;
1640 + dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
1648 + reg = <0x120b1000 0x1000>;
1659 + reg = <0x120b2000 0x1000>;
1670 + reg = <0x120b3000 0x1000>;
1681 + reg = <0x120b4000 0x1000>;
1691 + reg = <0x120b5000 0x1000>;
1702 + reg = <0x120b6000 0x1000>;
1713 + reg = <0x120b7000 0x1000>;
1725 + arm,primecell-periphid = <0x00800022>;
1726 + reg = <0x120c0000 0x1000>;
1727 + interrupts = <0 68 4>;
1731 + #size-cells = <0>;
1741 + arm,primecell-periphid = <0x00800022>;
1742 + reg = <0x120c1000 0x1000>, <0x12030000 0x4>;
1743 + interrupts = <0 69 4>;
1747 + #size-cells = <0>;
1750 + hisi,spi_cs_mask_bit = <0x4>;//0100
1760 + arm,primecell-periphid = <0x00800022>;
1761 + reg = <0x120c2000 0x1000>;
1762 + interrupts = <0 70 4>;
1766 + #size-cells = <0>;
1778 + interrupts = <0 10 4>;
1779 + reg = <0x10300000 0x4000>;
1785 + reg = <0x10011100 0x10>;
1790 + resets = <&clock 0x16c 3>;
1793 + #size-cells = <0>;
1799 + reg = <0x10010000 0x1000>,<0x10011300 0x200>;
1800 + interrupts = <0 32 4>;
1802 + resets = <&clock 0x16c 0>;
1808 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
1811 + max-dma-size = <0x2000>;
1813 + #size-cells = <0>;
1815 + hisfc:spi-nor@0 {
1820 + #size-cells = <0>;
1823 + hisnfc:spi-nand@0 {
1828 + #size-cells = <0>;
1832 + mmc0: himci.eMMC@0x10100000 {
1834 + reg = <0x10100000 0x1000>;
1835 + interrupts = <0 64 4>;
1838 + resets = <&clock 0x148 0>;
1845 + devid = <0>;
1849 + mmc1: himci.SD@0x100f0000 {
1851 + reg = <0x100f0000 0x1000>;
1852 + interrupts = <0 30 4>;
1855 + resets = <&clock 0x160 0>;
1869 + mmc2: himci.SD@0x10020000 {
1871 + reg = <0x10020000 0x1000>;
1872 + interrupts = <0 31 4>;
1875 + resets = <&clock 0x154 0>;
1891 + reg = <0x10060000 0x1000>;
1892 + interrupts = <0 28 4>;
1895 + resets = <&clock 0xc8 4>;
1903 + reg = <0x12010000 0x1000>;
1904 + #phy-cells = <0>;
1908 + xhci_0@0x100e0000 {
1910 + reg = <0x100e0000 0x10000>;
1911 + interrupts = <0 27 4>;
1916 + hidwc3_0@0x100e0000 {
1918 + reg = <0x100e0000 0x10000>;
1919 + interrupts = <0 27 4>;
1927 + reg = <0x120d0000 0x1000>;
1928 + interrupts = <0 16 4>;
1937 + reg = <0x120d1000 0x1000>;
1938 + interrupts = <0 17 4>;
1947 + reg = <0x120d2000 0x1000>;
1948 + interrupts = <0 18 4>;
1957 + reg = <0x120d3000 0x1000>;
1958 + interrupts = <0 19 4>;
1967 + reg = <0x120d4000 0x1000>;
1968 + interrupts = <0 20 4>;
1977 + reg = <0x120d5000 0x1000>;
1978 + interrupts = <0 21 4>;
1987 + reg = <0x120d6000 0x1000>;
1988 + interrupts = <0 22 4>;
1997 + reg = <0x120d7000 0x1000>;
1998 + interrupts = <0 23 4>;
2007 + reg = <0x120d8000 0x1000>;
2008 + interrupts = <0 24 4>;
2017 + reg = <0x120d9000 0x1000>;
2018 + interrupts = <0 25 4>;
2027 + reg = <0x120da000 0x1000>;
2028 + interrupts = <0 26 4>;
2037 + reg = <0x120db000 0x1000>;
2038 + interrupts = <0 80 4>;
2045 + cipher: cipher@0x100c0000 {
2047 + reg = <0x100c0000 0x10000>;
2049 + interrupts = <0 71 4>, <0 72 4>, <0 71 4>, <0 72 4>;
2072 + reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
2073 + <0x12060000 0x10000>, <0x12030000 0x8000>;
2079 + reg = <0x113a0000 0x10000>;
2081 + interrupts = <0 57 4>;
2087 + reg = <0x11270000 0x10000>;
2089 + interrupts = <0 63 4>;
2095 + reg = <0x11300000 0xa0000>, <0x11000000 0x40000>;
2097 + interrupts = <0 56 4>, <0 44 4>;
2103 + reg = <0x11020000 0x20000>;
2105 + interrupts = <0 56 4>;
2111 + reg = <0x11040000 0x10000>;
2113 + interrupts = <0 43 4>;
2119 + reg = <0x11240000 0x10000>;
2121 + interrupts = <0 38 4>;
2127 + reg = <0x11440000 0x40000>;
2129 + interrupts = <0 58 4>;
2135 + reg = <0x11440000 0x40000>, <0x12020000 0x8000>;
2137 + interrupts = <0 59 4>, <0 51 4>;
2143 + reg = <0x11210000 0x10000>;
2145 + interrupts = <0 35 4>;
2155 + reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
2157 + interrupts = <0 42 4>, <0 41 4>;
2163 + reg = <0x11200000 0x10000>;
2165 + interrupts = <0 34 4>;
2171 + reg = <0x11260000 0x10000>;
2173 + interrupts = <0 45 4>;
2179 + reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
2181 + interrupts = <0 40 4>, <0 36 4>;
2191 + reg = <0x10030000 0x10000>;
2193 + interrupts = <0 67 4>;
2199 + reg = <0x11400000 0x30000>;
2205 + reg = <0x113b0000 0x10000>,<0x113c0000 0x10000>,<0x12010000 0x10000>;
2207 + interrupts = <0 55 4>;
2213 + reg = <0x11100000 0x10000>,<0x11110000 0x10000>;
2215 + interrupts = <0 41 4>,<0 42 4>;
2221 + reg = <0x11230000 0x10000>;
2223 + interrupts = <0 37 4>;
2229 + reg = <0x120e0000 0x1000>;
2230 + interrupts = <0 65 4>;
2231 + resets = <&clock 0x1bc 2>;
2237 + reg = <0x120f0000 0x1000>;
2238 + interrupts = <0 75 4>;
2243 + reg = <0x12080000 0x1000>;
2244 + interrupts = <0 5 4>;
2249 + reg = <0x12050000 0x1000>;
2254 …0x11240000 0x10000>,<0x11040000 0x10000>,<0x10030000 0x10000>,<0x113b0000 0x10000>,<0x113c0000 0x1…
2256 …terrupts = <0 67 4>,<0 26 4>,<0 56 4>, <0 44 4>,<0 43 4>,<0 38 4>,<0 58 4>,<0 40 4>,<0 36 4>,<0 37…
2266 @@ -0,0 +1,175 @@
2295 + reg = <0x40000000 0x20000000>;
2330 + spidev@0 {
2332 + reg = <0>;
2333 + pl022,interface = <0>;
2334 + pl022,com-mode = <0>;
2343 + spidev@0 {
2345 + reg = <0>;
2346 + pl022,interface = <0>;
2347 + pl022,com-mode = <0>;
2353 + pl022,interface = <0>;
2354 + pl022,com-mode = <0>;
2380 + reg = <0>;
2388 + reg = <0>;
2447 @@ -0,0 +1,700 @@
2497 + #size-cells = <0>;
2500 + cpu@0 {
2504 + reg = <0>;
2515 + reg = <0x12010000 0x1000>;
2521 + #address-cells = <0>;
2524 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
2530 + interrupts = <1 13 0xf08>,
2531 + <1 14 0xf08>;
2544 + #clock-cells = <0>;
2550 + #clock-cells = <0>;
2556 + interrupts = <0 58 4>;
2561 + reg = <0x100B0000 0x1000>;
2562 + interrupts = <0 38 4>;
2566 + resets = <&clock 0x194 0>;
2570 + devid = <0>;
2579 + reg = <0x100B0000 0x1000>;
2580 + interrupts = <0 38 4>;
2584 + resets = <&clock 0x194 0>;
2588 + devid = <0>;
2597 + reg = <0x12020000 0x1000>;
2598 + reboot-offset = <0x4>;
2611 + interrupts = <0 5 4>;
2612 + reg = <0x12000000 0x1000>;
2621 + interrupts = <0 6 4>;
2622 + reg = <0x12001000 0x1000>;
2630 + reg = <0x12040000 0x1000>;
2631 + interrupts = <0 7 4>;
2639 + reg = <0x12041000 0x1000>;
2640 + interrupts = <0 8 4>;
2652 + reg = <0x12042000 0x1000>;
2653 + interrupts = <0 9 4>;
2668 + reg = <0x12060000 0x1000>;
2676 + reg = <0x12061000 0x1000>;
2684 + reg = <0x12062000 0x1000>;
2691 + arm,primecell-periphid = <0x00800022>;
2692 + reg = <0x12070000 0x1000>;
2693 + interrupts = <0 14 4>;
2697 + #size-cells = <0>;
2707 + arm,primecell-periphid = <0x00800022>;
2708 + reg = <0x12071000 0x1000>, <0x12028000 0x4>;
2709 + interrupts = <0 15 4>;
2713 + #size-cells = <0>;
2716 + hisi,spi_cs_mask_bit = <0x4>;//0100
2726 + reg = <0x10041100 0x10>,<0x12028024 0x4>;
2729 + resets = <&clock 0x16c 3>;
2732 + #size-cells = <0>;
2738 + reg = <0x10040000 0x1000>,<0x10041300 0x200>;
2739 + interrupts = <0 33 4>;
2741 + resets = <&clock 0x16c 0>;
2747 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
2750 + max-dma-size = <0x2000>;
2752 + #size-cells = <0>;
2754 + hisfc:spi-nor@0 {
2759 + #size-cells = <0>;
2762 + hisnfc:spi-nand@0 {
2767 + #size-cells = <0>;
2773 + reg = <0x100C0000 0x10000>;
2776 + mmc0: sdhci@0x10010000 {
2778 + reg = <0x10010000 0x1000>;
2779 + interrupts = <0 30 4>;
2782 + resets = <&clock 0x1f4 27>, <&clock 0x1f4 29>;
2796 + devid = <0>;
2800 + mmc1: sdhci@0x10020000 {
2802 + reg = <0x10020000 0x1000>;
2803 + interrupts = <0 31 4>;
2806 + resets = <&clock 0x22c 27>, <&clock 0x22c 29>;
2819 + usb2_phy0: phy2-0 {
2821 + reg = <0x100D0000 0x1000>,
2822 + <0x12010000 0x1000>,
2823 + <0x100c0000 0x1000>;
2830 + resets = <&clock 0x140 0>,
2831 + <&clock 0x140 1>;
2834 + phy_pll_offset = <0x14>;
2835 + phy_pll_mask = <0x03>;
2836 + phy_pll_val = <0x00>;
2837 + crg_offset = <0x140>;
2838 + crg_defal_mask = <0x0c07>;
2839 + crg_defal_val = <0x0807>;
2840 + vbus_offset = <0x7c>;
2841 + vbus_val = <0x0431>;
2842 + pwren_offset = <0x80>;
2843 + pwren_val = <0x1>;
2844 + ana_cfg_0_eye_val = <0x0433c003>;
2845 + ana_cfg_0_offset = <0x00>;
2846 + ana_cfg_2_eye_val = <0x00120e0f>;
2847 + ana_cfg_2_offset = <0x08>;
2848 + ana_cfg_4_eye_val = <0x655>;
2849 + ana_cfg_4_offset = <0x10>;
2850 + trim_otp_addr = <0x12028004>;
2851 + trim_otp_mask = <0x1f>;
2852 + trim_otp_bit_offset = <0x00>;
2853 + trim_otp_min = <0x09>;
2854 + trim_otp_max = <0x1d>;
2855 + svb_otp_addr = <0x12020158>;
2856 + svb_otp_predev5_min = <0x2bc>;
2857 + svb_otp_predev5_max = <0x32a>;
2858 + svb_phy_predev5_val = <0x05>;
2859 + svb_otp_predev4_min = <0x32a>;
2860 + svb_otp_predev4_max = <0x398>;
2861 + svb_phy_predev4_val = <0x04>;
2862 + svb_otp_predev3_min = <0x398>;
2863 + svb_otp_predev3_max = <0x3ca>;
2864 + svb_phy_predev3_val = <0x03>;
2865 + svb_otp_predev2_min = <0x3ca>;
2866 + svb_otp_predev2_max = <0x44c>;
2867 + svb_phy_predev2_val = <0x02>;
2868 + #phy-cells = <0>;
2871 + usbdrd3_0: usb3-0{
2873 + reg = <0x10030000 0x10000>,
2874 + <0x12010000 0x1000>;
2877 + crg_offset = <0x140>;
2878 + crg_ctrl_def_mask = <0x3308>;
2879 + crg_ctrl_def_val = <0x1308>;
2886 + resets = <&clock 0x140 3>;
2890 + hidwc3@0x100e0000 {
2892 + reg = <0x10030000 0x10000>;
2893 + interrupts = <0 39 4>;
2899 + eps_directions = <0x6a>;
2901 + eps_map=<0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
2908 + reg = <0x120b0000 0x1000>;
2909 + interrupts = <0 16 4>;
2918 + reg = <0x120b1000 0x1000>;
2919 + interrupts = <0 17 4>;
2928 + reg = <0x120b2000 0x1000>;
2929 + interrupts = <0 18 4>;
2938 + reg = <0x120b3000 0x1000>;
2939 + interrupts = <0 19 4>;
2948 + reg = <0x120b4000 0x1000>;
2949 + interrupts = <0 20 4>;
2958 + reg = <0x120b5000 0x1000>;
2959 + interrupts = <0 21 4>;
2968 + reg = <0x120b6000 0x1000>;
2969 + interrupts = <0 22 4>;
2978 + reg = <0x120b7000 0x1000>;
2979 + interrupts = <0 23 4>;
2988 + reg = <0x120b8000 0x1000>;
2989 + interrupts = <0 24 4>;
2998 + reg = <0x120b9000 0x1000>;
2999 + interrupts = <0 25 4>;
3006 + cipher: cipher@0x10050000 {
3008 + reg = <0x10050000 0x10000>;
3010 + interrupts = <0 34 4>, <0 34 4>;
3016 + reg = <0x120e0000 0x1000>;
3017 + interrupts = <0 0 4>;
3022 + reg = <0x120a0000 0x1000>;
3023 + interrupts = <0 4 4>;
3025 + resets = <&clock 0x1bc 2>;
3030 + wdg: wdg@0x12030000 {
3032 + reg = <0x12030000 0x1000>;
3034 + interrupts = <0 2 4>;
3055 + mipi: mipi@0x11240000 {
3057 + reg = <0x11240000 0x10000>;
3059 + interrupts = <0 45 4>;
3065 + reg = <0x11000000 0x200000>, <0x11200000 0x40000>;
3067 + interrupts = <0 43 4>, <0 44 4>;
3073 + reg = <0x11220000 0x20000>;
3075 + interrupts = <0 43 4>;
3081 + reg = <0x11400000 0x10000>;
3083 + interrupts = <0 46 4>;
3089 + reg = <0x11280000 0x40000>;
3091 + interrupts = <0 40 4>;
3097 + reg = <0x11280000 0x40000>;
3099 + interrupts = <0 41 4>;
3105 + reg = <0x11300000 0x10000>;
3107 + interrupts = <0 49 4>;
3113 + reg = <0x11310000 0x10000>;
3115 + interrupts = <0 50 4>;
3121 + reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
3123 + interrupts = <0 47 4>, <0 48 4>;
3133 + reg = <0x100e0000 0x10000>,<0x100f0000 0x10000>;
3135 + interrupts = <0 42 4>;
3141 + reg = <0x11320000 0x10000>;
3143 + interrupts = <0 51 4>;
3153 @@ -0,0 +1,270 @@
3183 + reg = <0x82000000 0x20000000>;
3268 + spidev@0 {
3270 + reg = <0>;
3271 + pl022,interface = <0>;
3272 + pl022,com-mode = <0>;
3280 + spidev@0 {
3282 + reg = <0>;
3283 + pl022,interface = <0>;
3284 + pl022,com-mode = <0>;
3290 + pl022,interface = <0>;
3291 + pl022,com-mode = <0>;
3299 + spidev@0 {
3301 + reg = <0>;
3302 + pl022,interface = <0>;
3303 + pl022,com-mode = <0>;
3326 + reg = <0>;
3334 + reg = <0>;
3429 @@ -0,0 +1,906 @@
3485 + #size-cells = <0>;
3488 + cpu@0 {
3492 + reg = <0>;
3510 + reg = <0x12010000 0x1000>;
3516 + #address-cells = <0>;
3519 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
3525 + interrupts = <1 13 0xf08>,
3526 + <1 14 0xf08>;
3539 + #clock-cells = <0>;
3545 + #clock-cells = <0>;
3551 + interrupts = <0 54 4>;
3556 + reg = <0x10060000 0x1000>;
3557 + interrupts = <0 28 4>;
3561 + resets = <&clock 0x194 0>;
3565 + devid = <0>;
3573 + reg = <0x10060000 0x1000>;
3574 + interrupts = <0 28 4>;
3578 + resets = <&clock 0x194 0>;
3582 + devid = <0>;
3590 + reg = <0x12020000 0x1000>;
3591 + reboot-offset = <0x4>;
3604 + reg = <0x12000000 0x20>, /* clocksource */
3605 + <0x12000020 0x20>, /* local timer for each cpu */
3606 + <0x12001000 0x20>;
3607 + interrupts = <0 1 4>, /* irq of local timer */
3608 + <0 2 4>;
3618 + interrupts = <0 3 4>;
3619 + reg = <0x12002000 0x1000>;
3627 + arm,primecell-periphid = <0x00141805>;
3628 + reg = <0x12051000 0x1000>;
3636 + reg = <0x120a0000 0x1000>;
3637 + interrupts = <0 6 4>;
3645 + reg = <0x120a1000 0x1000>;
3646 + interrupts = <0 7 4>;
3658 + reg = <0x120a2000 0x1000>;
3659 + interrupts = <0 8 4>;
3671 + reg = <0x120a3000 0x1000>;
3672 + interrupts = <0 9 4>;
3684 + reg = <0x120a4000 0x1000>;
3685 + interrupts = <0 10 4>;
3700 + reg = <0x120b0000 0x1000>;
3703 + dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
3711 + reg = <0x120b1000 0x1000>;
3722 + reg = <0x120b2000 0x1000>;
3733 + reg = <0x120b3000 0x1000>;
3744 + reg = <0x120b4000 0x1000>;
3754 + reg = <0x120b5000 0x1000>;
3765 + reg = <0x120b6000 0x1000>;
3776 + reg = <0x120b7000 0x1000>;
3788 + arm,primecell-periphid = <0x00800022>;
3789 + reg = <0x120c0000 0x1000>;
3790 + interrupts = <0 68 4>;
3794 + #size-cells = <0>;
3804 + arm,primecell-periphid = <0x00800022>;
3805 + reg = <0x120c1000 0x1000>, <0x12030000 0x4>;
3806 + interrupts = <0 69 4>;
3810 + #size-cells = <0>;
3813 + hisi,spi_cs_mask_bit = <0x4>;//0100
3823 + arm,primecell-periphid = <0x00800022>;
3824 + reg = <0x120c2000 0x1000>;
3825 + interrupts = <0 70 4>;
3829 + #size-cells = <0>;
3841 + interrupts = <0 10 4>;
3842 + reg = <0x10300000 0x4000>;
3848 + reg = <0x10011100 0x10>;
3853 + resets = <&clock 0x16c 3>;
3856 + #size-cells = <0>;
3862 + reg = <0x10010000 0x1000>,<0x10011300 0x200>;
3863 + interrupts = <0 32 4>;
3865 + resets = <&clock 0x16c 0>;
3871 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
3874 + max-dma-size = <0x2000>;
3876 + #size-cells = <0>;
3878 + hisfc:spi-nor@0 {
3883 + #size-cells = <0>;
3886 + hisnfc:spi-nand@0 {
3891 + #size-cells = <0>;
3895 + mmc0: himci.eMMC@0x10100000 {
3897 + reg = <0x10100000 0x1000>;
3898 + interrupts = <0 64 4>;
3901 + resets = <&clock 0x148 0>;
3907 + devid = <0>;
3911 + mmc1: himci.SD@0x100f0000 {
3913 + reg = <0x100f0000 0x1000>;
3914 + interrupts = <0 30 4>;
3917 + resets = <&clock 0x160 0>;
3931 + mmc2: himci.SD@0x10020000 {
3933 + reg = <0x10020000 0x1000>;
3934 + interrupts = <0 31 4>;
3937 + resets = <&clock 0x154 0>;
3950 + reg = <0x10060000 0x1000>;
3951 + interrupts = <0 28 4>;
3954 + resets = <&clock 0xc8 4>;
3962 + reg = <0x12010000 0x1000>;
3963 + #phy-cells = <0>;
3967 + xhci_0@0x100e0000 {
3969 + reg = <0x100e0000 0x10000>;
3970 + interrupts = <0 27 4>;
3975 + hidwc3_0@0x100e0000 {
3977 + reg = <0x100e0000 0x10000>;
3978 + interrupts = <0 27 4>;
3986 + reg = <0x120d0000 0x1000>;
3987 + interrupts = <0 16 4>;
3996 + reg = <0x120d1000 0x1000>;
3997 + interrupts = <0 17 4>;
4006 + reg = <0x120d2000 0x1000>;
4007 + interrupts = <0 18 4>;
4016 + reg = <0x120d3000 0x1000>;
4017 + interrupts = <0 19 4>;
4026 + reg = <0x120d4000 0x1000>;
4027 + interrupts = <0 20 4>;
4036 + reg = <0x120d5000 0x1000>;
4037 + interrupts = <0 21 4>;
4046 + reg = <0x120d6000 0x1000>;
4047 + interrupts = <0 22 4>;
4056 + reg = <0x120d7000 0x1000>;
4057 + interrupts = <0 23 4>;
4066 + reg = <0x120d8000 0x1000>;
4067 + interrupts = <0 24 4>;
4076 + reg = <0x120d9000 0x1000>;
4077 + interrupts = <0 25 4>;
4086 + reg = <0x120da000 0x1000>;
4087 + interrupts = <0 26 4>;
4096 + reg = <0x120db000 0x1000>;
4097 + interrupts = <0 80 4>;
4104 + cipher: cipher@0x100c0000 {
4106 + reg = <0x100c0000 0x10000>;
4108 + interrupts = <0 71 4>, <0 72 4>, <0 71 4>, <0 72 4>;
4135 + reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
4136 + <0x12060000 0x10000>, <0x12030000 0x8000>;
4142 + reg = <0x113a0000 0x10000>;
4144 + interrupts = <0 57 4>;
4150 + reg = <0x11270000 0x10000>;
4152 + interrupts = <0 63 4>;
4158 + reg = <0x11300000 0xa0000>, <0x11000000 0x40000>;
4160 + interrupts = <0 56 4>, <0 44 4>;
4166 + reg = <0x11020000 0x20000>;
4168 + interrupts = <0 56 4>;
4174 + reg = <0x11040000 0x10000>;
4176 + interrupts = <0 43 4>;
4182 + reg = <0x11240000 0x10000>;
4184 + interrupts = <0 38 4>;
4190 + reg = <0x11440000 0x40000>;
4192 + interrupts = <0 58 4>;
4198 + reg = <0x11440000 0x40000>, <0x12020000 0x8000>;
4200 + interrupts = <0 59 4>, <0 51 4>;
4206 + reg = <0x11210000 0x10000>;
4208 + interrupts = <0 35 4>;
4218 + reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
4220 + interrupts = <0 42 4>, <0 41 4>;
4226 + reg = <0x11200000 0x10000>;
4228 + interrupts = <0 34 4>;
4234 + reg = <0x11260000 0x10000>;
4236 + interrupts = <0 45 4>;
4242 + reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
4244 + interrupts = <0 40 4>, <0 36 4>;
4254 + reg = <0x10030000 0x10000>;
4256 + interrupts = <0 67 4>;
4262 + reg = <0x11400000 0x30000>;
4268 + reg = <0x113b0000 0x10000>,<0x113c0000 0x10000>,<0x12010000 0x10000>;
4270 + interrupts = <0 55 4>;
4276 + reg = <0x11100000 0x10000>,<0x11110000 0x10000>;
4278 + interrupts = <0 41 4>,<0 42 4>;
4284 + reg = <0x11230000 0x10000>;
4286 + interrupts = <0 37 4>;
4292 + reg = <0x120e0000 0x1000>;
4293 + interrupts = <0 65 4>;
4294 + resets = <&clock 0x1bc 2>;
4300 + reg = <0x120f0000 0x1000>;
4301 + interrupts = <0 75 4>;
4306 + reg = <0x12080000 0x1000>;
4307 + interrupts = <0 5 4>;
4312 + reg = <0x12050000 0x1000>;
4316 + reg = <0x12070000 0x20>;
4318 + resets = <&clock 0x1bc 6>;
4322 + reg = <0x12070020 0x20>;
4324 + resets = <&clock 0x1bc 6>;
4329 …0x11240000 0x10000>,<0x11040000 0x10000>,<0x10030000 0x10000>,<0x113b0000 0x10000>,<0x113c0000 0x1…
4331 …terrupts = <0 67 4>,<0 26 4>,<0 56 4>, <0 44 4>,<0 43 4>,<0 38 4>,<0 58 4>,<0 40 4>,<0 36 4>,<0 37…
4341 @@ -0,0 +1,166 @@
4370 + reg = <0x40000000 0x20000000>;
4405 + spidev@0 {
4407 + reg = <0>;
4408 + pl022,interface = <0>;
4409 + pl022,com-mode = <0>;
4418 + spidev@0 {
4420 + reg = <0>;
4421 + pl022,interface = <0>;
4422 + pl022,com-mode = <0>;
4428 + pl022,interface = <0>;
4429 + pl022,com-mode = <0>;
4455 + reg = <0>;
4463 + reg = <0>;
4513 @@ -0,0 +1,678 @@
4561 + #size-cells = <0>;
4564 + cpu@0 {
4568 + reg = <0>;
4579 + reg = <0x12010000 0x1000>;
4585 + #address-cells = <0>;
4588 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
4594 + interrupts = <1 13 0xf08>,
4595 + <1 14 0xf08>;
4608 + #clock-cells = <0>;
4614 + #clock-cells = <0>;
4620 + interrupts = <0 58 4>;
4625 + reg = <0x100B0000 0x1000>;
4626 + interrupts = <0 38 4>;
4630 + resets = <&clock 0x194 0>;
4634 + devid = <0>;
4642 + reg = <0x100B0000 0x1000>;
4643 + interrupts = <0 38 4>;
4647 + resets = <&clock 0x194 0>;
4651 + devid = <0>;
4658 + reg = <0x12020000 0x1000>;
4659 + reboot-offset = <0x4>;
4672 + interrupts = <0 5 4>;
4673 + reg = <0x12000000 0x1000>;
4682 + interrupts = <0 6 4>;
4683 + reg = <0x12001000 0x1000>;
4691 + reg = <0x12040000 0x1000>;
4692 + interrupts = <0 7 4>;
4700 + reg = <0x12041000 0x1000>;
4701 + interrupts = <0 8 4>;
4713 + reg = <0x12042000 0x1000>;
4714 + interrupts = <0 9 4>;
4729 + reg = <0x12060000 0x1000>;
4737 + reg = <0x12061000 0x1000>;
4745 + reg = <0x12062000 0x1000>;
4752 + arm,primecell-periphid = <0x00800022>;
4753 + reg = <0x12070000 0x1000>;
4754 + interrupts = <0 14 4>;
4758 + #size-cells = <0>;
4768 + arm,primecell-periphid = <0x00800022>;
4769 + reg = <0x12071000 0x1000>, <0x12028000 0x4>;
4770 + interrupts = <0 15 4>;
4774 + #size-cells = <0>;
4777 + hisi,spi_cs_mask_bit = <0x4>;//0100
4787 + reg = <0x10041100 0x10>,<0x12028024 0x4>;
4790 + resets = <&clock 0x16c 3>;
4793 + #size-cells = <0>;
4799 + reg = <0x10040000 0x1000>,<0x10041300 0x200>;
4800 + interrupts = <0 33 4>;
4802 + resets = <&clock 0x16c 0>;
4808 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
4811 + max-dma-size = <0x2000>;
4813 + #size-cells = <0>;
4815 + hisfc:spi-nor@0 {
4820 + #size-cells = <0>;
4823 + hisnfc:spi-nand@0 {
4828 + #size-cells = <0>;
4834 + reg = <0x100C0000 0x10000>;
4839 + reg = <0x112C0000 0x10000>;
4842 + mmc0: sdhci@0x10010000 {
4844 + reg = <0x10010000 0x1000>;
4845 + interrupts = <0 30 4>;
4848 + resets = <&clock 0x1f4 27>, <&clock 0x1f4 29>;
4860 + devid = <0>;
4864 + mmc1: sdhci@0x10020000 {
4866 + reg = <0x10020000 0x1000>;
4867 + interrupts = <0 31 4>;
4870 + resets = <&clock 0x22c 27>, <&clock 0x22c 29>;
4883 + usb2_phy0: phy2-0 {
4885 + reg = <0x100D0000 0x1000>,
4886 + <0x12010000 0x1000>,
4887 + <0x100c0000 0x1000>;
4894 + resets = <&clock 0x140 0>,
4895 + <&clock 0x140 1>;
4898 + phy_pll_offset = <0x14>;
4899 + phy_pll_mask = <0x03>;
4900 + phy_pll_val = <0x00>;
4901 + crg_offset = <0x140>;
4902 + crg_defal_mask = <0x0c07>;
4903 + crg_defal_val = <0x0807>;
4904 + vbus_offset = <0x7c>;
4905 + vbus_val = <0x0531>;
4906 + pwren_offset = <0x80>;
4907 + pwren_val = <0x01>;
4908 + ana_cfg_0_eye_val = <0x0433c003>;
4909 + ana_cfg_0_offset = <0x00>;
4910 + ana_cfg_2_eye_val = <0x00120e0f>;
4911 + ana_cfg_2_offset = <0x08>;
4912 + ana_cfg_4_eye_val = <0x655>;
4913 + ana_cfg_4_offset = <0x10>;
4914 + trim_otp_addr = <0x12028004>;
4915 + trim_otp_mask = <0x1f>;
4916 + trim_otp_bit_offset = <0x00>;
4917 + trim_otp_min = <0x09>;
4918 + trim_otp_max = <0x1d>;
4919 + svb_otp_addr = <0x12020158>;
4920 + svb_otp_predev5_min = <0x2bc>;
4921 + svb_otp_predev5_max = <0x32a>;
4922 + svb_phy_predev5_val = <0x05>;
4923 + svb_otp_predev4_min = <0x32a>;
4924 + svb_otp_predev4_max = <0x398>;
4925 + svb_phy_predev4_val = <0x04>;
4926 + svb_otp_predev3_min = <0x398>;
4927 + svb_otp_predev3_max = <0x3ca>;
4928 + svb_phy_predev3_val = <0x03>;
4929 + svb_otp_predev2_min = <0x3ca>;
4930 + svb_otp_predev2_max = <0x44c>;
4931 + svb_phy_predev2_val = <0x02>;
4932 + #phy-cells = <0>;
4935 + usbdrd3_0: usb3-0{
4937 + reg = <0x10030000 0x10000>,
4938 + <0x12010000 0x1000>;
4941 + crg_offset = <0x140>;
4942 + crg_ctrl_def_mask = <0x3308>;
4943 + crg_ctrl_def_val = <0x1308>;
4950 + resets = <&clock 0x140 3>;
4954 + hidwc3@0x100e0000 {
4956 + reg = <0x10030000 0x10000>;
4957 + interrupts = <0 39 4>;
4963 + eps_directions = <0x6a>;
4965 + eps_map=<0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
4972 + reg = <0x120b0000 0x1000>;
4973 + interrupts = <0 16 4>;
4982 + reg = <0x120b1000 0x1000>;
4983 + interrupts = <0 17 4>;
4992 + reg = <0x120b2000 0x1000>;
4993 + interrupts = <0 18 4>;
5002 + reg = <0x120b4000 0x1000>;
5003 + interrupts = <0 20 4>;
5012 + reg = <0x120b5000 0x1000>;
5013 + interrupts = <0 21 4>;
5022 + reg = <0x120b6000 0x1000>;
5023 + interrupts = <0 22 4>;
5032 + reg = <0x120b7000 0x1000>;
5033 + interrupts = <0 23 4>;
5042 + reg = <0x120b8000 0x1000>;
5043 + interrupts = <0 24 4>;
5050 + cipher: cipher@0x10050000 {
5052 + reg = <0x10050000 0x10000>;
5054 + interrupts = <0 34 4>, <0 34 4>;
5060 + reg = <0x120e0000 0x1000>;
5061 + interrupts = <0 0 4>;
5066 + reg = <0x120a0000 0x1000>;
5067 + interrupts = <0 4 4>;
5069 + resets = <&clock 0x1bc 2>;
5074 + wdg: wdg@0x12030000 {
5076 + reg = <0x12030000 0x1000>;
5078 + interrupts = <0 2 4>;
5099 + mipi: mipi@0x11240000 {
5101 + reg = <0x11240000 0x10000>;
5103 + interrupts = <0 45 4>;
5109 + reg = <0x11000000 0x200000>, <0x11200000 0x40000>;
5111 + interrupts = <0 43 4>, <0 44 4>;
5117 + reg = <0x11220000 0x20000>;
5119 + interrupts = <0 43 4>;
5125 + reg = <0x11400000 0x10000>;
5127 + interrupts = <0 46 4>;
5133 + reg = <0x11280000 0x40000>;
5135 + interrupts = <0 40 4>;
5141 + reg = <0x11280000 0x40000>;
5143 + interrupts = <0 41 4>;
5149 + reg = <0x11300000 0x10000>;
5151 + interrupts = <0 49 4>;
5157 + reg = <0x11310000 0x10000>;
5159 + interrupts = <0 50 4>;
5165 + reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
5167 + interrupts = <0 47 4>, <0 48 4>;
5177 + reg = <0x100e0000 0x10000>,<0x100f0000 0x10000>;
5179 + interrupts = <0 42 4>;
5185 + reg = <0x11320000 0x10000>;
5187 + interrupts = <0 51 4>;
5197 @@ -0,0 +1,174 @@
5226 + reg = <0x40000000 0x20000000>;
5261 + spidev@0 {
5263 + reg = <0>;
5264 + pl022,interface = <0>;
5265 + pl022,com-mode = <0>;
5274 + spidev@0 {
5276 + reg = <0>;
5277 + pl022,interface = <0>;
5278 + pl022,com-mode = <0>;
5284 + pl022,interface = <0>;
5285 + pl022,com-mode = <0>;
5311 + reg = <0>;
5319 + reg = <0>;
5377 @@ -0,0 +1,699 @@
5427 + #size-cells = <0>;
5430 + cpu@0 {
5434 + reg = <0>;
5445 + reg = <0x12010000 0x1000>;
5451 + #address-cells = <0>;
5454 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
5460 + interrupts = <1 13 0xf08>,
5461 + <1 14 0xf08>;
5474 + #clock-cells = <0>;
5480 + #clock-cells = <0>;
5486 + interrupts = <0 58 4>;
5491 + reg = <0x100B0000 0x1000>;
5492 + interrupts = <0 38 4>;
5496 + resets = <&clock 0x194 0>;
5500 + devid = <0>;
5509 + reg = <0x100B0000 0x1000>;
5510 + interrupts = <0 38 4>;
5514 + resets = <&clock 0x194 0>;
5518 + devid = <0>;
5526 + reg = <0x12020000 0x1000>;
5527 + reboot-offset = <0x4>;
5540 + interrupts = <0 5 4>;
5541 + reg = <0x12000000 0x1000>;
5550 + interrupts = <0 6 4>;
5551 + reg = <0x12001000 0x1000>;
5559 + reg = <0x12040000 0x1000>;
5560 + interrupts = <0 7 4>;
5568 + reg = <0x12041000 0x1000>;
5569 + interrupts = <0 8 4>;
5581 + reg = <0x12042000 0x1000>;
5582 + interrupts = <0 9 4>;
5597 + reg = <0x12060000 0x1000>;
5605 + reg = <0x12061000 0x1000>;
5613 + reg = <0x12062000 0x1000>;
5620 + arm,primecell-periphid = <0x00800022>;
5621 + reg = <0x12070000 0x1000>;
5622 + interrupts = <0 14 4>;
5626 + #size-cells = <0>;
5636 + arm,primecell-periphid = <0x00800022>;
5637 + reg = <0x12071000 0x1000>, <0x12028000 0x4>;
5638 + interrupts = <0 15 4>;
5642 + #size-cells = <0>;
5645 + hisi,spi_cs_mask_bit = <0x4>;//0100
5655 + reg = <0x10041100 0x10>,<0x12028024 0x4>;
5658 + resets = <&clock 0x16c 3>;
5661 + #size-cells = <0>;
5667 + reg = <0x10040000 0x1000>,<0x10041300 0x200>;
5668 + interrupts = <0 33 4>;
5670 + resets = <&clock 0x16c 0>;
5676 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
5679 + max-dma-size = <0x2000>;
5681 + #size-cells = <0>;
5683 + hisfc:spi-nor@0 {
5688 + #size-cells = <0>;
5691 + hisnfc:spi-nand@0 {
5696 + #size-cells = <0>;
5702 + reg = <0x100C0000 0x10000>;
5705 + mmc0: sdhci@0x10010000 {
5707 + reg = <0x10010000 0x1000>;
5708 + interrupts = <0 30 4>;
5711 + resets = <&clock 0x1f4 27>, <&clock 0x1f4 29>;
5725 + devid = <0>;
5729 + mmc1: sdhci@0x10020000 {
5731 + reg = <0x10020000 0x1000>;
5732 + interrupts = <0 31 4>;
5735 + resets = <&clock 0x22c 27>, <&clock 0x22c 29>;
5748 + usb2_phy0: phy2-0 {
5750 + reg = <0x100D0000 0x1000>,
5751 + <0x12010000 0x1000>,
5752 + <0x100c0000 0x1000>;
5759 + resets = <&clock 0x140 0>,
5760 + <&clock 0x140 1>;
5763 + phy_pll_offset = <0x14>;
5764 + phy_pll_mask = <0x03>;
5765 + phy_pll_val = <0x00>;
5766 + crg_offset = <0x140>;
5767 + crg_defal_mask = <0x0c07>;
5768 + crg_defal_val = <0x0807>;
5769 + vbus_offset = <0x7c>;
5770 + vbus_val = <0x0431>;
5771 + pwren_offset = <0x80>;
5772 + pwren_val = <0x1>;
5773 + ana_cfg_0_eye_val = <0x0433c003>;
5774 + ana_cfg_0_offset = <0x00>;
5775 + ana_cfg_2_eye_val = <0x00120e0f>;
5776 + ana_cfg_2_offset = <0x08>;
5777 + ana_cfg_4_eye_val = <0x655>;
5778 + ana_cfg_4_offset = <0x10>;
5779 + trim_otp_addr = <0x12028004>;
5780 + trim_otp_mask = <0x1f>;
5781 + trim_otp_bit_offset = <0x00>;
5782 + trim_otp_min = <0x09>;
5783 + trim_otp_max = <0x1d>;
5784 + svb_otp_addr = <0x12020158>;
5785 + svb_otp_predev5_min = <0x2bc>;
5786 + svb_otp_predev5_max = <0x32a>;
5787 + svb_phy_predev5_val = <0x05>;
5788 + svb_otp_predev4_min = <0x32a>;
5789 + svb_otp_predev4_max = <0x398>;
5790 + svb_phy_predev4_val = <0x04>;
5791 + svb_otp_predev3_min = <0x398>;
5792 + svb_otp_predev3_max = <0x3ca>;
5793 + svb_phy_predev3_val = <0x03>;
5794 + svb_otp_predev2_min = <0x3ca>;
5795 + svb_otp_predev2_max = <0x44c>;
5796 + svb_phy_predev2_val = <0x02>;
5797 + #phy-cells = <0>;
5800 + usbdrd3_0: usb3-0{
5802 + reg = <0x10030000 0x10000>,
5803 + <0x12010000 0x1000>;
5806 + crg_offset = <0x140>;
5807 + crg_ctrl_def_mask = <0x3308>;
5808 + crg_ctrl_def_val = <0x1308>;
5815 + resets = <&clock 0x140 3>;
5819 + hidwc3@0x100e0000 {
5821 + reg = <0x10030000 0x10000>;
5822 + interrupts = <0 39 4>;
5828 + eps_directions = <0x6a>;
5830 + eps_map=<0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
5837 + reg = <0x120b0000 0x1000>;
5838 + interrupts = <0 16 4>;
5847 + reg = <0x120b1000 0x1000>;
5848 + interrupts = <0 17 4>;
5857 + reg = <0x120b2000 0x1000>;
5858 + interrupts = <0 18 4>;
5867 + reg = <0x120b3000 0x1000>;
5868 + interrupts = <0 19 4>;
5877 + reg = <0x120b4000 0x1000>;
5878 + interrupts = <0 20 4>;
5887 + reg = <0x120b5000 0x1000>;
5888 + interrupts = <0 21 4>;
5897 + reg = <0x120b6000 0x1000>;
5898 + interrupts = <0 22 4>;
5907 + reg = <0x120b7000 0x1000>;
5908 + interrupts = <0 23 4>;
5917 + reg = <0x120b8000 0x1000>;
5918 + interrupts = <0 24 4>;
5927 + reg = <0x120b9000 0x1000>;
5928 + interrupts = <0 25 4>;
5935 + cipher: cipher@0x10050000 {
5937 + reg = <0x10050000 0x10000>;
5939 + interrupts = <0 34 4>, <0 34 4>;
5945 + reg = <0x120e0000 0x1000>;
5946 + interrupts = <0 0 4>;
5951 + reg = <0x120a0000 0x1000>;
5952 + interrupts = <0 4 4>;
5954 + resets = <&clock 0x1bc 2>;
5959 + wdg: wdg@0x12030000 {
5961 + reg = <0x12030000 0x1000>;
5963 + interrupts = <0 2 4>;
5984 + mipi: mipi@0x11240000 {
5986 + reg = <0x11240000 0x10000>;
5988 + interrupts = <0 45 4>;
5994 + reg = <0x11000000 0x200000>, <0x11200000 0x40000>;
5996 + interrupts = <0 43 4>, <0 44 4>;
6002 + reg = <0x11220000 0x20000>;
6004 + interrupts = <0 43 4>;
6010 + reg = <0x11400000 0x10000>;
6012 + interrupts = <0 46 4>;
6018 + reg = <0x11280000 0x40000>;
6020 + interrupts = <0 40 4>;
6026 + reg = <0x11280000 0x40000>;
6028 + interrupts = <0 41 4>;
6034 + reg = <0x11300000 0x10000>;
6036 + interrupts = <0 49 4>;
6042 + reg = <0x11310000 0x10000>;
6044 + interrupts = <0 50 4>;
6050 + reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
6052 + interrupts = <0 47 4>, <0 48 4>;
6062 + reg = <0x100e0000 0x10000>,<0x100f0000 0x10000>;
6064 + interrupts = <0 42 4>;
6070 + reg = <0x11320000 0x10000>;
6072 + interrupts = <0 51 4>;
6082 @@ -0,0 +1,197 @@
6131 + reg = <0x80000000 0x20000000>;
6154 + reg = <0>;
6163 + reg = <0>;
6215 + spidev@0 {
6217 + reg = <0>;
6218 + pl022,interface = <0>;
6219 + pl022,com-mode = <0>;
6228 + spidev@0 {
6230 + reg = <0>;
6231 + pl022,interface = <0>;
6232 + pl022,com-mode = <0>;
6239 + pl022,interface = <0>;
6240 + pl022,com-mode = <0>;
6285 @@ -0,0 +1,577 @@
6312 + #size-cells = <0>;
6314 + cpu@0 {
6317 + reg = <0>;
6325 + reg = <0x100d0000 0x1000>;
6337 + reg = <0x20030000 0x1000>;
6345 + reg = <0x20050000 0x1000>;
6352 + offset = <0x4>;
6353 + mask = <0xdeadbeef>;
6360 + reg = <0x20000000 0x1000>;
6372 + reg = <0x20010000 0x1000>;
6382 + reg = <0x20080000 0x1000>;
6391 + reg = <0x20090000 0x1000>;
6400 + reg = <0x200a0000 0x1000>;
6409 + reg = <0x20030000 0x10000>, <0x20120000 0x10000>,
6410 + <0x20050000 0x10000>;
6411 + #phy-cells = <0>;
6414 + ehci@0x100b0000 {
6416 + reg = <0x100b0000 0x10000>;
6424 + ohci@0x100a0000 {
6426 + reg = <0x100a0000 0x10000>;
6434 + hiudc@0x10080000 {
6436 + reg = <0x10080000 0x10000>;
6445 + reg = <0x200d0000 0x100>;
6449 + io-size = <0x1000>;
6450 + id = <0>;
6456 + reg = <0x20240000 0x100>;
6460 + io-size = <0x1000>;
6467 + reg = <0x20250000 0x100>;
6471 + io-size = <0x1000>;
6478 + arm,primecell-periphid = <0x00800022>;
6479 + reg = <0x200c0000 0x1000>;
6485 + #size-cells = <0>;
6490 + arm,primecell-periphid = <0x00800022>;
6491 + reg = <0x200e0000 0x1000>, <0x20120004 0x4>;
6497 + #size-cells = <0>;
6499 + hisi,spi_cs_mask_bit = <0x0c000000>;
6504 + reg = <0x10010000 0x1000>, <0x58000000 0x10000>;
6507 + max-dma-size = <0x2000>;
6509 + #size-cells = <0>;
6511 + hisfc:spi-nor@0 {
6516 + #size-cells = <0>;
6519 + hisnfc:spi-nand@0 {
6524 + #size-cells = <0>;
6530 + reg = <0x10091100 0x10>;
6535 + resets = <&clock 0xec 3>;
6538 + #size-cells = <0>;
6544 + reg = <0x10090000 0x1000>,<0x10091300 0x200>;
6547 + resets = <&clock 0xec 0>;
6551 + mmc0_emmc: himciv200.MMC@0x10020000{
6553 + reg = <0x10020000 0x1000>;
6558 + resets = <&clock 0xc4 8>;
6565 + devid = <0>;
6569 + mmc0_sd: himciv200.SD@0x10020000{
6571 + reg = <0x10020000 0x1000>;
6576 + resets = <&clock 0xc4 8>;
6584 + devid = <0>;
6588 + mmc1_sd: himciv200.SD@0x10030000{
6590 + reg = <0x10030000 0x1000>;
6595 + resets = <&clock 0xc4 0>;
6605 + reg = <0x200f0000 0x108>;
6614 + pinctrl-single,gpio-range = <&range 0 5 0
6615 + &range 6 38 0 &range 44 1 2
6616 + &range 45 13 0 &range 58 8 1>;
6625 + reg = <0x200f0800 0x130>;
6635 + reg = <0x20140000 0x10000>;
6640 + gpio-ranges = <&pmux 0 28 3>, <&pmux 3 12 1>,
6641 + <&pmux 4 0 4>;
6647 + reg = <0x20150000 0x10000>;
6652 + gpio-ranges = <&pmux 0 31 8>;
6658 + reg = <0x20160000 0x10000>;
6663 + gpio-ranges = <&pmux 0 4 8>;
6669 + reg = <0x20170000 0x10000>;
6674 + gpio-ranges = <&pmux 0 13 8>;
6680 + reg = <0x20180000 0x10000>;
6685 + gpio-ranges = <&pmux 0 21 7>, <&pmux 7 39 1>;
6691 + reg = <0x20190000 0x10000>;
6696 + gpio-ranges = <&pmux 0 40 8>;
6702 + reg = <0x201a0000 0x10000>;
6707 + gpio-ranges = <&pmux 0 48 8>;
6713 + reg = <0x201b0000 0x10000>;
6718 + gpio-ranges = <&pmux 0 56 8>;
6724 + reg = <0x201c0000 0x10000>;
6729 + gpio-ranges = <&pmux 0 64 2>;
6735 + reg = <0x10060000 0x1000>;
6739 + resets = <&clock 0xd8 4>;
6759 + reg = <0x20030000 0x10000>, <0x20050000 0x10000>,
6760 + <0x20110000 0x10000>, <0x20120000 0x10000>;
6767 + reg = <0x20650000 0x10000>;
6774 + reg = <0x206a0000 0x10000>;
6780 + reg = <0x20680000 0x10000>;
6786 + reg = <0x20580000 0x10000>, <0x205a0000 0x20000>;
6793 + reg = <0x20580000 0x40000>;
6799 + reg = <0x205c0000 0x10000>;
6805 + reg = <0x20630000 0x10000>;
6811 + reg = <0x20600000 0x10000>;
6817 + reg = <0x20620000 0x10000>;
6823 + reg = <0x20660000 0x10000>;
6829 + reg = <0x20610000 0x10000>;
6834 + reg = <0x20130000 0x10000>;
6839 + reg = <0x20040000 0x10000>;
6847 + reg = <0x20060000 0x10000>;
6853 + reg = <0x20070000 0x10000>;
6859 + reg = <0x100c0000 0x10000>;
6868 @@ -0,0 +1,166 @@
6897 + reg = <0x40000000 0x20000000>;
6932 + spidev@0 {
6934 + reg = <0>;
6935 + pl022,interface = <0>;
6936 + pl022,com-mode = <0>;
6945 + spidev@0 {
6947 + reg = <0>;
6948 + pl022,interface = <0>;
6949 + pl022,com-mode = <0>;
6955 + pl022,interface = <0>;
6956 + pl022,com-mode = <0>;
6982 + reg = <0>;
6990 + reg = <0>;
7040 @@ -0,0 +1,678 @@
7088 + #size-cells = <0>;
7091 + cpu@0 {
7095 + reg = <0>;
7106 + reg = <0x12010000 0x1000>;
7112 + #address-cells = <0>;
7115 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
7121 + interrupts = <1 13 0xf08>,
7122 + <1 14 0xf08>;
7135 + #clock-cells = <0>;
7141 + #clock-cells = <0>;
7147 + interrupts = <0 58 4>;
7152 + reg = <0x100B0000 0x1000>;
7153 + interrupts = <0 38 4>;
7157 + resets = <&clock 0x194 0>;
7161 + devid = <0>;
7169 + reg = <0x100B0000 0x1000>;
7170 + interrupts = <0 38 4>;
7174 + resets = <&clock 0x194 0>;
7178 + devid = <0>;
7185 + reg = <0x12020000 0x1000>;
7186 + reboot-offset = <0x4>;
7199 + interrupts = <0 5 4>;
7200 + reg = <0x12000000 0x1000>;
7209 + interrupts = <0 6 4>;
7210 + reg = <0x12001000 0x1000>;
7218 + reg = <0x12040000 0x1000>;
7219 + interrupts = <0 7 4>;
7227 + reg = <0x12041000 0x1000>;
7228 + interrupts = <0 8 4>;
7240 + reg = <0x12042000 0x1000>;
7241 + interrupts = <0 9 4>;
7256 + reg = <0x12060000 0x1000>;
7264 + reg = <0x12061000 0x1000>;
7272 + reg = <0x12062000 0x1000>;
7279 + arm,primecell-periphid = <0x00800022>;
7280 + reg = <0x12070000 0x1000>;
7281 + interrupts = <0 14 4>;
7285 + #size-cells = <0>;
7295 + arm,primecell-periphid = <0x00800022>;
7296 + reg = <0x12071000 0x1000>, <0x12028000 0x4>;
7297 + interrupts = <0 15 4>;
7301 + #size-cells = <0>;
7304 + hisi,spi_cs_mask_bit = <0x4>;//0100
7314 + reg = <0x10041100 0x10>,<0x12028024 0x4>;
7317 + resets = <&clock 0x16c 3>;
7320 + #size-cells = <0>;
7326 + reg = <0x10040000 0x1000>,<0x10041300 0x200>;
7327 + interrupts = <0 33 4>;
7329 + resets = <&clock 0x16c 0>;
7335 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
7338 + max-dma-size = <0x2000>;
7340 + #size-cells = <0>;
7342 + hisfc:spi-nor@0 {
7347 + #size-cells = <0>;
7350 + hisnfc:spi-nand@0 {
7355 + #size-cells = <0>;
7361 + reg = <0x100C0000 0x10000>;
7366 + reg = <0x112C0000 0x10000>;
7369 + mmc0: sdhci@0x10010000 {
7371 + reg = <0x10010000 0x1000>;
7372 + interrupts = <0 30 4>;
7375 + resets = <&clock 0x1f4 27>, <&clock 0x1f4 29>;
7387 + devid = <0>;
7391 + mmc1: sdhci@0x10020000 {
7393 + reg = <0x10020000 0x1000>;
7394 + interrupts = <0 31 4>;
7397 + resets = <&clock 0x22c 27>, <&clock 0x22c 29>;
7410 + usb2_phy0: phy2-0 {
7412 + reg = <0x100D0000 0x1000>,
7413 + <0x12010000 0x1000>,
7414 + <0x100c0000 0x1000>;
7421 + resets = <&clock 0x140 0>,
7422 + <&clock 0x140 1>;
7425 + phy_pll_offset = <0x14>;
7426 + phy_pll_mask = <0x03>;
7427 + phy_pll_val = <0x00>;
7428 + crg_offset = <0x140>;
7429 + crg_defal_mask = <0x0c07>;
7430 + crg_defal_val = <0x0807>;
7431 + vbus_offset = <0x7c>;
7432 + vbus_val = <0x0531>;
7433 + pwren_offset = <0x80>;
7434 + pwren_val = <0x1>;
7435 + ana_cfg_0_eye_val = <0x0433c003>;
7436 + ana_cfg_0_offset = <0x00>;
7437 + ana_cfg_2_eye_val = <0x00120e0f>;
7438 + ana_cfg_2_offset = <0x08>;
7439 + ana_cfg_4_eye_val = <0x655>;
7440 + ana_cfg_4_offset = <0x10>;
7441 + trim_otp_addr = <0x12028004>;
7442 + trim_otp_mask = <0x1f>;
7443 + trim_otp_bit_offset = <0x00>;
7444 + trim_otp_min = <0x09>;
7445 + trim_otp_max = <0x1d>;
7446 + svb_otp_addr = <0x12020158>;
7447 + svb_otp_predev5_min = <0x2bc>;
7448 + svb_otp_predev5_max = <0x32a>;
7449 + svb_phy_predev5_val = <0x05>;
7450 + svb_otp_predev4_min = <0x32a>;
7451 + svb_otp_predev4_max = <0x398>;
7452 + svb_phy_predev4_val = <0x04>;
7453 + svb_otp_predev3_min = <0x398>;
7454 + svb_otp_predev3_max = <0x3ca>;
7455 + svb_phy_predev3_val = <0x03>;
7456 + svb_otp_predev2_min = <0x3ca>;
7457 + svb_otp_predev2_max = <0x44c>;
7458 + svb_phy_predev2_val = <0x02>;
7459 + #phy-cells = <0>;
7462 + usbdrd3_0: usb3-0{
7464 + reg = <0x10030000 0x10000>,
7465 + <0x12010000 0x1000>;
7468 + crg_offset = <0x140>;
7469 + crg_ctrl_def_mask = <0x3308>;
7470 + crg_ctrl_def_val = <0x1308>;
7477 + resets = <&clock 0x140 3>;
7481 + hidwc3@0x100e0000 {
7483 + reg = <0x10030000 0x10000>;
7484 + interrupts = <0 39 4>;
7490 + eps_directions = <0x6a>;
7492 + eps_map=<0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
7499 + reg = <0x120b0000 0x1000>;
7500 + interrupts = <0 16 4>;
7509 + reg = <0x120b1000 0x1000>;
7510 + interrupts = <0 17 4>;
7519 + reg = <0x120b2000 0x1000>;
7520 + interrupts = <0 18 4>;
7529 + reg = <0x120b4000 0x1000>;
7530 + interrupts = <0 20 4>;
7539 + reg = <0x120b5000 0x1000>;
7540 + interrupts = <0 21 4>;
7549 + reg = <0x120b6000 0x1000>;
7550 + interrupts = <0 22 4>;
7559 + reg = <0x120b7000 0x1000>;
7560 + interrupts = <0 23 4>;
7569 + reg = <0x120b8000 0x1000>;
7570 + interrupts = <0 24 4>;
7577 + cipher: cipher@0x10050000 {
7579 + reg = <0x10050000 0x10000>;
7581 + interrupts = <0 34 4>, <0 34 4>;
7587 + reg = <0x120e0000 0x1000>;
7588 + interrupts = <0 0 4>;
7593 + reg = <0x120a0000 0x1000>;
7594 + interrupts = <0 4 4>;
7596 + resets = <&clock 0x1bc 2>;
7601 + wdg: wdg@0x12030000 {
7603 + reg = <0x12030000 0x1000>;
7605 + interrupts = <0 2 4>;
7626 + mipi: mipi@0x11240000 {
7628 + reg = <0x11240000 0x10000>;
7630 + interrupts = <0 45 4>;
7636 + reg = <0x11000000 0x200000>, <0x11200000 0x40000>;
7638 + interrupts = <0 43 4>, <0 44 4>;
7644 + reg = <0x11220000 0x20000>;
7646 + interrupts = <0 43 4>;
7652 + reg = <0x11400000 0x10000>;
7654 + interrupts = <0 46 4>;
7660 + reg = <0x11280000 0x40000>;
7662 + interrupts = <0 40 4>;
7668 + reg = <0x11280000 0x40000>;
7670 + interrupts = <0 41 4>;
7676 + reg = <0x11300000 0x10000>;
7678 + interrupts = <0 49 4>;
7684 + reg = <0x11310000 0x10000>;
7686 + interrupts = <0 50 4>;
7692 + reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
7694 + interrupts = <0 47 4>, <0 48 4>;
7704 + reg = <0x100e0000 0x10000>,<0x100f0000 0x10000>;
7706 + interrupts = <0 42 4>;
7712 + reg = <0x11320000 0x10000>;
7714 + interrupts = <0 51 4>;
7724 @@ -0,0 +1,25 @@
7755 @@ -0,0 +1,25 @@
7786 @@ -0,0 +1,25 @@
7817 @@ -0,0 +1,25 @@
7848 @@ -0,0 +1,289 @@
7876 + linux,initrd-start = <0x23000040>;
7877 + linux,initrd-end = <0x24000000>;
7882 + #size-cells = <0>;
7885 + cpu@0 {
7888 + reg = <0>;
7895 + reg = <0x100>;
7903 + reg = <0x22000000 0x10000000>;
7958 + spidev@0 {
7960 + reg = <0>;
7961 + pl022,interface = <0>;
7962 + pl022,com-mode = <0>;
7970 + spidev@0 {
7972 + reg = <0>;
7973 + pl022,interface = <0>;
7974 + pl022,com-mode = <0>;
7982 + spidev@0 {
7984 + reg = <0>;
7985 + pl022,interface = <0>;
7986 + pl022,com-mode = <0>;
7994 + spidev@0 {
7996 + reg = <0>;
7997 + pl022,interface = <0>;
7998 + pl022,com-mode = <0>;
8006 + spidev@0 {
8008 + reg = <0>;
8009 + pl022,interface = <0>;
8010 + pl022,com-mode = <0>;
8029 + reg = <0>;
8038 + reg = <0>;
8046 + reg = <0>;
8143 @@ -0,0 +1,280 @@
8171 + linux,initrd-start = <0x23000040>;
8172 + linux,initrd-end = <0x24000000>;
8177 + #size-cells = <0>;
8179 + cpu@0 {
8182 + reg = <0>;
8189 + reg = <0x32000000 0x10000000>;
8244 + spidev@0 {
8246 + reg = <0>;
8247 + pl022,interface = <0>;
8248 + pl022,com-mode = <0>;
8256 + spidev@0 {
8258 + reg = <0>;
8259 + pl022,interface = <0>;
8260 + pl022,com-mode = <0>;
8268 + spidev@0 {
8270 + reg = <0>;
8271 + pl022,interface = <0>;
8272 + pl022,com-mode = <0>;
8280 + spidev@0 {
8282 + reg = <0>;
8283 + pl022,interface = <0>;
8284 + pl022,com-mode = <0>;
8292 + spidev@0 {
8294 + reg = <0>;
8295 + pl022,interface = <0>;
8296 + pl022,com-mode = <0>;
8315 + reg = <0>;
8324 + reg = <0>;
8332 + reg = <0>;
8429 @@ -0,0 +1,1070 @@
8493 + #address-cells = <0>;
8496 + reg = <0x04C01000 0x1000>, <0x04C02000 0x1000>;
8505 + reg = <0x04510000 0x10000>;
8511 + #clock-cells = <0>;
8518 + interrupts = <1 13 0xf08>,
8519 + <1 14 0xf08>;
8526 + interrupts = <0 74 4>;
8527 + reg = <0x045E0000 0x1000>;
8546 + reg = <0x04540000 0x1000>;
8547 + interrupts = <0 36 4>;
8555 + reg = <0x04541000 0x1000>;
8556 + interrupts = <0 37 4>;
8566 + reg = <0x04542000 0x1000>;
8567 + interrupts = <0 38 4>;
8577 + reg = <0x04543000 0x1000>;
8578 + interrupts = <0 39 4>;
8588 + reg = <0x04544000 0x1000>;
8589 + interrupts = <0 40 4>;
8599 + reg = <0x04560000 0x1000>;
8603 + dmas = <&hiedmacv310_1 0 14>, <&hiedmacv310_1 1 15>;
8609 + reg = <0x04561000 0x1000>;
8619 + reg = <0x04562000 0x1000>;
8629 + reg = <0x04563000 0x1000>;
8639 + reg = <0x04564000 0x1000>;
8649 + reg = <0x04565000 0x1000>;
8659 + reg = <0x04566000 0x1000>;
8669 + reg = <0x04567000 0x1000>;
8679 + reg = <0x04568000 0x1000>;
8689 + reg = <0x04569000 0x1000>;
8699 + arm,primecell-periphid = <0x00800022>;
8700 + reg = <0x04570000 0x1000>;
8701 + interrupts = <0 155 4>;
8705 + #size-cells = <0>;
8714 + arm,primecell-periphid = <0x00800022>;
8715 + reg = <0x04571000 0x1000>;
8716 + interrupts = <0 156 4>;
8720 + #size-cells = <0>;
8729 + arm,primecell-periphid = <0x00800022>;
8730 + reg = <0x04572000 0x1000>;
8731 + interrupts = <0 157 4>;
8735 + #size-cells = <0>;
8744 + arm,primecell-periphid = <0x00800022>;
8745 + reg = <0x04573000 0x1000>;
8746 + interrupts = <0 158 4>;
8750 + #size-cells = <0>;
8759 + arm,primecell-periphid = <0x00800022>;
8760 + reg = <0x04574000 0x1000>;
8761 + interrupts = <0 159 4>;
8765 + #size-cells = <0>;
8774 + reg = <0x045f0000 0x1000>;
8775 + interrupts = <0 56 4>;
8784 + reg = <0x045f1000 0x1000>;
8785 + interrupts = <0 57 4>;
8794 + reg = <0x045f2000 0x1000>;
8795 + interrupts = <0 58 4>;
8804 + reg = <0x045f3000 0x1000>;
8805 + interrupts = <0 59 4>;
8814 + reg = <0x045f4000 0x1000>;
8815 + interrupts = <0 60 4>;
8824 + reg = <0x045f5000 0x1000>;
8825 + interrupts = <0 61 4>;
8834 + reg = <0x045f6000 0x1000>;
8835 + interrupts = <0 62 4>;
8844 + reg = <0x045f7000 0x1000>;
8845 + interrupts = <0 63 4>;
8854 + reg = <0x045f8000 0x1000>;
8855 + interrupts = <0 64 4>;
8864 + reg = <0x045f9000 0x1000>;
8865 + interrupts = <0 65 4>;
8874 + reg = <0x045fa000 0x1000>;
8875 + interrupts = <0 66 4>;
8884 + reg = <0x045fb000 0x1000>;
8885 + interrupts = <0 67 4>;
8894 + reg = <0x045fc000 0x1000>;
8895 + interrupts = <0 68 4>;
8904 + reg = <0x045fd000 0x1000>;
8905 + interrupts = <0 69 4>;
8914 + reg = <0x045fe000 0x1000>;
8915 + interrupts = <0 70 4>;
8923 + interrupts = <0 30 4>;
8924 + reg = <0x04500000 0x1000>;
8931 + reg = <0x04500000 0x20>, /* clocksource */
8932 + <0x04500020 0x20>, /* local timer for each cpu */
8933 + <0x04501000 0x20>;
8934 + interrupts = <0 30 4>, /* irq of local timer */
8935 + <0 31 4>;
8946 + reg = <0x04c10000 0x1000>;
8947 + interrupts = <0 2 4>;
8950 + resets = <&clock 0x14c 4>;
8958 + reg = <0x04040000 0x1000>;
8960 + misc_ctrl_base = <0x124>;
8961 + interrupts = <0 98 4>;
8965 + resets = <&clock 0x16c 4>;
8969 + devid = <0>;
8976 + reg = <0x04050000 0x1000>;
8978 + misc_ctrl_base = <0x144>;
8979 + interrupts = <0 99 4>;
8983 + resets = <&clock 0x16c 7>;
8994 + reg = <0x04520000 0x1000>;
9001 + offset = <0x4>;
9002 + mask = <0xdeadbeef>;
9008 + reg = <0x04528000 0x10000>;
9013 + reg = <0x04058000 0x100>;
9018 + reg = <0x047B8000 0x100>;
9023 + reg = <0x047E0000 0x100>;
9028 + reg = <0x047E8000 0x100>;
9033 + reg = <0x04510000 0x1000>, <0x04528000 0x1000>, <0x04520000 0x1000>;
9034 + #phy-cells = <0>;
9038 + xhci_0@0x04110000 {
9040 + reg = <0x04110000 0x10000>;
9041 + interrupts = <0 111 4>;
9047 + xhci_1@0x04120000 {
9049 + reg = <0x04120000 0x10000>;
9050 + interrupts = <0 112 4>;
9056 + hidwc3_0@0x04110000 {
9058 + reg = <0x04110000 0x10000>, <0x04510000 0x1000>, <0x04520000 0x1000>;
9059 + interrupts = <0 111 4>;
9069 + hidwc3_1@0x04120000 {
9071 + reg = <0x04120000 0x10000>, <0x04510000 0x1000>, <0x04520000 0x1000>;
9072 + interrupts = <0 112 4>;
9082 + reg = <0x04d00000 0x1000>;
9083 + ranges = <0x0 0x04d00000 0x6000>;
9088 + reg = <0x2000 0x1000>;
9094 + reg = <0x3000 0x1000>;
9101 + reg = <0x040e03c0 0x20>;
9103 + resets = <&clock 0x174 14>;
9106 + #size-cells = <0>;
9111 + reg = <0x040e0000 0x1000>,<0x040e300c 0x4>;
9112 + interrupts = <0 89 4>;
9119 + resets = <&clock 0x174 0>,
9120 + <&clock 0x174 4>;
9129 + reg = <0x04020000 0x1000>, <0x0f000000 0x1000000>;
9132 + max-dma-size = <0x2000>;
9134 + #size-cells = <0>;
9141 + #size-cells = <0>;
9149 + #size-cells = <0>;
9157 + #size-cells = <0>;
9161 + mmc0: eMMC@0x04030000 {
9163 + reg = <0x04030000 0x1000>, <0x04048000 0x1000>;
9164 + interrupts = <0 92 4>;
9167 + resets = <&clock 0x1a8 27>, <&clock 0x1a8 29>, <&clock 0x1a8 30>;
9177 + devid = <0>;
9181 + mmc1: SD@0x040c0000 {
9183 + reg = <0x040c0000 0x1000>;
9184 + interrupts = <0 87 4>;
9187 + resets = <&clock 0x1ec 27>, <&clock 0x1ec 29>, <&clock 0x1ec 30>;
9202 + mmc2: SD@0x040d0000 {
9204 + reg = <0x040d0000 0x1000>;
9205 + interrupts = <0 88 4>;
9208 + resets = <&clock 0x214 27>, <&clock 0x214 29>, <&clock 0x214 30>;
9223 + pcie0: pcie@0x0eff0000 {
9229 + bus-range = <0x0 0xff>;
9230 + ranges = <0x02000000 0x00 0x18000000 0x18000000 0x00 0xff00000>;
9231 + interrupts = <0 107 4>;
9233 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
9234 + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 102 0x4
9235 + 0x0 0x0 0x0 0x2 &gic 0x0 103 0x4
9236 + 0x0 0x0 0x0 0x3 &gic 0x0 104 0x4
9237 + 0x0 0x0 0x0 0x4 &gic 0x0 105 0x4>;
9238 + pcie_controller = <0>;
9239 + dev_mem_size = <0x8000000>;
9240 + dev_conf_size = <0x8000000>;
9241 + pcie_dbi_base = <0x0eff0000>;
9242 + ep_conf_base = <0x10000000>;
9245 + pcie_mcc: pcie_mcc@0x0 {
9247 + interrupts = <0 102 4>,<0 103 4>,< 0 104 4>
9248 + ,< 0 105 4>,< 0 106 4>,< 0 73 4>;
9251 + cipher: cipher@0x04060000 {
9253 + reg = <0x04060000 0x10000>, <0x04080000 0x10000>;
9255 + interrupts = <0 93 4>, <0 94 4>, <0 93 4>, <0 94 4>, <0 95 4>, <0 85 4>;
9261 + reg = <0x045c0000 0x1000>;
9262 + interrupts = <0 55 4>;
9267 + reg = <0x04550000 0x1000>;
9268 + interrupts = <0 28 4>;
9273 + reg = <0x04530000 0x1000>;
9292 + reg = <0x04510000 0x10000>, <0x04520000 0x8000>,
9293 + <0x04600000 0x10000>, <0x04528000 0x8000>;
9299 + reg = <0x04a40000 0x10000>, <0x04a80000 0x10000>;
9301 + interrupts = <0 128 4>, <0 129 4>;
9307 + reg = <0x04780000 0x10000>;
9309 + interrupts = <0 120 4>;
9315 + reg = <0x04800000 0x200000>, <0x04a00000 0x40000>;
9317 + interrupts = <0 127 4>, <0 125 4>;
9323 + reg = <0x04a20000 0x20000>;
9325 + interrupts = <0 127 4>;
9331 + reg = <0x04b20000 0x10000>;
9333 + interrupts = <0 126 4>;
9339 + reg = <0x04a90000 0x10000>;
9341 + interrupts = <0 130 4>;
9347 + reg = <0x04700000 0x20000>;
9349 + interrupts = <0 117 4>;
9355 + reg = <0x04700000 0x20000>;
9357 + interrupts = <0 118 4>;
9363 + reg = <0x04ad0000 0x10000>;
9365 + interrupts = <0 149 4>;
9371 + reg = <0x04b00000 0x10000>;
9373 + interrupts = <0 139 4>;
9379 + reg = <0x04aa0000 0x10000>;
9381 + interrupts = <0 134 4>;
9391 + reg = <0x04ab0000 0x10000>;
9393 + interrupts = <0 133 4>;
9399 + reg = <0x04790000 0x10000>;
9401 + interrupts = <0 138 4>;
9407 + reg = <0x04ac0000 0x10000>;
9409 + interrupts = <0 131 4>;
9415 + reg = <0x047c0000 0x8000>, <0x047c8000 0x8000>;
9417 + interrupts = <0 115 4>, <0 132 4>;
9427 + reg = <0x047d0000 0x10000>;
9429 + interrupts = <0 114 4>, <0 113 4>;
9435 + reg = <0x04740000 0x30000>;
9441 + reg = <0x047a0000 0x10000>,<0x047b0000 0x10000>,<0x04510000 0x10000>;
9443 + interrupts = <0 119 4>,<0 151 4>;
9447 + nnie: nnie@0x04C30000 {
9449 + reg = <0x04C30000 0x10000>;
9451 + interrupts = <0 1 4>;
9455 + dpu_rect: dpu_rect@0x04AE0000 {
9457 + reg = <0x04AE0000 0x10000>;
9459 + interrupts = <0 135 4>;
9463 + dpu_match: dpu_match@0x04AE0000 {
9465 + reg = <0x04AE0000 0x10000>;
9467 + interrupts = <0 136 4>;
9471 + dsp: dsp@0x04C20000 {
9473 + reg = <0x04C20000 0x10000>;
9477 + ive: ive@0x04B10000 {
9479 + reg = <0x04B10000 0x10000>;
9481 + interrupts = <0 147 4>;
9487 + reg = <0x045d0000 0x1000>;
9488 + interrupts = <0 83 4>;
9489 + resets = <&clock 0x194 16>;
9496 + reg = <0x045A0000 0x10000>;
9505 @@ -0,0 +1,211 @@
9560 + reg = <0x40000000 0xC0000000>;
9597 + spidev@0 {
9599 + reg = <0>;
9600 + pl022,interface = <0>;
9601 + pl022,com-mode = <0>;
9610 + spidev@0 {
9612 + reg = <0>;
9613 + pl022,interface = <0>;
9614 + pl022,com-mode = <0>;
9625 + phy0: ethernet-phy@0 {
9626 + reg = <0>;
9640 + reg = <0>;
9648 + reg = <0>;
9722 @@ -0,0 +1,103 @@
9757 + reg = <0x80000000 0x20000000>;
9776 + reg = <0>;
9785 + reg = <0>;
9810 + spidev@0 {
9812 + reg = <0>;
9813 + pl022,interface = <0>;
9814 + pl022,com-mode = <0>;
9821 + pl022,interface = <0>;
9822 + pl022,com-mode = <0>;
9831 @@ -0,0 +1,406 @@
9858 + #size-cells = <0>;
9860 + cpu@0 {
9863 + reg = <0>;
9870 + #address-cells = <0>;
9873 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
9885 + reg = <0x12040000 0x1000>;
9892 + reg = <0x12050000 0x1000>;
9899 + offset = <0x4>;
9900 + mask = <0xdeadbeef>;
9907 + reg = <0x12000000 0x1000>;
9919 + reg = <0x12010000 0x1000>;
9931 + reg = <0x12020000 0x1000>;
9944 + reg = <0x12030000 0x1000>;
9954 + reg = <0x10060000 0x1000>;
9958 + resets = <&clock 0x80 4>;
9966 + reg = <0x12080000 0x1000>;
9975 + reg = <0x12090000 0x1000>;
9984 + reg = <0x120a0000 0x1000>;
9993 + reg = <0x120c0000 0x100>;
9997 + io-size = <0x1000>;
9998 + id = <0>;
10004 + arm,primecell-periphid = <0x00800022>;
10005 + reg = <0x120d0000 0x1000>, <0x12120014 0x4>;
10011 + #size-cells = <0>;
10012 + hisi,spi_cs_sb = <0>;
10013 + hisi,spi_cs_mask_bit = <0x00000003>;
10018 + reg = <0x12040000 0x10000>, <0x12120000 0x10000>;
10019 + #phy-cells = <0>;
10022 + ehci@0x10040000 {
10024 + reg = <0x10040000 0x10000>;
10028 + ohci@0x10030000 {
10030 + reg = <0x10030000 0x10000>;
10036 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
10039 + max-dma-size = <0x2000>;
10041 + #size-cells = <0>;
10043 + hisfc:spi-nor@0 {
10048 + #size-cells = <0>;
10051 + hisnfc:spi-nand@0 {
10056 + #size-cells = <0>;
10062 + reg = <0x100a03c0 0x20>;
10067 + resets = <&clock 0x78 5>;
10070 + #size-cells = <0>;
10075 + reg = <0x100a0000 0x1000>,<0x1204008c 0x4>,
10076 + <0x100a3014 0x4>;
10084 + resets = <&clock 0x78 0>,
10085 + <&clock 0x78 2>;
10094 + reg = <0x11010000 0x10000>;
10096 + #phy-cells = <0>;
10101 + reg = <0x11010000 0x1000>;
10106 + #size-cells = <0>;
10119 + reg = <0x12040000 0x10000>, <0x12050000 0x10000>,
10120 + <0x12110000 0x10000>, <0x12120000 0x10000>;
10127 + reg = <0x120b0000 0x10000>;
10130 + hiir: hiir@0x12140000 {
10133 + reg = <0x12140000 0x10000>;
10136 + cipher: cipher@0x10070000 {
10139 + reg = <0x10070000 0x2000>;
10145 + reg = <0x130C0000 0x40000>;
10151 + reg = <0x13020000 0x10000>;
10158 + reg = <0x13110000 0x5000>;
10165 + reg = <0x13080000 0x5000>;
10171 + reg = <0x13150000 0x10000>;
10177 + reg = <0x13050000 0x1000>;
10184 + reg = <0x13040000 0x10000>,
10185 + <0x13100000 0x10000>;
10192 + reg = <0x13130000 0x10000>;
10199 + reg = <0x13070000 0x10000>;
10206 + reg = <0x13060000 0x10000>;
10213 + reg = <0x10080000 0x4000>;
10220 + reg = <0x13140000 0x10000>;
10227 + reg = <0x13120000 0x10000>;
10233 + reg = <0x13010000 0x10000>;
10243 @@ -0,0 +1,211 @@
10298 + reg = <0x40000000 0xC0000000>;
10335 + spidev@0 {
10337 + reg = <0>;
10338 + pl022,interface = <0>;
10339 + pl022,com-mode = <0>;
10348 + spidev@0 {
10350 + reg = <0>;
10351 + pl022,interface = <0>;
10352 + pl022,com-mode = <0>;
10363 + phy0: ethernet-phy@0 {
10364 + reg = <0>;
10378 + reg = <0>;
10386 + reg = <0>;
10460 @@ -0,0 +1,719 @@
10489 + #size-cells = <0>;
10492 + cpu@0 {
10496 + reg = <0>;
10536 + reg = <0x11010000 0x4490>;
10542 + #address-cells = <0>;
10544 + reg = <0x12401000 0x1000>,
10545 + <0x12402000 0x2000>;
10550 + interrupts = <1 13 0xf08>,
10551 + <1 14 0xf08>;
10564 + #clock-cells = <0>;
10570 + reg = <0x10280000 0x1000>;
10575 + resets = <&clock 0x2a80 0>;
10579 + devid = <0>;
10586 + reg = <0x11020000 0x4000>;
10587 + reboot-offset = <0x4>;
10599 + reg = <0x11040000 0x1000>;
10608 + reg = <0x11041000 0x1000>;
10619 + reg = <0x11042000 0x1000>;
10630 + reg = <0x11043000 0x1000>;
10641 + reg = <0x11044000 0x1000>;
10653 + reg = <0x11060000 0x1000>;
10661 + reg = <0x11061000 0x1000>;
10669 + arm,primecell-periphid = <0x00800022>;
10670 + reg = <0x11070000 0x1000>;
10675 + #size-cells = <0>;
10683 + arm,primecell-periphid = <0x00800022>;
10684 + reg = <0x11071000 0x1000>;
10689 + #size-cells = <0>;
10697 + reg = <0x11090000 0x1000>;
10707 + reg = <0x11091000 0x1000>;
10717 + reg = <0x11092000 0x1000>;
10727 + reg = <0x11093000 0x1000>;
10737 + reg = <0x11094000 0x1000>;
10747 + reg = <0x11095000 0x1000>;
10757 + reg = <0x11096000 0x1000>;
10767 + reg = <0x11097000 0x1000>;
10777 + reg = <0x11098000 0x1000>;
10787 + reg = <0x11099000 0x1000>;
10797 + reg = <0x1109a000 0x1000>;
10807 + reg = <0x1109b000 0x1000>;
10817 + reg = <0x1109c000 0x1000>;
10827 + reg = <0x1109d000 0x1000>;
10837 + reg = <0x11110000 0x10000>;
10846 + reg = <0x10000000 0x10000>, <0x0F000000 0x100000>;
10849 + max-dma-size = <0x2000>;
10851 + #size-cells = <0>;
10858 + #size-cells = <0>;
10866 + #size-cells = <0>;
10873 + reg = <0x102a1100 0x10>,<0x11024218 0x4>,<0x11020448 0x4>;
10876 + resets = <&clock 0x37d0 0>;
10879 + #size-cells = <0>;
10884 + reg = <0x102a0000 0x1000>,<0x102a1300 0x200>;
10887 + resets = <&clock 0x37c8 0>;
10893 + reg = <0x10ff0000 0x10000>;
10897 + mmc0: eMMC@0x10020000 {
10899 + reg = <0x10020000 0x1000>;
10903 + resets = <&clock 0x34c0 16>, <&clock 0x34c4 1>;
10917 + devid = <0>;
10921 + mmc1: SD@0x10200000 {
10923 + reg = <0x10020000 0x1000>;
10927 + resets = <&clock 0x34c0 16>, <&clock 0x34c4 1>;
10940 + mmc2: SDIO@0x10200000 {
10942 + reg = <0x10020000 0x1000>;
10946 + resets = <&clock 0x34c0 16>, <&clock 0x34c4 1>;
10962 + reg = <0x110138c0 0x280>, <0x11024188 0x10>, <0x11020444 0x4>;
10965 + xhci_0:xhci_0@0x10300000 {
10967 + reg = <0x10300000 0x10000>;
10968 + interrupts = <0 79 4>;
10972 + xhci_1:xhci_1@0x10340000 {
10974 + reg = <0x10340000 0x10000>;
10975 + interrupts = <0 80 4>;
10979 + sata_phy: phy@0x10390000 {
10981 + reg = <0x10390000 0x10000>;
10983 + #phy-cells = <0>;
10986 + ahci: sata@0x10390000 {
10988 + reg = <0x10390000 0x1000>;
10993 + #size-cells = <0>;
10996 + cipher: cipher@0x10100000 {
10998 + reg = <0x10100000 0x10000>;
11007 + otp: otp@0x10200000 {
11009 + reg = <0x10200000 0x1000>;
11013 + wdg: wdg@0x11030000 {
11015 + reg = <0x11030000 0x1000>;
11035 + reg = <0x11014500 0xBB00>,
11036 + <0x11020450 0x3BB0>,
11037 + <0x11130000 0x10000>,
11038 + <0X11024000 0x5000>;
11042 + vi: vi@0x17400000 {
11044 + reg = <0x17400000 0x40000>,
11045 + <0x11003000 0x1000>;
11047 + interrupts = <0 93 4>,
11052 + mipi: mipi@0x173c0000 {
11054 + reg = <0x173c0000 0x10000>;
11056 + interrupts = <0 92 4>;
11060 + vpss: vpss@0x17900000 {
11062 + reg = <0x17900000 0x10000>;
11064 + interrupts = <0 102 4>;
11068 + vgs: vgs@0x17240000 {
11070 + reg = <0x17240000 0x10000>;
11072 + interrupts = <0 105 4>;
11076 + vo: vo@0x17a00000 {
11078 + reg = <0x17a00000 0x40000>;
11080 + interrupts = <0 95 4>;
11084 + hifb: hifb@0x17a00000 {
11087 + interrupts = <0 96 4>;
11091 + hdmi: hdmi@0x17B40000 {
11093 + reg = <0x17B40000 0x20000>,<0x17BC0000 0x10000>;
11095 + interrupts = <0 98 4>,<0 99 4>,<0 100 4>;
11099 + venc: venc@0x17140000 {
11101 + reg = <0x17140000 0x10000>, <0x171c0000 0x10000>;
11103 + interrupts = <0 111 4>, <0 113 4>;
11107 + vdh: vdh@0x17100000 {
11109 + reg = <0x17100000 0x10000>;
11111 + interrupts = <0 109 4>,<0 108 4>;
11115 + jpegd: jpegd@0x17180000 {
11117 + reg = <0x17180000 0x10000>;
11119 + interrupts = <0 114 4>;
11123 + vda: vda@0x170c0000 {
11125 + reg = <0x170c0000 0x10000>;
11127 + interrupts = <0 119 4>;
11131 + nnie: nnie@0x170D0000 {
11133 + reg = <0x170D0000 0x10000>;
11135 + interrupts = <0 116 4>;
11139 + ive: ive@0x17000000 {
11141 + reg = <0x17000000 0x10000>;
11143 + interrupts = <0 117 4>;
11147 + mau: mau@0x170E0000 {
11149 + reg = <0x170E0000 0x10000>;
11151 + interrupts = <0 118 4>;
11157 + reg = <0x17c00000 0x10000>;
11159 + interrupts = <0 97 4>;
11163 + tde: tde@0x17280000 {
11165 + reg = <0x17280000 0x10000>;
11167 + interrupts = <0 106 4>;
11171 + ir: ir@0x110F0000 {
11173 + reg = <0x110F0000 0x10000>;
11175 + interrupts = <0 2 4>;
11185 @@ -0,0 +1,146 @@
11213 + linux,initrd-start = <0x42000000>;
11218 + #size-cells = <0>;
11221 + cpu@0 {
11224 + reg = <0>;
11238 + reg = <0x40000000 0xc0000000>;
11253 + reg = <0>;
11262 + reg = <0>;
11273 + reg = <0>;
11301 + spidev@0 {
11303 + reg = <0>;
11304 + pl022,interface = <0>;
11305 + pl022,com-mode = <0>;
11312 + pl022,interface = <0>;
11313 + pl022,com-mode = <0>;
11320 + pl022,interface = <0>;
11321 + pl022,com-mode = <0>;
11327 + pl022,interface = <0>;
11328 + pl022,com-mode = <0>;
11337 @@ -0,0 +1,508 @@
11376 + #address-cells = <0>;
11379 + reg = <0x10301000 0x1000>, <0x10300100 0x100>;
11391 + reg = <0x12040000 0x1000>;
11398 + reg = <0x12050000 0x1000>;
11405 + offset = <0x4>;
11406 + mask = <0xdeadbeef>;
11417 + reg = <0x10700000 0x10000>;
11425 + reg = <0x10060000 0x1000>;
11429 + resets = <&clock 0x144 0>;
11437 + reg = <0x12080000 0x1000>;
11446 + reg = <0x12090000 0x1000>;
11455 + reg = <0x120a0000 0x1000>;
11464 + reg = <0x12130000 0x1000>;
11473 + reg = <0x12040000 0x10000>, <0x12120000 0x10000>;
11474 + #phy-cells = <0>;
11479 + reg = <0x12040000 0x10000>, <0x12120000 0x10000>, <0x11000000 0x100000>;
11480 + #phy-cells = <0>;
11483 + xhci@0x11000000 {
11485 + reg = <0x11000000 0x10000>;
11486 + interrupts = <0 22 4>;
11490 + ehci@0x100c0000 {
11492 + reg = <0x100c0000 0x10000>;
11493 + interrupts = <0 19 4>;
11496 + ohci@0x100b0000 {
11498 + reg = <0x100b0000 0x10000>;
11499 + interrupts = <0 18 4>;
11504 + reg = <0x120c0000 0x100>;
11508 + io-size = <0x1000>;
11509 + id = <0>;
11515 + reg = <0x122e0000 0x100>;
11519 + io-size = <0x1000>;
11526 + arm,primecell-periphid = <0x00800022>;
11527 + reg = <0x120d0000 0x1000>, <0x12120014 0x4>;
11533 + #size-cells = <0>;
11534 + hisi,spi_cs_sb = <0>;
11535 + hisi,spi_cs_mask_bit = <0x00000007>;
11541 + reg = <0x12000000 0x20>, /* clocksource */
11542 + <0x12000020 0x20>, /* local timer for each cpu */
11543 + <0x12010000 0x20>;
11556 + reg = <0x12020000 0x1000>;
11568 + reg = <0x12030000 0x1000>;
11578 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
11581 + max-dma-size = <0x2000>;
11583 + #size-cells = <0>;
11590 + #size-cells = <0>;
11598 + #size-cells = <0>;
11604 + reg = <0x10010000 0x10000>, <0x15000000 0x10000>;
11608 + #size-cells = <0>;
11613 + reg = <0x100a03c0 0x20>;
11618 + resets = <&clock 0x14c 5>;
11621 + #size-cells = <0>;
11626 + reg = <0x100a0000 0x1000>,<0x1204015c 0x4>,
11627 + <0x100a3014 0x4>;
11635 + resets = <&clock 0x14c 0>,
11636 + <&clock 0x14c 2>;
11645 + reg = <0x11010000 0x10000>;
11647 + #phy-cells = <0>;
11652 + reg = <0x11010000 0x1000>;
11657 + #size-cells = <0>;
11660 + pcie0: pcie0@0x11020000 {
11663 + bus-range = <0x0 0xff>;
11666 + ranges = <0x02000000 0x00 0x28000000 0x28000000 0x00 0x8000000>;
11668 + interrupt-map-mask = <0x0 0x0 0x0 0x4>;
11669 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
11670 + pcie_controller = <0>;
11671 + dev_mem_size = <0x8000000>;
11672 + dev_conf_size = <0x8000000>;
11673 + pcie_dbi_base = <0x11020000>;
11674 + ep_conf_base = <0x20000000>;
11677 + pcie1: pcie1@0x11030000 {
11680 + bus-range = <0x0 0xff>;
11683 + ranges = <0x02000000 0x00 0x38000000 0x38000000 0x00 0x8000000>;
11685 + interrupt-map-mask = <0x0 0x0 0x0 0x4>;
11686 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
11688 + dev_mem_size = <0x8000000>;
11689 + dev_conf_size = <0x8000000>;
11690 + pcie_dbi_base = <0x11030000>;
11691 + ep_conf_base = <0x30000000>;
11694 + pcie_mcc: pcie_mcc@0x0 {
11719 + reg = <0x12040000 0x10000>, <0x12050000 0x10000>,
11720 + <0x12110000 0x10000>, <0x12120000 0x10000>;
11727 + reg = <0x120b0000 0x10000>;
11730 + hiir: hiir@0x12140000 {
11733 + reg = <0x12140000 0x10000>;
11736 + cipher: cipher@0x10070000 {
11739 + reg = <0x10070000 0x2000>;
11745 + reg = <0x130C0000 0x40000>;
11751 + reg = <0x13020000 0x10000>;
11760 + reg = <0x13080000 0x5000>,
11761 + <0x13110000 0x5000>,
11762 + <0x13180000 0x5000>;
11769 + reg = <0x13150000 0x5000>;
11775 + reg = <0x13090000 0x10000>;
11781 + reg = <0x13050000 0x1000>;
11790 + reg = <0x13040000 0x10000>,
11791 + <0x13100000 0x10000>,
11792 + <0x13170000 0x10000>,
11793 + <0x13190000 0x10000>;
11800 + reg = <0x13130000 0x10000>;
11807 + reg = <0x13070000 0x10000>;
11814 + reg = <0x13060000 0x10000>;
11821 + reg = <0x10080000 0x4000>;
11828 + reg = <0x13140000 0x10000>;
11835 + reg = <0x13120000 0x10000>;
11841 + reg = <0x13010000 0x10000>;
11851 @@ -0,0 +1,192 @@
11880 + reg = <0x80000000 0x20000000>;
11913 + reg = <0>;
11921 + reg = <0>;
11958 + 0x0070 0x2
11959 + 0x0078 0x2
11960 + 0x007c 0x2
11961 + 0x0090 0x2
11962 + 0x0094 0x2
11967 + 0x0040 0x3 /*I2S_SD_RX*/
11968 + 0x0044 0x3 /*I2S_MCLK*/
11969 + 0x0048 0x3 /*I2S_WS*/
11970 + 0x004c 0x3 /*I2S_BCLK*/
11971 + 0x0050 0x3 /*I2S_SD_TX*/
11978 + 0x120f08ac 0xb0
11979 + 0x120f08b4 0xb0
11980 + 0x120f08b8 0xb0
11981 + 0x120f08cc 0xb0
11982 + 0x120f08d0 0xb0
11985 + 0x120f0868 0x80
11986 + 0x120f086c 0xa0
11987 + 0x120f0870 0xa0
11988 + 0x120f0874 0xa0
11989 + 0x120f0878 0xa0
11992 + 0x12120078 0x55322100 /* JPGD - JPGE - TFE - VGS - VDH - A7 - VDP - AIAO */
11993 + 0x1212007c 0x65665526 /* FMC - DMA1 - DMA9 - DDRT - SATA - ETH1 - ETH0 - VOIE */
11994 + 0x12120080 0x66666666 /* - - - - - - CIPHER - USB */
11995 + 0x12120084 0x55522100 /* JPGD - JPGE - TFE - VGS - VDH - A7 - VDP - AIAO */
11996 + 0x12120088 0x65665526 /* FMC - DMA1 - DMA9 - DDRT - SATA - ETH1 - ETH0 - VOIE */
11997 + 0x1212008c 0x66626666 /* - - - - - - CIPHER - USB */
11998 + 0x12120094 0x10 /* aio_vdp_axi_pri*/
11999 + 0x12120090 0x80020000 /* aio_vdp_axi_timeout*/
12000 + 0x12110020 0x000fff01 /* AXI_ACTION[19:8]:wr_rcv_mode=0,12ports */
12001 + 0x12110200 0x00200000 /* ports0 */
12002 + 0x12110210 0x00300000 /* ports1 */
12003 + 0x12110220 0x00300000 /* ports2 */
12004 + 0x12110230 0x00300000 /* ports3 */
12005 + 0x12110240 0x00300000 /* ports4 */
12006 + 0x12110250 0x00300000 /* ports5 */
12007 + 0x12110260 0x00300000 /* ports6 */
12008 + 0x12110270 0x00300000 /* ports7 */
12009 + 0x12110204 0x76543210 /* ports0 */
12010 + 0x12110214 0x76543210 /* ports1 */
12011 + 0x12110224 0x76543210 /* ports2 */
12012 + 0x12110234 0x76543210 /* ports3 */
12013 + 0x12110244 0x76543210 /* ports4 */
12014 + 0x12110254 0x76543210 /* ports5 */
12015 + 0x12110264 0x76543210 /* ports6 */
12016 + 0x12110274 0x76543210 /* ports7 */
12017 + 0x12110208 0x76543210 /* ports0 */
12018 + 0x12110218 0x76543210 /* ports1 */
12019 + 0x12110228 0x76543210 /* ports2 */
12020 + 0x12110238 0x76543210 /* ports3 */
12021 + 0x12110248 0x76543210 /* ports4 */
12022 + 0x12110258 0x76543210 /* ports5 */
12023 + 0x12110268 0x76543210 /* ports6 */
12024 + 0x12110278 0x76543210 /* ports7 */
12025 + 0x12114000 0x00000002 /*qosb_push_ctrl */
12026 + 0x1211410c 0x0000000a /*qosb_dmc_lvl */
12027 + 0x12114110 0x0000000a /*qosb_dmc_lvl */
12028 + 0x1211408c 0xb3032010 /*qosb_wbuf_ctrl */
12029 + 0x12114090 0xb3032010 /*qosb_wbuf_ctrl */
12030 + 0x121140f4 0x00000033 /*row-hit enable */
12031 + 0x121140ec 0x00000044 /*row-hit */
12032 + 0x121140f0 0x00003333 /*row-hit */
12033 + 0x121141f4 0x00000000 /*qosb_wbuf_pri_ctrl*/
12034 + 0x121141f0 0x00000001 /*enable qosbuf timeout,through prilvl to remap timeout level*/
12035 + 0x1211409c 0x0000000a /* wr_tout3 ~wr_tout0 */
12036 + 0x121140ac 0x0000000a /* rd_tout3 ~rd_tout0 */
12037 + 0x121141f8 0x00800002 /* qosb_rhit_ctrl,open_window=128,close_window=2*/
12040 + pinctrl-0 = <&i2s1_pmux>;
12049 @@ -0,0 +1,445 @@
12085 + #size-cells = <0>;
12087 + cpu@0 {
12090 + reg = <0>;
12100 + reg = <0x12040000 0x1000>;
12106 + #address-cells = <0>;
12109 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
12121 + interrupts = <0 54 4>;
12126 + reg = <0x12050000 0x1000>;
12133 + offset = <0x4>;
12134 + mask = <0xdeadbeef>;
12146 + interrupts = <0 1 4>;
12147 + reg = <0x12000000 0x1000>;
12158 + interrupts = <0 2 4>;
12159 + reg = <0x12010000 0x1000>;
12170 + interrupts = <0 3 4>;
12171 + reg = <0x12020000 0x1000>;
12182 + interrupts = <0 4 4>;
12183 + reg = <0x12030000 0x1000>;
12193 + reg = <0x12080000 0x1000>;
12194 + interrupts = <0 6 4>;
12202 + reg = <0x12090000 0x1000>;
12203 + interrupts = <0 7 4>;
12211 + reg = <0x120a0000 0x1000>;
12212 + interrupts = <0 8 4>;
12223 + reg = <0x120c0000 0x1000>;
12230 + reg = <0x10030000 0x10000>;
12232 + #phy-cells = <0>;
12237 + reg = <0x10030000 0x1000>;
12238 + interrupts = <0 17 4>;
12242 + #size-cells = <0>;
12247 + reg = <0x10011100 0x10>, <0x12120064 0x4>,
12248 + <0x12121000 0x4>;
12252 + resets = <&clock 0xc4 3>, <&clock 0xc4 9>;
12255 + #size-cells = <0>;
12261 + reg = <0x10010000 0x1000>,<0x10011300 0x200>;
12262 + interrupts = <0 11 4>;
12264 + resets = <&clock 0xc4 0>;
12270 + reg = <0x12040000 0x1000>, <0x12120000 0x10000>;
12273 + ehci@0x11010000 {
12275 + reg = <0x11010000 0x10000>;
12276 + interrupts = <0 19 4>;
12279 + ohci@0x11000000 {
12281 + reg = <0x11000000 0x10000>;
12282 + interrupts = <0 18 4>;
12287 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
12290 + max-dma-size = <0x2000>;
12292 + #size-cells = <0>;
12294 + hisfc:spi-nor@0 {
12299 + #size-cells = <0>;
12302 + hisnfc:spi-nand@0 {
12307 + #size-cells = <0>;
12313 + reg = <0x11020000 0x1000>;
12314 + interrupts = <0 14 4>;
12317 + resets = <&clock 0xc8 4>;
12325 + reg = <0x12150000 0x10000>;
12326 + interrupts = <0 55 4>;
12335 + reg = <0x12160000 0x10000>;
12336 + interrupts = <0 56 4>;
12345 + reg = <0x12170000 0x10000>;
12346 + interrupts = <0 57 4>;
12355 + reg = <0x12180000 0x10000>;
12356 + interrupts = <0 58 4>;
12365 + reg = <0x12190000 0x10000>;
12366 + interrupts = <0 59 4>;
12375 + reg = <0x121a0000 0x10000>;
12376 + interrupts = <0 60 4>;
12385 + reg = <0x120F0000 0x3A8>;
12394 + pinctrl-single,gpio-range = <&range 0 54 0
12395 + &range 55 6 1 &range 61 5 0>;
12416 + reg = <0x12040000 0x10000>, <0x12050000 0x10000>,
12417 + <0x12110000 0x10000>, <0x12120000 0x10000>;
12423 + interrupts = <0 5 4>;
12424 + reg = <0x120b0000 0x10000>;
12429 + interrupts = <0 34 4>;
12430 + reg = <0x13020000 0x10000>;
12435 + interrupts = <0 28 4>;
12436 + reg = <0x13100000 0x10000>;
12441 + interrupts = <0 32 4>;
12442 + reg = <0x13040000 0x10000>, <0x130500d0 0x10000>;
12448 + interrupts = <0 21 4>, <0 23 4>;
12450 + reg = <0x13200000 0xc000>, <0x1320c000 0x4000>;
12456 + interrupts = <0 29 4>;
12457 + reg = <0x13130000 0x1000>;
12462 + interrupts = <0 31 4>;
12464 + reg = <0x13110000 0x10000>;
12468 + hiir: hiir@0x12140000 {
12470 + interrupts = <0 9 4>;
12471 + reg = <0x12140000 0x10000>;
12474 + cipher: cipher@0x11030000 {
12476 + interrupts = <0 13 4>;
12477 + reg = <0x11030000 0x10000>;
12482 + interrupts = <0 30 4>;
12483 + reg = <0x13120000 0x10000>;
12500 @@ -0,0 +1,25 @@
12531 @@ -0,0 +1,25 @@
12562 @@ -0,0 +1,275 @@
12595 + #size-cells = <0>;
12597 + cpu@0 {
12600 + reg = <0>;
12607 + reg = <0x32000000 0x10000000>;
12662 + spidev@0 {
12664 + reg = <0>;
12665 + pl022,interface = <0>;
12666 + pl022,com-mode = <0>;
12674 + spidev@0 {
12676 + reg = <0>;
12677 + pl022,interface = <0>;
12678 + pl022,com-mode = <0>;
12686 + spidev@0 {
12688 + reg = <0>;
12689 + pl022,interface = <0>;
12690 + pl022,com-mode = <0>;
12698 + spidev@0 {
12700 + reg = <0>;
12701 + pl022,interface = <0>;
12702 + pl022,com-mode = <0>;
12710 + spidev@0 {
12712 + reg = <0>;
12713 + pl022,interface = <0>;
12714 + pl022,com-mode = <0>;
12733 + reg = <0>;
12742 + reg = <0>;
12750 + reg = <0>;
12843 @@ -0,0 +1,974 @@
12907 + #address-cells = <0>;
12910 + reg = <0x04C01000 0x1000>, <0x04C02000 0x1000>;
12919 + reg = <0x04510000 0x10000>;
12925 + #clock-cells = <0>;
12932 + interrupts = <1 13 0xf08>,
12933 + <1 14 0xf08>;
12940 + interrupts = <0 74 4>;
12941 + reg = <0x045E0000 0x1000>;
12960 + reg = <0x04540000 0x1000>;
12961 + interrupts = <0 36 4>;
12969 + reg = <0x04541000 0x1000>;
12970 + interrupts = <0 37 4>;
12978 + reg = <0x04542000 0x1000>;
12979 + interrupts = <0 38 4>;
12987 + reg = <0x04543000 0x1000>;
12988 + interrupts = <0 39 4>;
12996 + reg = <0x04544000 0x1000>;
12997 + interrupts = <0 40 4>;
13005 + reg = <0x04560000 0x1000>;
13013 + reg = <0x04561000 0x1000>;
13021 + reg = <0x04562000 0x1000>;
13029 + reg = <0x04563000 0x1000>;
13037 + reg = <0x04564000 0x1000>;
13045 + reg = <0x04565000 0x1000>;
13053 + reg = <0x04566000 0x1000>;
13061 + reg = <0x04567000 0x1000>;
13069 + reg = <0x04568000 0x1000>;
13077 + reg = <0x04569000 0x1000>;
13085 + arm,primecell-periphid = <0x00800022>;
13086 + reg = <0x04570000 0x1000>;
13087 + interrupts = <0 155 4>;
13091 + #size-cells = <0>;
13098 + arm,primecell-periphid = <0x00800022>;
13099 + reg = <0x04571000 0x1000>;
13100 + interrupts = <0 156 4>;
13104 + #size-cells = <0>;
13111 + arm,primecell-periphid = <0x00800022>;
13112 + reg = <0x04572000 0x1000>;
13113 + interrupts = <0 157 4>;
13117 + #size-cells = <0>;
13124 + arm,primecell-periphid = <0x00800022>;
13125 + reg = <0x04573000 0x1000>;
13126 + interrupts = <0 158 4>;
13130 + #size-cells = <0>;
13137 + arm,primecell-periphid = <0x00800022>;
13138 + reg = <0x04574000 0x1000>;
13139 + interrupts = <0 159 4>;
13143 + #size-cells = <0>;
13150 + reg = <0x045f0000 0x1000>;
13151 + interrupts = <0 56 4>;
13160 + reg = <0x045f1000 0x1000>;
13161 + interrupts = <0 57 4>;
13170 + reg = <0x045f2000 0x1000>;
13171 + interrupts = <0 58 4>;
13180 + reg = <0x045f3000 0x1000>;
13181 + interrupts = <0 59 4>;
13190 + reg = <0x045f4000 0x1000>;
13191 + interrupts = <0 60 4>;
13200 + reg = <0x045f5000 0x1000>;
13201 + interrupts = <0 61 4>;
13210 + reg = <0x045f6000 0x1000>;
13211 + interrupts = <0 62 4>;
13220 + reg = <0x045f7000 0x1000>;
13221 + interrupts = <0 63 4>;
13230 + reg = <0x045f8000 0x1000>;
13231 + interrupts = <0 64 4>;
13240 + reg = <0x045f9000 0x1000>;
13241 + interrupts = <0 65 4>;
13250 + reg = <0x045fa000 0x1000>;
13251 + interrupts = <0 66 4>;
13260 + reg = <0x045fb000 0x1000>;
13261 + interrupts = <0 67 4>;
13270 + reg = <0x045fc000 0x1000>;
13271 + interrupts = <0 68 4>;
13280 + reg = <0x045fd000 0x1000>;
13281 + interrupts = <0 69 4>;
13290 + reg = <0x045fe000 0x1000>;
13291 + interrupts = <0 70 4>;
13299 + interrupts = <0 30 4>;
13300 + reg = <0x04500000 0x1000>;
13307 + reg = <0x04500000 0x20>, /* clocksource */
13308 + <0x04500020 0x20>, /* local timer for each cpu */
13309 + <0x04501000 0x20>;
13310 + interrupts = <0 30 4>, /* irq of local timer */
13311 + <0 31 4>;
13323 + reg = <0x04c10000 0x1000>;
13324 + interrupts = <0 2 4>;
13327 + resets = <&clock 0x14c 4>;
13336 + reg = <0x04040000 0x1000>;
13337 + interrupts = <0 98 4>;
13340 + resets = <&clock 0x16c 4>;
13348 + reg = <0x04520000 0x1000>;
13355 + offset = <0x4>;
13356 + mask = <0xdeadbeef>;
13362 + reg = <0x04528000 0x10000>;
13367 + reg = <0x04058000 0x100>;
13372 + reg = <0x047B8000 0x100>;
13377 + reg = <0x047E0000 0x100>;
13382 + reg = <0x047E8000 0x100>;
13387 + reg = <0x04510000 0x1000>, <0x04528000 0x1000>, <0x04520000 0x1000>;
13388 + #phy-cells = <0>;
13391 + xhci_0@0x04110000 {
13393 + reg = <0x04110000 0x10000>;
13394 + interrupts = <0 111 4>;
13399 + xhci_1@0x04120000 {
13401 + reg = <0x04120000 0x10000>;
13402 + interrupts = <0 112 4>;
13407 + hidwc3_0@0x04110000 {
13409 + reg = <0x04110000 0x10000>, <0x04510000 0x1000>, <0x04520000 0x1000>;
13410 + interrupts = <0 111 4>;
13419 + hidwc3_1@0x04120000 {
13421 + reg = <0x04120000 0x10000>, <0x04510000 0x1000>, <0x04520000 0x1000>;
13422 + interrupts = <0 112 4>;
13432 + reg = <0x04d00000 0x1000>;
13433 + ranges = <0x0 0x04d00000 0x6000>;
13438 + reg = <0x2000 0x1000>;
13444 + reg = <0x3000 0x1000>;
13451 + reg = <0x040e03c0 0x20>;
13453 + resets = <&clock 0x174 14>;
13456 + #size-cells = <0>;
13461 + reg = <0x040e0000 0x1000>,<0x040e300c 0x4>;
13462 + interrupts = <0 89 4>;
13469 + resets = <&clock 0x174 0>,
13470 + <&clock 0x174 4>;
13479 + reg = <0x04020000 0x1000>, <0x0f000000 0x1000000>;
13482 + max-dma-size = <0x2000>;
13484 + #size-cells = <0>;
13491 + #size-cells = <0>;
13499 + #size-cells = <0>;
13507 + #size-cells = <0>;
13511 + mmc0: eMMC@0x04030000 {
13513 + reg = <0x04030000 0x1000>, <0x04048000 0x1000>;
13514 + interrupts = <0 92 4>;
13517 + resets = <&clock 0x1a8 27>, <&clock 0x1a8 29>, <&clock 0x1a8 30>;
13527 + devid = <0>;
13531 + mmc1: SD@0x040c0000 {
13533 + reg = <0x040c0000 0x1000>;
13534 + interrupts = <0 87 4>;
13537 + resets = <&clock 0x1ec 27>, <&clock 0x1ec 29>, <&clock 0x1ec 30>;
13552 + mmc2: SD@0x040d0000 {
13554 + reg = <0x040d0000 0x1000>;
13555 + interrupts = <0 88 4>;
13558 + resets = <&clock 0x214 27>, <&clock 0x214 29>, <&clock 0x214 30>;
13573 + cipher: cipher@0x04060000 {
13575 + reg = <0x04060000 0x10000>, <0x04080000 0x10000>;
13577 + interrupts = <0 93 4>, <0 94 4>, <0 93 4>, <0 94 4>, <0 95 4>, <0 85 4>;
13583 + reg = <0x045c0000 0x1000>;
13584 + interrupts = <0 55 4>;
13589 + reg = <0x04550000 0x1000>;
13590 + interrupts = <0 28 4>;
13595 + reg = <0x04530000 0x1000>;
13614 + reg = <0x04510000 0x10000>, <0x04520000 0x8000>,
13615 + <0x04600000 0x10000>, <0x04528000 0x8000>;
13621 + reg = <0x04a40000 0x10000>, <0x04a80000 0x10000>;
13623 + interrupts = <0 128 4>, <0 129 4>;
13629 + reg = <0x04780000 0x10000>;
13631 + interrupts = <0 120 4>;
13637 + reg = <0x04800000 0x200000>, <0x04a00000 0x40000>;
13639 + interrupts = <0 127 4>, <0 125 4>;
13645 + reg = <0x04a20000 0x20000>;
13647 + interrupts = <0 127 4>;
13653 + reg = <0x04b20000 0x10000>;
13655 + interrupts = <0 126 4>;
13661 + reg = <0x04a90000 0x10000>;
13663 + interrupts = <0 130 4>;
13669 + reg = <0x04700000 0x20000>;
13671 + interrupts = <0 117 4>;
13677 + reg = <0x04700000 0x20000>;
13679 + interrupts = <0 118 4>;
13685 + reg = <0x04ad0000 0x10000>;
13687 + interrupts = <0 149 4>;
13693 + reg = <0x04b00000 0x10000>;
13695 + interrupts = <0 139 4>;
13701 + reg = <0x04aa0000 0x10000>;
13703 + interrupts = <0 134 4>;
13709 + reg = <0x04ab0000 0x10000>;
13711 + interrupts = <0 133 4>;
13717 + reg = <0x04790000 0x10000>;
13719 + interrupts = <0 138 4>;
13725 + reg = <0x04ac0000 0x10000>;
13727 + interrupts = <0 131 4>;
13733 + reg = <0x047c0000 0x8000>, <0x047c8000 0x8000>;
13735 + interrupts = <0 115 4>, <0 132 4>;
13745 + reg = <0x047d0000 0x10000>;
13747 + interrupts = <0 114 4>, <0 113 4>;
13753 + reg = <0x04740000 0x30000>;
13759 + reg = <0x047a0000 0x10000>,<0x047b0000 0x10000>,<0x04510000 0x10000>;
13761 + interrupts = <0 119 4>,<0 151 4>;
13765 + nnie: nnie@0x04C30000 {
13767 + reg = <0x04C30000 0x10000>;
13769 + interrupts = <0 1 4>;
13773 + dpu_rect: dpu_rect@0x04AE0000 {
13775 + reg = <0x04AE0000 0x10000>;
13777 + interrupts = <0 135 4>;
13781 + dpu_match: dpu_match@0x04AE0000 {
13783 + reg = <0x04AE0000 0x10000>;
13785 + interrupts = <0 136 4>;
13789 + dsp: dsp@0x04C20000 {
13791 + reg = <0x04C20000 0x10000>;
13795 + ive: ive@0x04B10000 {
13797 + reg = <0x04B10000 0x10000>;
13799 + interrupts = <0 147 4>;
13805 + reg = <0x045d0000 0x1000>;
13806 + interrupts = <0 83 4>;
13807 + resets = <&clock 0x194 16>;
13814 + reg = <0x045A0000 0x10000>;
13823 @@ -0,0 +1,250 @@
13853 + reg = <0x82000000 0x20000000>;/* system memory base */
13917 + spidev@0 {
13919 + reg = <0>;
13920 + pl022,interface = <0>;
13921 + pl022,com-mode = <0>;
13929 + spidev@0 {
13931 + reg = <0>;
13932 + pl022,interface = <0>;
13933 + pl022,com-mode = <0>;
13939 + pl022,interface = <0>;
13940 + pl022,com-mode = <0>;
13948 + spidev@0 {
13950 + reg = <0>;
13951 + pl022,interface = <0>;
13952 + pl022,com-mode = <0>;
13975 + reg = <0>;
13983 + reg = <0>;
14079 @@ -0,0 +1,896 @@
14136 + #size-cells = <0>;
14139 + cpu@0 {
14143 + reg = <0>;
14161 + reg = <0x12010000 0x1000>;
14167 + #address-cells = <0>;
14170 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
14176 + interrupts = <1 13 0xf08>,
14177 + <1 14 0xf08>;
14190 + #clock-cells = <0>;
14196 + #clock-cells = <0>;
14202 + interrupts = <0 54 4>;
14207 + reg = <0x10060000 0x1000>;
14208 + interrupts = <0 28 4>;
14212 + resets = <&clock 0x194 0>;
14216 + devid = <0>;
14224 + reg = <0x10060000 0x1000>;
14225 + interrupts = <0 28 4>;
14229 + resets = <&clock 0x194 0>;
14233 + devid = <0>;
14241 + reg = <0x12020000 0x1000>;
14242 + reboot-offset = <0x4>;
14255 + reg = <0x12000000 0x20>, /* clocksource */
14256 + <0x12000020 0x20>, /* local timer for each cpu */
14257 + <0x12001000 0x20>;
14258 + interrupts = <0 1 4>, /* irq of local timer */
14259 + <0 2 4>;
14269 + interrupts = <0 3 4>;
14270 + reg = <0x12002000 0x1000>;
14278 + arm,primecell-periphid = <0x00141805>;
14279 + reg = <0x12051000 0x1000>;
14287 + reg = <0x12070000 0x10000>;
14289 + resets = <&clock 0x1bc 6>;
14296 + reg = <0x120a0000 0x1000>;
14297 + interrupts = <0 6 4>;
14305 + reg = <0x120a1000 0x1000>;
14306 + interrupts = <0 7 4>;
14318 + reg = <0x120a2000 0x1000>;
14319 + interrupts = <0 8 4>;
14331 + reg = <0x120a3000 0x1000>;
14332 + interrupts = <0 9 4>;
14344 + reg = <0x120a4000 0x1000>;
14345 + interrupts = <0 10 4>;
14360 + reg = <0x120b0000 0x1000>;
14363 + dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
14371 + reg = <0x120b1000 0x1000>;
14383 + reg = <0x120b2000 0x1000>;
14394 + reg = <0x120b3000 0x1000>;
14404 + reg = <0x120b4000 0x1000>;
14415 + reg = <0x120b5000 0x1000>;
14426 + reg = <0x120b6000 0x1000>;
14437 + reg = <0x120b7000 0x1000>;
14449 + arm,primecell-periphid = <0x00800022>;
14450 + reg = <0x120c0000 0x1000>;
14451 + interrupts = <0 68 4>;
14455 + #size-cells = <0>;
14465 + arm,primecell-periphid = <0x00800022>;
14466 + reg = <0x120c1000 0x1000>, <0x12030000 0x4>;
14467 + interrupts = <0 69 4>;
14471 + #size-cells = <0>;
14474 + hisi,spi_cs_mask_bit = <0x4>;//0100
14484 + arm,primecell-periphid = <0x00800022>;
14485 + reg = <0x120c2000 0x1000>;
14486 + interrupts = <0 70 4>;
14490 + #size-cells = <0>;
14502 + interrupts = <0 10 4>;
14503 + reg = <0x10300000 0x4000>;
14509 + reg = <0x10011100 0x10>;
14514 + resets = <&clock 0x16c 3>;
14517 + #size-cells = <0>;
14523 + reg = <0x10010000 0x1000>,<0x10011300 0x200>;
14524 + interrupts = <0 32 4>;
14526 + resets = <&clock 0x16c 0>;
14532 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
14535 + max-dma-size = <0x2000>;
14537 + #size-cells = <0>;
14539 + hisfc:spi-nor@0 {
14544 + #size-cells = <0>;
14547 + hisnfc:spi-nand@0 {
14552 + #size-cells = <0>;
14556 + mmc0: himci.eMMC@0x10100000 {
14558 + reg = <0x10100000 0x1000>;
14559 + interrupts = <0 64 4>;
14562 + resets = <&clock 0x148 0>;
14570 + devid = <0>;
14574 + mmc1: himci.SD@0x100f0000 {
14576 + reg = <0x100f0000 0x1000>;
14577 + interrupts = <0 30 4>;
14580 + resets = <&clock 0x160 0>;
14593 + mmc2: himci.SD@0x10020000 {
14595 + reg = <0x10020000 0x1000>;
14596 + interrupts = <0 31 4>;
14599 + resets = <&clock 0x154 0>;
14614 + reg = <0x10060000 0x1000>;
14615 + interrupts = <0 28 4>;
14618 + resets = <&clock 0xc8 4>;
14626 + reg = <0x12010000 0x1000>;
14627 + #phy-cells = <0>;
14631 + xhci_0@0x100e0000 {
14633 + reg = <0x100e0000 0x10000>;
14634 + interrupts = <0 27 4>;
14639 + hidwc3_0@0x100e0000 {
14641 + reg = <0x100e0000 0x10000>;
14642 + interrupts = <0 27 4>;
14650 + reg = <0x120d0000 0x1000>;
14651 + interrupts = <0 16 4>;
14660 + reg = <0x120d1000 0x1000>;
14661 + interrupts = <0 17 4>;
14670 + reg = <0x120d2000 0x1000>;
14671 + interrupts = <0 18 4>;
14680 + reg = <0x120d3000 0x1000>;
14681 + interrupts = <0 19 4>;
14690 + reg = <0x120d4000 0x1000>;
14691 + interrupts = <0 20 4>;
14700 + reg = <0x120d5000 0x1000>;
14701 + interrupts = <0 21 4>;
14710 + reg = <0x120d6000 0x1000>;
14711 + interrupts = <0 22 4>;
14720 + reg = <0x120d7000 0x1000>;
14721 + interrupts = <0 23 4>;
14730 + reg = <0x120d8000 0x1000>;
14731 + interrupts = <0 24 4>;
14740 + reg = <0x120d9000 0x1000>;
14741 + interrupts = <0 25 4>;
14750 + reg = <0x120da000 0x1000>;
14751 + interrupts = <0 26 4>;
14760 + reg = <0x120db000 0x1000>;
14761 + interrupts = <0 80 4>;
14768 + cipher: cipher@0x100c0000 {
14770 + reg = <0x100c0000 0x10000>;
14772 + interrupts = <0 71 4>, <0 72 4>, <0 71 4>, <0 72 4>;
14795 + reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
14796 + <0x12060000 0x10000>, <0x12030000 0x8000>;
14802 + reg = <0x113a0000 0x10000>;
14804 + interrupts = <0 57 4>;
14810 + reg = <0x11270000 0x10000>;
14812 + interrupts = <0 63 4>;
14818 + reg = <0x11300000 0xa0000>, <0x11000000 0x40000>;
14820 + interrupts = <0 56 4>, <0 44 4>;
14826 + reg = <0x11020000 0x20000>;
14828 + interrupts = <0 56 4>;
14834 + reg = <0x11040000 0x10000>;
14836 + interrupts = <0 43 4>;
14842 + reg = <0x11240000 0x10000>;
14844 + interrupts = <0 38 4>;
14850 + reg = <0x11440000 0x40000>;
14852 + interrupts = <0 58 4>;
14858 + reg = <0x11440000 0x40000>, <0x12020000 0x8000>;
14860 + interrupts = <0 59 4>, <0 51 4>;
14866 + reg = <0x11210000 0x10000>;
14868 + interrupts = <0 35 4>;
14878 + reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
14880 + interrupts = <0 42 4>, <0 41 4>;
14886 + reg = <0x11200000 0x10000>;
14888 + interrupts = <0 34 4>;
14894 + reg = <0x11260000 0x10000>;
14896 + interrupts = <0 45 4>;
14902 + reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
14904 + interrupts = <0 40 4>, <0 36 4>;
14914 + reg = <0x10030000 0x10000>;
14916 + interrupts = <0 67 4>;
14922 + reg = <0x11400000 0x30000>;
14928 + reg = <0x113b0000 0x10000>,<0x113c0000 0x10000>,<0x12010000 0x10000>;
14930 + interrupts = <0 55 4>;
14936 + reg = <0x11100000 0x10000>,<0x11110000 0x10000>;
14938 + interrupts = <0 41 4>,<0 42 4>;
14944 + reg = <0x11230000 0x10000>;
14946 + interrupts = <0 37 4>;
14952 + reg = <0x120e0000 0x1000>;
14953 + interrupts = <0 65 4>;
14954 + resets = <&clock 0x1bc 2>;
14960 + reg = <0x120f0000 0x1000>;
14961 + interrupts = <0 75 4>;
14966 + reg = <0x12080000 0x1000>;
14967 + interrupts = <0 5 4>;
14972 + reg = <0x12050000 0x1000>;
14981 @@ -0,0 +1,250 @@
15011 + reg = <0x82000000 0x20000000>;/* system memory base */
15075 + spidev@0 {
15077 + reg = <0>;
15078 + pl022,interface = <0>;
15079 + pl022,com-mode = <0>;
15087 + spidev@0 {
15089 + reg = <0>;
15090 + pl022,interface = <0>;
15091 + pl022,com-mode = <0>;
15097 + pl022,interface = <0>;
15098 + pl022,com-mode = <0>;
15106 + spidev@0 {
15108 + reg = <0>;
15109 + pl022,interface = <0>;
15110 + pl022,com-mode = <0>;
15133 + reg = <0>;
15141 + reg = <0>;
15237 @@ -0,0 +1,895 @@
15294 + #size-cells = <0>;
15297 + cpu@0 {
15301 + reg = <0>;
15319 + reg = <0x12010000 0x1000>;
15325 + #address-cells = <0>;
15328 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
15334 + interrupts = <1 13 0xf08>,
15335 + <1 14 0xf08>;
15348 + #clock-cells = <0>;
15354 + #clock-cells = <0>;
15360 + interrupts = <0 54 4>;
15365 + reg = <0x10060000 0x1000>;
15366 + interrupts = <0 28 4>;
15370 + resets = <&clock 0x194 0>;
15374 + devid = <0>;
15382 + reg = <0x10060000 0x1000>;
15383 + interrupts = <0 28 4>;
15387 + resets = <&clock 0x194 0>;
15391 + devid = <0>;
15399 + reg = <0x12020000 0x1000>;
15400 + reboot-offset = <0x4>;
15413 + reg = <0x12000000 0x20>, /* clocksource */
15414 + <0x12000020 0x20>, /* local timer for each cpu */
15415 + <0x12001000 0x20>;
15416 + interrupts = <0 1 4>, /* irq of local timer */
15417 + <0 2 4>;
15427 + interrupts = <0 3 4>;
15428 + reg = <0x12002000 0x1000>;
15436 + arm,primecell-periphid = <0x00141805>;
15437 + reg = <0x12051000 0x1000>;
15445 + reg = <0x12070000 0x10000>;
15447 + resets = <&clock 0x1bc 6>;
15454 + reg = <0x120a0000 0x1000>;
15455 + interrupts = <0 6 4>;
15463 + reg = <0x120a1000 0x1000>;
15464 + interrupts = <0 7 4>;
15476 + reg = <0x120a2000 0x1000>;
15477 + interrupts = <0 8 4>;
15489 + reg = <0x120a3000 0x1000>;
15490 + interrupts = <0 9 4>;
15502 + reg = <0x120a4000 0x1000>;
15503 + interrupts = <0 10 4>;
15518 + reg = <0x120b0000 0x1000>;
15521 + dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
15529 + reg = <0x120b1000 0x1000>;
15541 + reg = <0x120b2000 0x1000>;
15552 + reg = <0x120b3000 0x1000>;
15562 + reg = <0x120b4000 0x1000>;
15572 + reg = <0x120b5000 0x1000>;
15583 + reg = <0x120b6000 0x1000>;
15594 + reg = <0x120b7000 0x1000>;
15606 + arm,primecell-periphid = <0x00800022>;
15607 + reg = <0x120c0000 0x1000>;
15608 + interrupts = <0 68 4>;
15612 + #size-cells = <0>;
15622 + arm,primecell-periphid = <0x00800022>;
15623 + reg = <0x120c1000 0x1000>, <0x12030000 0x4>;
15624 + interrupts = <0 69 4>;
15628 + #size-cells = <0>;
15631 + hisi,spi_cs_mask_bit = <0x4>;//0100
15641 + arm,primecell-periphid = <0x00800022>;
15642 + reg = <0x120c2000 0x1000>;
15643 + interrupts = <0 70 4>;
15647 + #size-cells = <0>;
15659 + interrupts = <0 10 4>;
15660 + reg = <0x10300000 0x4000>;
15666 + reg = <0x10011100 0x10>;
15671 + resets = <&clock 0x16c 3>;
15674 + #size-cells = <0>;
15680 + reg = <0x10010000 0x1000>,<0x10011300 0x200>;
15681 + interrupts = <0 32 4>;
15683 + resets = <&clock 0x16c 0>;
15689 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
15692 + max-dma-size = <0x2000>;
15694 + #size-cells = <0>;
15696 + hisfc:spi-nor@0 {
15701 + #size-cells = <0>;
15704 + hisnfc:spi-nand@0 {
15709 + #size-cells = <0>;
15713 + mmc0: himci.eMMC@0x10100000 {
15715 + reg = <0x10100000 0x1000>;
15716 + interrupts = <0 64 4>;
15719 + resets = <&clock 0x148 0>;
15727 + devid = <0>;
15731 + mmc1: himci.SD@0x100f0000 {
15733 + reg = <0x100f0000 0x1000>;
15734 + interrupts = <0 30 4>;
15737 + resets = <&clock 0x160 0>;
15750 + mmc2: himci.SD@0x10020000 {
15752 + reg = <0x10020000 0x1000>;
15753 + interrupts = <0 31 4>;
15756 + resets = <&clock 0x154 0>;
15771 + reg = <0x10060000 0x1000>;
15772 + interrupts = <0 28 4>;
15775 + resets = <&clock 0xc8 4>;
15783 + reg = <0x12010000 0x1000>;
15784 + #phy-cells = <0>;
15788 + xhci_0@0x100e0000 {
15790 + reg = <0x100e0000 0x10000>;
15791 + interrupts = <0 27 4>;
15796 + hidwc3_0@0x100e0000 {
15798 + reg = <0x100e0000 0x10000>;
15799 + interrupts = <0 27 4>;
15807 + reg = <0x120d0000 0x1000>;
15808 + interrupts = <0 16 4>;
15817 + reg = <0x120d1000 0x1000>;
15818 + interrupts = <0 17 4>;
15827 + reg = <0x120d2000 0x1000>;
15828 + interrupts = <0 18 4>;
15837 + reg = <0x120d3000 0x1000>;
15838 + interrupts = <0 19 4>;
15847 + reg = <0x120d4000 0x1000>;
15848 + interrupts = <0 20 4>;
15857 + reg = <0x120d5000 0x1000>;
15858 + interrupts = <0 21 4>;
15867 + reg = <0x120d6000 0x1000>;
15868 + interrupts = <0 22 4>;
15877 + reg = <0x120d7000 0x1000>;
15878 + interrupts = <0 23 4>;
15887 + reg = <0x120d8000 0x1000>;
15888 + interrupts = <0 24 4>;
15897 + reg = <0x120d9000 0x1000>;
15898 + interrupts = <0 25 4>;
15907 + reg = <0x120da000 0x1000>;
15908 + interrupts = <0 26 4>;
15917 + reg = <0x120db000 0x1000>;
15918 + interrupts = <0 80 4>;
15925 + cipher: cipher@0x100c0000 {
15927 + reg = <0x100c0000 0x10000>;
15929 + interrupts = <0 71 4>, <0 72 4>, <0 71 4>, <0 72 4>;
15952 + reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
15953 + <0x12060000 0x10000>, <0x12030000 0x8000>;
15959 + reg = <0x113a0000 0x10000>;
15961 + interrupts = <0 57 4>;
15967 + reg = <0x11270000 0x10000>;
15969 + interrupts = <0 63 4>;
15975 + reg = <0x11300000 0xa0000>, <0x11000000 0x40000>;
15977 + interrupts = <0 56 4>, <0 44 4>;
15983 + reg = <0x11020000 0x20000>;
15985 + interrupts = <0 56 4>;
15991 + reg = <0x11040000 0x10000>;
15993 + interrupts = <0 43 4>;
15999 + reg = <0x11240000 0x10000>;
16001 + interrupts = <0 38 4>;
16007 + reg = <0x11440000 0x40000>;
16009 + interrupts = <0 58 4>;
16015 + reg = <0x11440000 0x40000>, <0x12020000 0x8000>;
16017 + interrupts = <0 59 4>, <0 51 4>;
16023 + reg = <0x11210000 0x10000>;
16025 + interrupts = <0 35 4>;
16035 + reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
16037 + interrupts = <0 42 4>, <0 41 4>;
16043 + reg = <0x11200000 0x10000>;
16045 + interrupts = <0 34 4>;
16051 + reg = <0x11260000 0x10000>;
16053 + interrupts = <0 45 4>;
16059 + reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
16061 + interrupts = <0 40 4>, <0 36 4>;
16071 + reg = <0x10030000 0x10000>;
16073 + interrupts = <0 67 4>;
16079 + reg = <0x11400000 0x30000>;
16085 + reg = <0x113b0000 0x10000>,<0x113c0000 0x10000>,<0x12010000 0x10000>;
16087 + interrupts = <0 55 4>;
16093 + reg = <0x11100000 0x10000>,<0x11110000 0x10000>;
16095 + interrupts = <0 41 4>,<0 42 4>;
16101 + reg = <0x11230000 0x10000>;
16103 + interrupts = <0 37 4>;
16109 + reg = <0x120e0000 0x1000>;
16110 + interrupts = <0 65 4>;
16111 + resets = <&clock 0x1bc 2>;
16117 + reg = <0x120f0000 0x1000>;
16118 + interrupts = <0 75 4>;
16123 + reg = <0x12080000 0x1000>;
16124 + interrupts = <0 5 4>;
16129 + reg = <0x12050000 0x1000>;
16138 @@ -0,0 +1,233 @@
16168 + reg = <0x82000000 0x20000000>;/* system memory base */
16227 + spidev@0 {
16229 + reg = <0>;
16230 + pl022,interface = <0>;
16231 + pl022,com-mode = <0>;
16239 + spidev@0 {
16241 + reg = <0>;
16242 + pl022,interface = <0>;
16243 + pl022,com-mode = <0>;
16249 + pl022,interface = <0>;
16250 + pl022,com-mode = <0>;
16258 + spidev@0 {
16260 + reg = <0>;
16261 + pl022,interface = <0>;
16262 + pl022,com-mode = <0>;
16285 + reg = <0>;
16293 + reg = <0>;
16377 @@ -0,0 +1,868 @@
16432 + #size-cells = <0>;
16435 + cpu@0 {
16439 + reg = <0>;
16457 + reg = <0x12010000 0x1000>;
16463 + #address-cells = <0>;
16466 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
16472 + interrupts = <1 13 0xf08>,
16473 + <1 14 0xf08>;
16486 + #clock-cells = <0>;
16492 + #clock-cells = <0>;
16498 + interrupts = <0 54 4>;
16503 + reg = <0x10060000 0x1000>;
16504 + interrupts = <0 28 4>;
16508 + resets = <&clock 0x194 0>;
16512 + devid = <0>;
16520 + reg = <0x10060000 0x1000>;
16521 + interrupts = <0 28 4>;
16525 + resets = <&clock 0x194 0>;
16529 + devid = <0>;
16537 + reg = <0x12020000 0x1000>;
16538 + reboot-offset = <0x4>;
16551 + reg = <0x12000000 0x20>, /* clocksource */
16552 + <0x12000020 0x20>, /* local timer for each cpu */
16553 + <0x12001000 0x20>;
16554 + interrupts = <0 1 4>, /* irq of local timer */
16555 + <0 2 4>;
16565 + interrupts = <0 3 4>;
16566 + reg = <0x12002000 0x1000>;
16574 + reg = <0x120a0000 0x1000>;
16575 + interrupts = <0 6 4>;
16583 + reg = <0x120a1000 0x1000>;
16584 + interrupts = <0 7 4>;
16596 + reg = <0x120a2000 0x1000>;
16597 + interrupts = <0 8 4>;
16609 + reg = <0x120a3000 0x1000>;
16610 + interrupts = <0 9 4>;
16622 + reg = <0x120a4000 0x1000>;
16623 + interrupts = <0 10 4>;
16638 + reg = <0x120b0000 0x1000>;
16641 + dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
16649 + reg = <0x120b1000 0x1000>;
16660 + reg = <0x120b2000 0x1000>;
16672 + reg = <0x120b3000 0x1000>;
16682 + reg = <0x120b4000 0x1000>;
16692 + reg = <0x120b5000 0x1000>;
16703 + reg = <0x120b6000 0x1000>;
16714 + reg = <0x120b7000 0x1000>;
16726 + arm,primecell-periphid = <0x00800022>;
16727 + reg = <0x120c0000 0x1000>;
16728 + interrupts = <0 68 4>;
16732 + #size-cells = <0>;
16742 + arm,primecell-periphid = <0x00800022>;
16743 + reg = <0x120c1000 0x1000>, <0x12030000 0x4>;
16744 + interrupts = <0 69 4>;
16748 + #size-cells = <0>;
16751 + hisi,spi_cs_mask_bit = <0x4>;//0100
16761 + arm,primecell-periphid = <0x00800022>;
16762 + reg = <0x120c2000 0x1000>;
16763 + interrupts = <0 70 4>;
16767 + #size-cells = <0>;
16779 + interrupts = <0 10 4>;
16780 + reg = <0x10300000 0x4000>;
16786 + reg = <0x10011100 0x10>;
16791 + resets = <&clock 0x16c 3>;
16794 + #size-cells = <0>;
16800 + reg = <0x10010000 0x1000>,<0x10011300 0x200>;
16801 + interrupts = <0 32 4>;
16803 + resets = <&clock 0x16c 0>;
16809 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
16812 + max-dma-size = <0x2000>;
16814 + #size-cells = <0>;
16816 + hisfc:spi-nor@0 {
16821 + #size-cells = <0>;
16824 + hisnfc:spi-nand@0 {
16829 + #size-cells = <0>;
16833 + mmc0: himci.eMMC@0x10100000 {
16835 + reg = <0x10100000 0x1000>;
16836 + interrupts = <0 64 4>;
16839 + resets = <&clock 0x148 0>;
16847 + devid = <0>;
16851 + mmc1: himci.SD@0x100f0000 {
16853 + reg = <0x100f0000 0x1000>;
16854 + interrupts = <0 30 4>;
16857 + resets = <&clock 0x160 0>;
16870 + mmc2: himci.SD@0x10020000 {
16872 + reg = <0x10020000 0x1000>;
16873 + interrupts = <0 31 4>;
16876 + resets = <&clock 0x154 0>;
16891 + reg = <0x10060000 0x1000>;
16892 + interrupts = <0 28 4>;
16895 + resets = <&clock 0xc8 4>;
16903 + reg = <0x12010000 0x1000>;
16904 + #phy-cells = <0>;
16908 + xhci_0@0x100e0000 {
16910 + reg = <0x100e0000 0x10000>;
16911 + interrupts = <0 27 4>;
16916 + hidwc3_0@0x100e0000 {
16918 + reg = <0x100e0000 0x10000>;
16919 + interrupts = <0 27 4>;
16927 + reg = <0x120d0000 0x1000>;
16928 + interrupts = <0 16 4>;
16937 + reg = <0x120d1000 0x1000>;
16938 + interrupts = <0 17 4>;
16947 + reg = <0x120d2000 0x1000>;
16948 + interrupts = <0 18 4>;
16957 + reg = <0x120d3000 0x1000>;
16958 + interrupts = <0 19 4>;
16967 + reg = <0x120d4000 0x1000>;
16968 + interrupts = <0 20 4>;
16977 + reg = <0x120d5000 0x1000>;
16978 + interrupts = <0 21 4>;
16987 + reg = <0x120d6000 0x1000>;
16988 + interrupts = <0 22 4>;
16997 + reg = <0x120d7000 0x1000>;
16998 + interrupts = <0 23 4>;
17007 + reg = <0x120d8000 0x1000>;
17008 + interrupts = <0 24 4>;
17017 + reg = <0x120d9000 0x1000>;
17018 + interrupts = <0 25 4>;
17027 + reg = <0x120da000 0x1000>;
17028 + interrupts = <0 26 4>;
17037 + reg = <0x120db000 0x1000>;
17038 + interrupts = <0 80 4>;
17045 + cipher: cipher@0x100c0000 {
17047 + reg = <0x100c0000 0x10000>;
17049 + interrupts = <0 71 4>, <0 72 4>, <0 71 4>, <0 72 4>;
17068 + reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
17069 + <0x12060000 0x10000>, <0x12030000 0x8000>;
17075 + reg = <0x113a0000 0x10000>;
17077 + interrupts = <0 57 4>;
17083 + reg = <0x11270000 0x10000>;
17085 + interrupts = <0 63 4>;
17091 + reg = <0x11300000 0xa0000>, <0x11000000 0x40000>;
17093 + interrupts = <0 56 4>, <0 44 4>;
17099 + reg = <0x11020000 0x20000>;
17101 + interrupts = <0 56 4>;
17107 + reg = <0x11040000 0x10000>;
17109 + interrupts = <0 43 4>;
17115 + reg = <0x11240000 0x10000>;
17117 + interrupts = <0 38 4>;
17123 + reg = <0x11440000 0x40000>;
17125 + interrupts = <0 58 4>;
17131 + reg = <0x11440000 0x40000>, <0x12020000 0x8000>;
17133 + interrupts = <0 59 4>, <0 51 4>;
17139 + reg = <0x11210000 0x10000>;
17141 + interrupts = <0 35 4>;
17147 + reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
17149 + interrupts = <0 42 4>, <0 41 4>;
17155 + reg = <0x11200000 0x10000>;
17157 + interrupts = <0 34 4>;
17163 + reg = <0x11260000 0x10000>;
17165 + interrupts = <0 45 4>;
17171 + reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
17173 + interrupts = <0 40 4>, <0 36 4>;
17179 + reg = <0x10030000 0x10000>;
17181 + interrupts = <0 67 4>;
17187 + reg = <0x11400000 0x30000>;
17193 + reg = <0x113b0000 0x10000>,<0x113c0000 0x10000>,<0x12010000 0x10000>;
17195 + interrupts = <0 55 4>;
17201 + reg = <0x11100000 0x10000>,<0x11110000 0x10000>;
17203 + interrupts = <0 41 4>,<0 42 4>;
17209 + reg = <0x11230000 0x10000>;
17211 + interrupts = <0 37 4>;
17217 + reg = <0x120e0000 0x1000>;
17218 + interrupts = <0 65 4>;
17219 + resets = <&clock 0x1bc 2>;
17225 + reg = <0x120f0000 0x1000>;
17226 + interrupts = <0 75 4>;
17231 + reg = <0x12080000 0x1000>;
17232 + interrupts = <0 5 4>;
17237 + reg = <0x12050000 0x1000>;
17241 + reg = <0x12090000 0x20>;
17251 @@ -0,0 +1,233 @@
17281 + reg = <0x82000000 0x20000000>;/* system memory base */
17340 + spidev@0 {
17342 + reg = <0>;
17343 + pl022,interface = <0>;
17344 + pl022,com-mode = <0>;
17352 + spidev@0 {
17354 + reg = <0>;
17355 + pl022,interface = <0>;
17356 + pl022,com-mode = <0>;
17362 + pl022,interface = <0>;
17363 + pl022,com-mode = <0>;
17371 + spidev@0 {
17373 + reg = <0>;
17374 + pl022,interface = <0>;
17375 + pl022,com-mode = <0>;
17398 + reg = <0>;
17406 + reg = <0>;
17490 @@ -0,0 +1,868 @@
17545 + #size-cells = <0>;
17548 + cpu@0 {
17552 + reg = <0>;
17570 + reg = <0x12010000 0x1000>;
17576 + #address-cells = <0>;
17579 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
17585 + interrupts = <1 13 0xf08>,
17586 + <1 14 0xf08>;
17599 + #clock-cells = <0>;
17605 + #clock-cells = <0>;
17611 + interrupts = <0 54 4>;
17616 + reg = <0x10060000 0x1000>;
17617 + interrupts = <0 28 4>;
17621 + resets = <&clock 0x194 0>;
17625 + devid = <0>;
17633 + reg = <0x10060000 0x1000>;
17634 + interrupts = <0 28 4>;
17638 + resets = <&clock 0x194 0>;
17642 + devid = <0>;
17650 + reg = <0x12020000 0x1000>;
17651 + reboot-offset = <0x4>;
17664 + reg = <0x12000000 0x20>, /* clocksource */
17665 + <0x12000020 0x20>, /* local timer for each cpu */
17666 + <0x12001000 0x20>;
17667 + interrupts = <0 1 4>, /* irq of local timer */
17668 + <0 2 4>;
17678 + interrupts = <0 3 4>;
17679 + reg = <0x12002000 0x1000>;
17687 + reg = <0x120a0000 0x1000>;
17688 + interrupts = <0 6 4>;
17696 + reg = <0x120a1000 0x1000>;
17697 + interrupts = <0 7 4>;
17709 + reg = <0x120a2000 0x1000>;
17710 + interrupts = <0 8 4>;
17722 + reg = <0x120a3000 0x1000>;
17723 + interrupts = <0 9 4>;
17735 + reg = <0x120a4000 0x1000>;
17736 + interrupts = <0 10 4>;
17751 + reg = <0x120b0000 0x1000>;
17754 + dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
17762 + reg = <0x120b1000 0x1000>;
17773 + reg = <0x120b2000 0x1000>;
17785 + reg = <0x120b3000 0x1000>;
17795 + reg = <0x120b4000 0x1000>;
17805 + reg = <0x120b5000 0x1000>;
17816 + reg = <0x120b6000 0x1000>;
17827 + reg = <0x120b7000 0x1000>;
17839 + arm,primecell-periphid = <0x00800022>;
17840 + reg = <0x120c0000 0x1000>;
17841 + interrupts = <0 68 4>;
17845 + #size-cells = <0>;
17855 + arm,primecell-periphid = <0x00800022>;
17856 + reg = <0x120c1000 0x1000>, <0x12030000 0x4>;
17857 + interrupts = <0 69 4>;
17861 + #size-cells = <0>;
17864 + hisi,spi_cs_mask_bit = <0x4>;//0100
17874 + arm,primecell-periphid = <0x00800022>;
17875 + reg = <0x120c2000 0x1000>;
17876 + interrupts = <0 70 4>;
17880 + #size-cells = <0>;
17892 + interrupts = <0 10 4>;
17893 + reg = <0x10300000 0x4000>;
17899 + reg = <0x10011100 0x10>;
17904 + resets = <&clock 0x16c 3>;
17907 + #size-cells = <0>;
17913 + reg = <0x10010000 0x1000>,<0x10011300 0x200>;
17914 + interrupts = <0 32 4>;
17916 + resets = <&clock 0x16c 0>;
17922 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
17925 + max-dma-size = <0x2000>;
17927 + #size-cells = <0>;
17929 + hisfc:spi-nor@0 {
17934 + #size-cells = <0>;
17937 + hisnfc:spi-nand@0 {
17942 + #size-cells = <0>;
17946 + mmc0: himci.eMMC@0x10100000 {
17948 + reg = <0x10100000 0x1000>;
17949 + interrupts = <0 64 4>;
17952 + resets = <&clock 0x148 0>;
17960 + devid = <0>;
17964 + mmc1: himci.SD@0x100f0000 {
17966 + reg = <0x100f0000 0x1000>;
17967 + interrupts = <0 30 4>;
17970 + resets = <&clock 0x160 0>;
17983 + mmc2: himci.SD@0x10020000 {
17985 + reg = <0x10020000 0x1000>;
17986 + interrupts = <0 31 4>;
17989 + resets = <&clock 0x154 0>;
18004 + reg = <0x10060000 0x1000>;
18005 + interrupts = <0 28 4>;
18008 + resets = <&clock 0xc8 4>;
18016 + reg = <0x12010000 0x1000>;
18017 + #phy-cells = <0>;
18021 + xhci_0@0x100e0000 {
18023 + reg = <0x100e0000 0x10000>;
18024 + interrupts = <0 27 4>;
18029 + hidwc3_0@0x100e0000 {
18031 + reg = <0x100e0000 0x10000>;
18032 + interrupts = <0 27 4>;
18040 + reg = <0x120d0000 0x1000>;
18041 + interrupts = <0 16 4>;
18050 + reg = <0x120d1000 0x1000>;
18051 + interrupts = <0 17 4>;
18060 + reg = <0x120d2000 0x1000>;
18061 + interrupts = <0 18 4>;
18070 + reg = <0x120d3000 0x1000>;
18071 + interrupts = <0 19 4>;
18080 + reg = <0x120d4000 0x1000>;
18081 + interrupts = <0 20 4>;
18090 + reg = <0x120d5000 0x1000>;
18091 + interrupts = <0 21 4>;
18100 + reg = <0x120d6000 0x1000>;
18101 + interrupts = <0 22 4>;
18110 + reg = <0x120d7000 0x1000>;
18111 + interrupts = <0 23 4>;
18120 + reg = <0x120d8000 0x1000>;
18121 + interrupts = <0 24 4>;
18130 + reg = <0x120d9000 0x1000>;
18131 + interrupts = <0 25 4>;
18140 + reg = <0x120da000 0x1000>;
18141 + interrupts = <0 26 4>;
18150 + reg = <0x120db000 0x1000>;
18151 + interrupts = <0 80 4>;
18158 + cipher: cipher@0x100c0000 {
18160 + reg = <0x100c0000 0x10000>;
18162 + interrupts = <0 71 4>, <0 72 4>, <0 71 4>, <0 72 4>;
18181 + reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
18182 + <0x12060000 0x10000>, <0x12030000 0x8000>;
18188 + reg = <0x113a0000 0x10000>;
18190 + interrupts = <0 57 4>;
18196 + reg = <0x11270000 0x10000>;
18198 + interrupts = <0 63 4>;
18204 + reg = <0x11300000 0xa0000>, <0x11000000 0x40000>;
18206 + interrupts = <0 56 4>, <0 44 4>;
18212 + reg = <0x11020000 0x20000>;
18214 + interrupts = <0 56 4>;
18220 + reg = <0x11040000 0x10000>;
18222 + interrupts = <0 43 4>;
18228 + reg = <0x11240000 0x10000>;
18230 + interrupts = <0 38 4>;
18236 + reg = <0x11440000 0x40000>;
18238 + interrupts = <0 58 4>;
18244 + reg = <0x11440000 0x40000>, <0x12020000 0x8000>;
18246 + interrupts = <0 59 4>, <0 51 4>;
18252 + reg = <0x11210000 0x10000>;
18254 + interrupts = <0 35 4>;
18260 + reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
18262 + interrupts = <0 42 4>, <0 41 4>;
18268 + reg = <0x11200000 0x10000>;
18270 + interrupts = <0 34 4>;
18276 + reg = <0x11260000 0x10000>;
18278 + interrupts = <0 45 4>;
18284 + reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
18286 + interrupts = <0 40 4>, <0 36 4>;
18292 + reg = <0x10030000 0x10000>;
18294 + interrupts = <0 67 4>;
18300 + reg = <0x11400000 0x30000>;
18306 + reg = <0x113b0000 0x10000>,<0x113c0000 0x10000>,<0x12010000 0x10000>;
18308 + interrupts = <0 55 4>;
18314 + reg = <0x11100000 0x10000>,<0x11110000 0x10000>;
18316 + interrupts = <0 41 4>,<0 42 4>;
18322 + reg = <0x11230000 0x10000>;
18324 + interrupts = <0 37 4>;
18330 + reg = <0x120e0000 0x1000>;
18331 + interrupts = <0 65 4>;
18332 + resets = <&clock 0x1bc 2>;
18338 + reg = <0x120f0000 0x1000>;
18339 + interrupts = <0 75 4>;
18344 + reg = <0x12080000 0x1000>;
18345 + interrupts = <0 5 4>;
18350 + reg = <0x12050000 0x1000>;
18354 + reg = <0x12090000 0x20>;
18364 @@ -0,0 +1,25 @@
18395 @@ -0,0 +1,25 @@
18426 @@ -0,0 +1,284 @@
18454 + linux,initrd-start = <0x23000040>;
18455 + linux,initrd-end = <0x24000000>;
18460 + #size-cells = <0>;
18462 + cpu@0 {
18465 + reg = <0>;
18472 + reg = <0x32000000 0x10000000>;
18527 + spidev@0 {
18529 + reg = <0>;
18530 + pl022,interface = <0>;
18531 + pl022,com-mode = <0>;
18539 + spidev@0 {
18541 + reg = <0>;
18542 + pl022,interface = <0>;
18543 + pl022,com-mode = <0>;
18551 + spidev@0 {
18553 + reg = <0>;
18554 + pl022,interface = <0>;
18555 + pl022,com-mode = <0>;
18563 + spidev@0 {
18565 + reg = <0>;
18566 + pl022,interface = <0>;
18567 + pl022,com-mode = <0>;
18575 + spidev@0 {
18577 + reg = <0>;
18578 + pl022,interface = <0>;
18579 + pl022,com-mode = <0>;
18598 + reg = <0>;
18607 + reg = <0>;
18615 + reg = <0>;
18716 @@ -0,0 +1,1081 @@
18780 + #address-cells = <0>;
18783 + reg = <0x04C01000 0x1000>, <0x04C02000 0x1000>;
18792 + reg = <0x04510000 0x10000>;
18798 + #clock-cells = <0>;
18805 + interrupts = <1 13 0xf08>,
18806 + <1 14 0xf08>;
18813 + interrupts = <0 74 4>;
18814 + reg = <0x045E0000 0x1000>;
18833 + reg = <0x04540000 0x1000>;
18834 + interrupts = <0 36 4>;
18842 + reg = <0x04541000 0x1000>;
18843 + interrupts = <0 37 4>;
18853 + reg = <0x04542000 0x1000>;
18854 + interrupts = <0 38 4>;
18864 + reg = <0x04543000 0x1000>;
18865 + interrupts = <0 39 4>;
18875 + reg = <0x04544000 0x1000>;
18876 + interrupts = <0 40 4>;
18886 + reg = <0x04560000 0x1000>;
18890 + dmas = <&hiedmacv310_1 0 14>, <&hiedmacv310_1 1 15>;
18896 + reg = <0x04561000 0x1000>;
18906 + reg = <0x04562000 0x1000>;
18916 + reg = <0x04563000 0x1000>;
18926 + reg = <0x04564000 0x1000>;
18936 + reg = <0x04565000 0x1000>;
18946 + reg = <0x04566000 0x1000>;
18956 + reg = <0x04567000 0x1000>;
18966 + reg = <0x04568000 0x1000>;
18976 + reg = <0x04569000 0x1000>;
18986 + arm,primecell-periphid = <0x00800022>;
18987 + reg = <0x04570000 0x1000>;
18988 + interrupts = <0 155 4>;
18992 + #size-cells = <0>;
19001 + arm,primecell-periphid = <0x00800022>;
19002 + reg = <0x04571000 0x1000>;
19003 + interrupts = <0 156 4>;
19007 + #size-cells = <0>;
19016 + arm,primecell-periphid = <0x00800022>;
19017 + reg = <0x04572000 0x1000>;
19018 + interrupts = <0 157 4>;
19022 + #size-cells = <0>;
19031 + arm,primecell-periphid = <0x00800022>;
19032 + reg = <0x04573000 0x1000>;
19033 + interrupts = <0 158 4>;
19037 + #size-cells = <0>;
19046 + arm,primecell-periphid = <0x00800022>;
19047 + reg = <0x04574000 0x1000>;
19048 + interrupts = <0 159 4>;
19052 + #size-cells = <0>;
19061 + reg = <0x045f0000 0x1000>;
19062 + interrupts = <0 56 4>;
19071 + reg = <0x045f1000 0x1000>;
19072 + interrupts = <0 57 4>;
19081 + reg = <0x045f2000 0x1000>;
19082 + interrupts = <0 58 4>;
19091 + reg = <0x045f3000 0x1000>;
19092 + interrupts = <0 59 4>;
19101 + reg = <0x045f4000 0x1000>;
19102 + interrupts = <0 60 4>;
19111 + reg = <0x045f5000 0x1000>;
19112 + interrupts = <0 61 4>;
19121 + reg = <0x045f6000 0x1000>;
19122 + interrupts = <0 62 4>;
19131 + reg = <0x045f7000 0x1000>;
19132 + interrupts = <0 63 4>;
19141 + reg = <0x045f8000 0x1000>;
19142 + interrupts = <0 64 4>;
19151 + reg = <0x045f9000 0x1000>;
19152 + interrupts = <0 65 4>;
19161 + reg = <0x045fa000 0x1000>;
19162 + interrupts = <0 66 4>;
19171 + reg = <0x045fb000 0x1000>;
19172 + interrupts = <0 67 4>;
19181 + reg = <0x045fc000 0x1000>;
19182 + interrupts = <0 68 4>;
19191 + reg = <0x045fd000 0x1000>;
19192 + interrupts = <0 69 4>;
19201 + reg = <0x045fe000 0x1000>;
19202 + interrupts = <0 70 4>;
19210 + interrupts = <0 30 4>;
19211 + reg = <0x04500000 0x1000>;
19218 + reg = <0x04500000 0x20>, /* clocksource */
19219 + <0x04500020 0x20>, /* local timer for each cpu */
19220 + <0x04501000 0x20>;
19221 + interrupts = <0 30 4>, /* irq of local timer */
19222 + <0 31 4>;
19233 + reg = <0x04c10000 0x1000>;
19234 + interrupts = <0 2 4>;
19237 + resets = <&clock 0x14c 4>;
19246 + reg = <0x04040000 0x1000>;
19247 + interrupts = <0 98 4>;
19250 + resets = <&clock 0x16c 4>;
19258 + reg = <0x04040000 0x1000>;
19260 + misc_ctrl_base = <0x124>;
19261 + interrupts = <0 98 4>;
19265 + resets = <&clock 0x16c 4>;
19269 + devid = <0>;
19276 + reg = <0x04050000 0x1000>;
19278 + misc_ctrl_base = <0x144>;
19279 + interrupts = <0 99 4>;
19283 + resets = <&clock 0x16c 7>;
19294 + reg = <0x04520000 0x1000>;
19301 + offset = <0x4>;
19302 + mask = <0xdeadbeef>;
19308 + reg = <0x04528000 0x10000>;
19313 + reg = <0x04058000 0x100>;
19318 + reg = <0x047B8000 0x100>;
19323 + reg = <0x047E0000 0x100>;
19328 + reg = <0x047E8000 0x100>;
19333 + reg = <0x04510000 0x1000>, <0x04528000 0x1000>, <0x04520000 0x1000>;
19334 + #phy-cells = <0>;
19338 + xhci_0@0x04110000 {
19340 + reg = <0x04110000 0x10000>;
19341 + interrupts = <0 111 4>;
19347 + xhci_1@0x04120000 {
19349 + reg = <0x04120000 0x10000>;
19350 + interrupts = <0 112 4>;
19356 + hidwc3_0@0x04110000 {
19358 + reg = <0x04110000 0x10000>, <0x04510000 0x1000>, <0x04520000 0x1000>;
19359 + interrupts = <0 111 4>;
19369 + hidwc3_1@0x04120000 {
19371 + reg = <0x04120000 0x10000>, <0x04510000 0x1000>, <0x04520000 0x1000>;
19372 + interrupts = <0 112 4>;
19382 + reg = <0x04d00000 0x1000>;
19383 + ranges = <0x0 0x04d00000 0x6000>;
19388 + reg = <0x2000 0x1000>;
19394 + reg = <0x3000 0x1000>;
19401 + reg = <0x040e03c0 0x20>;
19403 + resets = <&clock 0x174 14>;
19406 + #size-cells = <0>;
19411 + reg = <0x040e0000 0x1000>,<0x040e300c 0x4>;
19412 + interrupts = <0 89 4>;
19419 + resets = <&clock 0x174 0>,
19420 + <&clock 0x174 4>;
19429 + reg = <0x04020000 0x1000>, <0x0f000000 0x1000000>;
19432 + max-dma-size = <0x2000>;
19434 + #size-cells = <0>;
19441 + #size-cells = <0>;
19449 + #size-cells = <0>;
19457 + #size-cells = <0>;
19461 + mmc0: eMMC@0x04030000 {
19463 + reg = <0x04030000 0x1000>, <0x04048000 0x1000>;
19464 + interrupts = <0 92 4>;
19467 + resets = <&clock 0x1a8 27>, <&clock 0x1a8 29>, <&clock 0x1a8 30>;
19477 + devid = <0>;
19481 + mmc1: SD@0x040c0000 {
19483 + reg = <0x040c0000 0x1000>;
19484 + interrupts = <0 87 4>;
19487 + resets = <&clock 0x1ec 27>, <&clock 0x1ec 29>, <&clock 0x1ec 30>;
19502 + mmc2: SD@0x040d0000 {
19504 + reg = <0x040d0000 0x1000>;
19505 + interrupts = <0 88 4>;
19508 + resets = <&clock 0x214 27>, <&clock 0x214 29>, <&clock 0x214 30>;
19523 + pcie0: pcie@0x0eff0000 {
19529 + bus-range = <0x0 0xff>;
19530 + ranges = <0x02000000 0x00 0x18000000 0x18000000 0x00 0xff00000>;
19531 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
19532 + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 102 0x4
19533 + 0x0 0x0 0x0 0x2 &gic 0x0 103 0x4
19534 + 0x0 0x0 0x0 0x3 &gic 0x0 104 0x4
19535 + 0x0 0x0 0x0 0x4 &gic 0x0 105 0x4>;
19536 + pcie_controller = <0>;
19537 + dev_mem_size = <0x8000000>;
19538 + dev_conf_size = <0x8000000>;
19539 + pcie_dbi_base = <0x0eff0000>;
19540 + ep_conf_base = <0x10000000>;
19543 + pcie_mcc: pcie_mcc@0x0 {
19545 + interrupts = <0 102 4>,<0 103 4>,< 0 104 4>
19546 + ,< 0 105 4>,< 0 106 4>,< 0 73 4>;
19549 + cipher: cipher@0x04060000 {
19551 + reg = <0x04060000 0x10000>, <0x04080000 0x10000>;
19553 + interrupts = <0 93 4>, <0 94 4>, <0 93 4>, <0 94 4>, <0 95 4>, <0 85 4>;
19559 + reg = <0x045c0000 0x1000>;
19560 + interrupts = <0 55 4>;
19565 + reg = <0x04550000 0x1000>;
19566 + interrupts = <0 28 4>;
19571 + reg = <0x04530000 0x1000>;
19590 + reg = <0x04510000 0x10000>, <0x04520000 0x8000>,
19591 + <0x04600000 0x10000>, <0x04528000 0x8000>;
19597 + reg = <0x04a40000 0x10000>, <0x04a80000 0x10000>;
19599 + interrupts = <0 128 4>, <0 129 4>;
19605 + reg = <0x04780000 0x10000>;
19607 + interrupts = <0 120 4>;
19613 + reg = <0x04800000 0x200000>, <0x04a00000 0x40000>;
19615 + interrupts = <0 127 4>, <0 125 4>;
19621 + reg = <0x04a20000 0x20000>;
19623 + interrupts = <0 127 4>;
19629 + reg = <0x04b20000 0x10000>;
19631 + interrupts = <0 126 4>;
19637 + reg = <0x04a90000 0x10000>;
19639 + interrupts = <0 130 4>;
19645 + reg = <0x04700000 0x20000>;
19647 + interrupts = <0 117 4>;
19653 + reg = <0x04700000 0x20000>;
19655 + interrupts = <0 118 4>;
19661 + reg = <0x04ad0000 0x10000>;
19663 + interrupts = <0 149 4>;
19669 + reg = <0x04b00000 0x10000>;
19671 + interrupts = <0 139 4>;
19677 + reg = <0x04aa0000 0x10000>;
19679 + interrupts = <0 134 4>;
19689 + reg = <0x04ab0000 0x10000>;
19691 + interrupts = <0 133 4>;
19697 + reg = <0x04790000 0x10000>;
19699 + interrupts = <0 138 4>;
19705 + reg = <0x04ac0000 0x10000>;
19707 + interrupts = <0 131 4>;
19713 + reg = <0x047c0000 0x8000>, <0x047c8000 0x8000>;
19715 + interrupts = <0 115 4>, <0 132 4>;
19725 + reg = <0x047d0000 0x10000>;
19727 + interrupts = <0 114 4>, <0 113 4>;
19733 + reg = <0x04740000 0x30000>;
19739 + reg = <0x047a0000 0x10000>,<0x047b0000 0x10000>,<0x04510000 0x10000>;
19741 + interrupts = <0 119 4>,<0 151 4>;
19745 + nnie: nnie@0x04C30000 {
19747 + reg = <0x04C30000 0x10000>;
19749 + interrupts = <0 1 4>;
19753 + dpu_rect: dpu_rect@0x04AE0000 {
19755 + reg = <0x04AE0000 0x10000>;
19757 + interrupts = <0 135 4>;
19761 + dpu_match: dpu_match@0x04AE0000 {
19763 + reg = <0x04AE0000 0x10000>;
19765 + interrupts = <0 136 4>;
19769 + dsp: dsp@0x04C20000 {
19771 + reg = <0x04C20000 0x10000>;
19775 + ive: ive@0x04B10000 {
19777 + reg = <0x04B10000 0x10000>;
19779 + interrupts = <0 147 4>;
19785 + reg = <0x045d0000 0x1000>;
19786 + interrupts = <0 83 4>;
19787 + resets = <&clock 0x194 16>;
19794 + reg = <0x045A0000 0x10000>;
19803 @@ -0,0 +1,2737 @@
19822 +CONFIG_VECTORS_BASE=0xffff0000
20040 +CONFIG_BASE_SMALL=0
20154 +CONFIG_HI_ZRELADDR=0x80008000
20155 +CONFIG_HI_PARAMS_PHYS=0x00000100
20156 +CONFIG_HI_INITRD_PHYS=0x00800000
20258 +CONFIG_PAGE_OFFSET=0xC0000000
20260 +CONFIG_ARCH_NR_GPIO=0
20264 +CONFIG_HZ_FIXED=0
20320 +CONFIG_ZBOOT_ROM_TEXT=0
20321 +CONFIG_ZBOOT_ROM_BSS=0
20561 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
20712 +CONFIG_HISFC350_SYSCTRL_ADDRESS=0x20030000
20924 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
20925 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
22071 +CONFIG_JFFS2_FS_DEBUG=0
22230 +CONFIG_PANIC_ON_OOPS_VALUE=0
22231 +CONFIG_PANIC_TIMEOUT=0
22546 @@ -0,0 +1,2335 @@
22565 +CONFIG_VECTORS_BASE=0xffff0000
22783 +CONFIG_BASE_SMALL=0
22897 +CONFIG_HI_ZRELADDR=0x80008000
22898 +CONFIG_HI_PARAMS_PHYS=0x00000100
22899 +CONFIG_HI_INITRD_PHYS=0x00800000
23001 +CONFIG_PAGE_OFFSET=0xC0000000
23003 +CONFIG_ARCH_NR_GPIO=0
23007 +CONFIG_HZ_FIXED=0
23063 +CONFIG_ZBOOT_ROM_TEXT=0
23064 +CONFIG_ZBOOT_ROM_BSS=0
23433 +CONFIG_HISFC350_SYSCTRL_ADDRESS=0x20030000
23604 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
23605 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
24417 +CONFIG_JFFS2_FS_DEBUG=0
24571 +CONFIG_PANIC_ON_OOPS_VALUE=0
24572 +CONFIG_PANIC_TIMEOUT=0
24887 @@ -0,0 +1,2733 @@
24906 +CONFIG_VECTORS_BASE=0xffff0000
25124 +CONFIG_BASE_SMALL=0
25238 +CONFIG_HI_ZRELADDR=0x80008000
25239 +CONFIG_HI_PARAMS_PHYS=0x00000100
25240 +CONFIG_HI_INITRD_PHYS=0x00800000
25342 +CONFIG_PAGE_OFFSET=0xC0000000
25344 +CONFIG_ARCH_NR_GPIO=0
25348 +CONFIG_HZ_FIXED=0
25404 +CONFIG_ZBOOT_ROM_TEXT=0
25405 +CONFIG_ZBOOT_ROM_BSS=0
25645 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
25792 +CONFIG_HISFC350_SYSCTRL_ADDRESS=0x20030000
26004 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
26005 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
27151 +CONFIG_JFFS2_FS_DEBUG=0
27310 +CONFIG_PANIC_ON_OOPS_VALUE=0
27311 +CONFIG_PANIC_TIMEOUT=0
27626 @@ -0,0 +1,2331 @@
27645 +CONFIG_VECTORS_BASE=0xffff0000
27863 +CONFIG_BASE_SMALL=0
27977 +CONFIG_HI_ZRELADDR=0x80008000
27978 +CONFIG_HI_PARAMS_PHYS=0x00000100
27979 +CONFIG_HI_INITRD_PHYS=0x00800000
28081 +CONFIG_PAGE_OFFSET=0xC0000000
28083 +CONFIG_ARCH_NR_GPIO=0
28087 +CONFIG_HZ_FIXED=0
28143 +CONFIG_ZBOOT_ROM_TEXT=0
28144 +CONFIG_ZBOOT_ROM_BSS=0
28509 +CONFIG_HISFC350_SYSCTRL_ADDRESS=0x20030000
28680 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
28681 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
29493 +CONFIG_JFFS2_FS_DEBUG=0
29647 +CONFIG_PANIC_ON_OOPS_VALUE=0
29648 +CONFIG_PANIC_TIMEOUT=0
29963 @@ -0,0 +1,3070 @@
29970 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
29974 +CONFIG_CLANG_VERSION=0
30229 +CONFIG_HI_ZRELADDR=0x80008000
30230 +CONFIG_HI_PARAMS_PHYS=0x00000100
30231 +CONFIG_HI_INITRD_PHYS=0x00800000
30348 +CONFIG_PAGE_OFFSET=0xC0000000
30352 +CONFIG_ARCH_NR_GPIO=0
30353 +CONFIG_HZ_FIXED=0
30385 +CONFIG_ZBOOT_ROM_TEXT=0
30386 +CONFIG_ZBOOT_ROM_BSS=0
30516 +CONFIG_BASE_SMALL=0
30747 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
32930 +CONFIG_PANIC_ON_OOPS_VALUE=0
32931 +CONFIG_PANIC_TIMEOUT=0
33039 @@ -0,0 +1,3189 @@
33046 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
33050 +CONFIG_CLANG_VERSION=0
33305 +CONFIG_HI_ZRELADDR=0x80008000
33306 +CONFIG_HI_PARAMS_PHYS=0x00000100
33307 +CONFIG_HI_INITRD_PHYS=0x00800000
33424 +CONFIG_PAGE_OFFSET=0xC0000000
33428 +CONFIG_ARCH_NR_GPIO=0
33429 +CONFIG_HZ_FIXED=0
33461 +CONFIG_ZBOOT_ROM_TEXT=0
33462 +CONFIG_ZBOOT_ROM_BSS=0
33592 +CONFIG_BASE_SMALL=0
33823 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
35730 +CONFIG_JFFS2_FS_DEBUG=0
36125 +CONFIG_PANIC_ON_OOPS_VALUE=0
36126 +CONFIG_PANIC_TIMEOUT=0
36234 @@ -0,0 +1,2641 @@
36253 +CONFIG_VECTORS_BASE=0xffff0000
36471 +CONFIG_BASE_SMALL=0
36578 +CONFIG_HI_ZRELADDR=0x80008000
36579 +CONFIG_HI_PARAMS_PHYS=0x00000100
36580 +CONFIG_HI_INITRD_PHYS=0x00800000
36642 +CONFIG_PAGE_OFFSET=0xC0000000
36643 +CONFIG_ARCH_NR_GPIO=0
36647 +CONFIG_HZ_FIXED=0
36700 +CONFIG_ZBOOT_ROM_TEXT=0
36701 +CONFIG_ZBOOT_ROM_BSS=0
38418 +CONFIG_JFFS2_FS_DEBUG=0
38574 +CONFIG_PANIC_TIMEOUT=0
38881 @@ -0,0 +1,3070 @@
38888 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
38892 +CONFIG_CLANG_VERSION=0
39147 +CONFIG_HI_ZRELADDR=0x80008000
39148 +CONFIG_HI_PARAMS_PHYS=0x00000100
39149 +CONFIG_HI_INITRD_PHYS=0x00800000
39266 +CONFIG_PAGE_OFFSET=0xC0000000
39270 +CONFIG_ARCH_NR_GPIO=0
39271 +CONFIG_HZ_FIXED=0
39303 +CONFIG_ZBOOT_ROM_TEXT=0
39304 +CONFIG_ZBOOT_ROM_BSS=0
39434 +CONFIG_BASE_SMALL=0
39665 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
41848 +CONFIG_PANIC_ON_OOPS_VALUE=0
41849 +CONFIG_PANIC_TIMEOUT=0
41957 @@ -0,0 +1,3189 @@
41964 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
41968 +CONFIG_CLANG_VERSION=0
42223 +CONFIG_HI_ZRELADDR=0x80008000
42224 +CONFIG_HI_PARAMS_PHYS=0x00000100
42225 +CONFIG_HI_INITRD_PHYS=0x00800000
42342 +CONFIG_PAGE_OFFSET=0xC0000000
42346 +CONFIG_ARCH_NR_GPIO=0
42347 +CONFIG_HZ_FIXED=0
42379 +CONFIG_ZBOOT_ROM_TEXT=0
42380 +CONFIG_ZBOOT_ROM_BSS=0
42510 +CONFIG_BASE_SMALL=0
42741 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
44648 +CONFIG_JFFS2_FS_DEBUG=0
45043 +CONFIG_PANIC_ON_OOPS_VALUE=0
45044 +CONFIG_PANIC_TIMEOUT=0
45152 @@ -0,0 +1,3006 @@
45159 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
45163 +CONFIG_CLANG_VERSION=0
45396 +CONFIG_HI_ZRELADDR=0x40008000
45397 +CONFIG_HI_PARAMS_PHYS=0x00000100
45398 +CONFIG_HI_INITRD_PHYS=0x00800000
45506 +CONFIG_PAGE_OFFSET=0xC0000000
45508 +CONFIG_ARCH_NR_GPIO=0
45509 +CONFIG_HZ_FIXED=0
45540 +CONFIG_ZBOOT_ROM_TEXT=0
45541 +CONFIG_ZBOOT_ROM_BSS=0
45667 +CONFIG_BASE_SMALL=0
45857 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
46220 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
46221 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
47703 +CONFIG_JFFS2_FS_DEBUG=0
48086 +CONFIG_PANIC_ON_OOPS_VALUE=0
48087 +CONFIG_PANIC_TIMEOUT=0
48164 @@ -0,0 +1,3006 @@
48171 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
48175 +CONFIG_CLANG_VERSION=0
48408 +CONFIG_HI_ZRELADDR=0x40008000
48409 +CONFIG_HI_PARAMS_PHYS=0x00000100
48410 +CONFIG_HI_INITRD_PHYS=0x00800000
48518 +CONFIG_PAGE_OFFSET=0xC0000000
48520 +CONFIG_ARCH_NR_GPIO=0
48521 +CONFIG_HZ_FIXED=0
48552 +CONFIG_ZBOOT_ROM_TEXT=0
48553 +CONFIG_ZBOOT_ROM_BSS=0
48679 +CONFIG_BASE_SMALL=0
48869 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
49232 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
49233 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
50715 +CONFIG_JFFS2_FS_DEBUG=0
51098 +CONFIG_PANIC_ON_OOPS_VALUE=0
51099 +CONFIG_PANIC_TIMEOUT=0
51176 @@ -0,0 +1,3070 @@
51183 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
51187 +CONFIG_CLANG_VERSION=0
51442 +CONFIG_HI_ZRELADDR=0x80008000
51443 +CONFIG_HI_PARAMS_PHYS=0x00000100
51444 +CONFIG_HI_INITRD_PHYS=0x00800000
51561 +CONFIG_PAGE_OFFSET=0xC0000000
51565 +CONFIG_ARCH_NR_GPIO=0
51566 +CONFIG_HZ_FIXED=0
51598 +CONFIG_ZBOOT_ROM_TEXT=0
51599 +CONFIG_ZBOOT_ROM_BSS=0
51729 +CONFIG_BASE_SMALL=0
51960 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
54143 +CONFIG_PANIC_ON_OOPS_VALUE=0
54144 +CONFIG_PANIC_TIMEOUT=0
54252 @@ -0,0 +1,3135 @@
54259 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
54263 +CONFIG_CLANG_VERSION=0
54545 +CONFIG_HI_ZRELADDR=0x80008000
54546 +CONFIG_HI_PARAMS_PHYS=0x00000100
54547 +CONFIG_HI_INITRD_PHYS=0x00800000
54664 +CONFIG_PAGE_OFFSET=0xC0000000
54668 +CONFIG_ARCH_NR_GPIO=0
54669 +CONFIG_HZ_FIXED=0
54701 +CONFIG_ZBOOT_ROM_TEXT=0
54702 +CONFIG_ZBOOT_ROM_BSS=0
54833 +CONFIG_BASE_SMALL=0
55066 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
57306 +CONFIG_PANIC_ON_OOPS_VALUE=0
57307 +CONFIG_PANIC_TIMEOUT=0
57393 @@ -0,0 +1,3189 @@
57400 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
57404 +CONFIG_CLANG_VERSION=0
57659 +CONFIG_HI_ZRELADDR=0x80008000
57660 +CONFIG_HI_PARAMS_PHYS=0x00000100
57661 +CONFIG_HI_INITRD_PHYS=0x00800000
57778 +CONFIG_PAGE_OFFSET=0xC0000000
57782 +CONFIG_ARCH_NR_GPIO=0
57783 +CONFIG_HZ_FIXED=0
57815 +CONFIG_ZBOOT_ROM_TEXT=0
57816 +CONFIG_ZBOOT_ROM_BSS=0
57946 +CONFIG_BASE_SMALL=0
58177 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
60084 +CONFIG_JFFS2_FS_DEBUG=0
60479 +CONFIG_PANIC_ON_OOPS_VALUE=0
60480 +CONFIG_PANIC_TIMEOUT=0
60588 @@ -0,0 +1,3006 @@
60595 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
60599 +CONFIG_CLANG_VERSION=0
60832 +CONFIG_HI_ZRELADDR=0x40008000
60833 +CONFIG_HI_PARAMS_PHYS=0x00000100
60834 +CONFIG_HI_INITRD_PHYS=0x00800000
60942 +CONFIG_PAGE_OFFSET=0xC0000000
60944 +CONFIG_ARCH_NR_GPIO=0
60945 +CONFIG_HZ_FIXED=0
60976 +CONFIG_ZBOOT_ROM_TEXT=0
60977 +CONFIG_ZBOOT_ROM_BSS=0
61103 +CONFIG_BASE_SMALL=0
61293 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
61656 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
61657 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
63139 +CONFIG_JFFS2_FS_DEBUG=0
63522 +CONFIG_PANIC_ON_OOPS_VALUE=0
63523 +CONFIG_PANIC_TIMEOUT=0
63600 @@ -0,0 +1,3006 @@
63607 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
63611 +CONFIG_CLANG_VERSION=0
63844 +CONFIG_HI_ZRELADDR=0x40008000
63845 +CONFIG_HI_PARAMS_PHYS=0x00000100
63846 +CONFIG_HI_INITRD_PHYS=0x00800000
63954 +CONFIG_PAGE_OFFSET=0xC0000000
63956 +CONFIG_ARCH_NR_GPIO=0
63957 +CONFIG_HZ_FIXED=0
63988 +CONFIG_ZBOOT_ROM_TEXT=0
63989 +CONFIG_ZBOOT_ROM_BSS=0
64115 +CONFIG_BASE_SMALL=0
64305 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
64668 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
64669 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
66151 +CONFIG_JFFS2_FS_DEBUG=0
66534 +CONFIG_PANIC_ON_OOPS_VALUE=0
66535 +CONFIG_PANIC_TIMEOUT=0
66612 @@ -0,0 +1,2067 @@
66619 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
66623 +CONFIG_CLANG_VERSION=0
66855 +CONFIG_HI_ZRELADDR=0x40008000
66856 +CONFIG_HI_PARAMS_PHYS=0x00000100
66857 +CONFIG_HI_INITRD_PHYS=0x00800000
66965 +CONFIG_PAGE_OFFSET=0xC0000000
66967 +CONFIG_ARCH_NR_GPIO=0
66968 +CONFIG_HZ_FIXED=0
66999 +CONFIG_ZBOOT_ROM_TEXT=0
67000 +CONFIG_ZBOOT_ROM_BSS=0
67126 +CONFIG_BASE_SMALL=0
68280 +CONFIG_JFFS2_FS_DEBUG=0
68607 +CONFIG_PANIC_ON_OOPS_VALUE=0
68608 +CONFIG_PANIC_TIMEOUT=0
68685 @@ -0,0 +1,3006 @@
68692 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
68696 +CONFIG_CLANG_VERSION=0
68929 +CONFIG_HI_ZRELADDR=0x40008000
68930 +CONFIG_HI_PARAMS_PHYS=0x00000100
68931 +CONFIG_HI_INITRD_PHYS=0x00800000
69039 +CONFIG_PAGE_OFFSET=0xC0000000
69041 +CONFIG_ARCH_NR_GPIO=0
69042 +CONFIG_HZ_FIXED=0
69073 +CONFIG_ZBOOT_ROM_TEXT=0
69074 +CONFIG_ZBOOT_ROM_BSS=0
69200 +CONFIG_BASE_SMALL=0
69390 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
69753 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
69754 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
71236 +CONFIG_JFFS2_FS_DEBUG=0
71619 +CONFIG_PANIC_ON_OOPS_VALUE=0
71620 +CONFIG_PANIC_TIMEOUT=0
71697 @@ -0,0 +1,3006 @@
71704 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
71708 +CONFIG_CLANG_VERSION=0
71941 +CONFIG_HI_ZRELADDR=0x40008000
71942 +CONFIG_HI_PARAMS_PHYS=0x00000100
71943 +CONFIG_HI_INITRD_PHYS=0x00800000
72051 +CONFIG_PAGE_OFFSET=0xC0000000
72053 +CONFIG_ARCH_NR_GPIO=0
72054 +CONFIG_HZ_FIXED=0
72085 +CONFIG_ZBOOT_ROM_TEXT=0
72086 +CONFIG_ZBOOT_ROM_BSS=0
72212 +CONFIG_BASE_SMALL=0
72402 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
72765 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
72766 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
74248 +CONFIG_JFFS2_FS_DEBUG=0
74631 +CONFIG_PANIC_ON_OOPS_VALUE=0
74632 +CONFIG_PANIC_TIMEOUT=0
74709 @@ -0,0 +1,2641 @@
74728 +CONFIG_VECTORS_BASE=0xffff0000
74946 +CONFIG_BASE_SMALL=0
75053 +CONFIG_HI_ZRELADDR=0x80008000
75054 +CONFIG_HI_PARAMS_PHYS=0x00000100
75055 +CONFIG_HI_INITRD_PHYS=0x00800000
75117 +CONFIG_PAGE_OFFSET=0xC0000000
75118 +CONFIG_ARCH_NR_GPIO=0
75122 +CONFIG_HZ_FIXED=0
75175 +CONFIG_ZBOOT_ROM_TEXT=0
75176 +CONFIG_ZBOOT_ROM_BSS=0
76893 +CONFIG_JFFS2_FS_DEBUG=0
77049 +CONFIG_PANIC_TIMEOUT=0
77356 @@ -0,0 +1,2318 @@
77375 +CONFIG_VECTORS_BASE=0xffff0000
77593 +CONFIG_BASE_SMALL=0
77700 +CONFIG_HI_ZRELADDR=0x80008000
77701 +CONFIG_HI_PARAMS_PHYS=0x00000100
77702 +CONFIG_HI_INITRD_PHYS=0x00800000
77764 +CONFIG_PAGE_OFFSET=0xC0000000
77765 +CONFIG_ARCH_NR_GPIO=0
77769 +CONFIG_HZ_FIXED=0
77822 +CONFIG_ZBOOT_ROM_TEXT=0
77823 +CONFIG_ZBOOT_ROM_BSS=0
79227 +CONFIG_JFFS2_FS_DEBUG=0
79378 +CONFIG_PANIC_TIMEOUT=0
79680 @@ -0,0 +1,3006 @@
79687 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
79691 +CONFIG_CLANG_VERSION=0
79924 +CONFIG_HI_ZRELADDR=0x40008000
79925 +CONFIG_HI_PARAMS_PHYS=0x00000100
79926 +CONFIG_HI_INITRD_PHYS=0x00800000
80034 +CONFIG_PAGE_OFFSET=0xC0000000
80036 +CONFIG_ARCH_NR_GPIO=0
80037 +CONFIG_HZ_FIXED=0
80068 +CONFIG_ZBOOT_ROM_TEXT=0
80069 +CONFIG_ZBOOT_ROM_BSS=0
80195 +CONFIG_BASE_SMALL=0
80385 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
80748 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
80749 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
82231 +CONFIG_JFFS2_FS_DEBUG=0
82614 +CONFIG_PANIC_ON_OOPS_VALUE=0
82615 +CONFIG_PANIC_TIMEOUT=0
82692 @@ -0,0 +1,3006 @@
82699 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
82703 +CONFIG_CLANG_VERSION=0
82936 +CONFIG_HI_ZRELADDR=0x40008000
82937 +CONFIG_HI_PARAMS_PHYS=0x00000100
82938 +CONFIG_HI_INITRD_PHYS=0x00800000
83046 +CONFIG_PAGE_OFFSET=0xC0000000
83048 +CONFIG_ARCH_NR_GPIO=0
83049 +CONFIG_HZ_FIXED=0
83080 +CONFIG_ZBOOT_ROM_TEXT=0
83081 +CONFIG_ZBOOT_ROM_BSS=0
83207 +CONFIG_BASE_SMALL=0
83397 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
83760 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
83761 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
85243 +CONFIG_JFFS2_FS_DEBUG=0
85626 +CONFIG_PANIC_ON_OOPS_VALUE=0
85627 +CONFIG_PANIC_TIMEOUT=0
85704 @@ -0,0 +1,1776 @@
85711 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
85715 +CONFIG_CLANG_VERSION=0
85947 +CONFIG_HI_ZRELADDR=0x40008000
85948 +CONFIG_HI_PARAMS_PHYS=0x00000100
85949 +CONFIG_HI_INITRD_PHYS=0x00800000
86057 +CONFIG_PAGE_OFFSET=0xC0000000
86059 +CONFIG_ARCH_NR_GPIO=0
86060 +CONFIG_HZ_FIXED=0
86091 +CONFIG_ZBOOT_ROM_TEXT=0
86092 +CONFIG_ZBOOT_ROM_BSS=0
86217 +CONFIG_BASE_SMALL=0
87213 +CONFIG_JFFS2_FS_DEBUG=0
87408 +CONFIG_PANIC_ON_OOPS_VALUE=0
87409 +CONFIG_PANIC_TIMEOUT=0
87486 @@ -0,0 +1,3048 @@
87493 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
87497 +CONFIG_CLANG_VERSION=0
87745 +CONFIG_AMP_ZRELADDR=0x25008000
87746 +CONFIG_HI_ZRELADDR=0x22008000
87747 +CONFIG_HI_PARAMS_PHYS=0x00000100
87748 +CONFIG_HI_INITRD_PHYS=0x00800000
87856 +CONFIG_PAGE_OFFSET=0xC0000000
87858 +CONFIG_ARCH_NR_GPIO=0
87859 +CONFIG_HZ_FIXED=0
87891 +CONFIG_ZBOOT_ROM_TEXT=0
87892 +CONFIG_ZBOOT_ROM_BSS=0
88019 +CONFIG_BASE_SMALL=0
88237 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
88600 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
88601 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
90034 +CONFIG_JFFS2_FS_DEBUG=0
90435 +CONFIG_PANIC_ON_OOPS_VALUE=0
90436 +CONFIG_PANIC_TIMEOUT=0
90540 @@ -0,0 +1,3015 @@
90547 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
90551 +CONFIG_CLANG_VERSION=0
90799 +CONFIG_AMP_ZRELADDR=0x25008000
90800 +CONFIG_HI_ZRELADDR=0x22008000
90801 +CONFIG_HI_PARAMS_PHYS=0x00000100
90802 +CONFIG_HI_INITRD_PHYS=0x00800000
90910 +CONFIG_PAGE_OFFSET=0xC0000000
90912 +CONFIG_ARCH_NR_GPIO=0
90913 +CONFIG_HZ_FIXED=0
90945 +CONFIG_ZBOOT_ROM_TEXT=0
90946 +CONFIG_ZBOOT_ROM_BSS=0
91073 +CONFIG_BASE_SMALL=0
91293 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
91634 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
91635 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
93456 +CONFIG_PANIC_ON_OOPS_VALUE=0
93457 +CONFIG_PANIC_TIMEOUT=0
93561 @@ -0,0 +1,3038 @@
93568 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
93572 +CONFIG_CLANG_VERSION=0
93820 +CONFIG_AMP_ZRELADDR=0x25008000
93821 +CONFIG_HI_ZRELADDR=0x22008000
93822 +CONFIG_HI_PARAMS_PHYS=0x00000100
93823 +CONFIG_HI_INITRD_PHYS=0x00800000
93931 +CONFIG_PAGE_OFFSET=0xC0000000
93933 +CONFIG_ARCH_NR_GPIO=0
93934 +CONFIG_HZ_FIXED=0
93966 +CONFIG_ZBOOT_ROM_TEXT=0
93967 +CONFIG_ZBOOT_ROM_BSS=0
94094 +CONFIG_BASE_SMALL=0
94312 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
94671 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
94672 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
96105 +CONFIG_JFFS2_FS_DEBUG=0
96500 +CONFIG_PANIC_ON_OOPS_VALUE=0
96501 +CONFIG_PANIC_TIMEOUT=0
96605 @@ -0,0 +1,3500 @@
96612 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
96616 +CONFIG_CLANG_VERSION=0
96872 +CONFIG_HI_ZRELADDR=0x22008000
96873 +CONFIG_HI_PARAMS_PHYS=0x00000100
96874 +CONFIG_HI_INITRD_PHYS=0x00800000
97036 +CONFIG_PAGE_OFFSET=0xC0000000
97040 +CONFIG_ARCH_NR_GPIO=0
97041 +CONFIG_HZ_FIXED=0
97073 +CONFIG_ZBOOT_ROM_TEXT=0
97074 +CONFIG_ZBOOT_ROM_BSS=0
97203 +CONFIG_BASE_SMALL=0
97436 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
97894 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
97895 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
99606 +CONFIG_JFFS2_FS_DEBUG=0
100002 +CONFIG_PANIC_ON_OOPS_VALUE=0
100003 +CONFIG_PANIC_TIMEOUT=0
100111 @@ -0,0 +1,3465 @@
100118 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
100122 +CONFIG_CLANG_VERSION=0
100378 +CONFIG_HI_ZRELADDR=0x22008000
100379 +CONFIG_HI_PARAMS_PHYS=0x00000100
100380 +CONFIG_HI_INITRD_PHYS=0x00800000
100542 +CONFIG_PAGE_OFFSET=0xC0000000
100546 +CONFIG_ARCH_NR_GPIO=0
100547 +CONFIG_HZ_FIXED=0
100579 +CONFIG_ZBOOT_ROM_TEXT=0
100580 +CONFIG_ZBOOT_ROM_BSS=0
100709 +CONFIG_BASE_SMALL=0
100942 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
101375 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
101376 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
103086 +CONFIG_JFFS2_FS_DEBUG=0
103473 +CONFIG_PANIC_ON_OOPS_VALUE=0
103474 +CONFIG_PANIC_TIMEOUT=0
103582 @@ -0,0 +1,3493 @@
103589 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
103593 +CONFIG_CLANG_VERSION=0
103849 +CONFIG_HI_ZRELADDR=0x22008000
103850 +CONFIG_HI_PARAMS_PHYS=0x00000100
103851 +CONFIG_HI_INITRD_PHYS=0x00800000
104013 +CONFIG_PAGE_OFFSET=0xC0000000
104017 +CONFIG_ARCH_NR_GPIO=0
104018 +CONFIG_HZ_FIXED=0
104049 +CONFIG_ZBOOT_ROM_TEXT=0
104050 +CONFIG_ZBOOT_ROM_BSS=0
104179 +CONFIG_BASE_SMALL=0
104411 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
104865 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
104866 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
106577 +CONFIG_JFFS2_FS_DEBUG=0
106972 +CONFIG_PANIC_ON_OOPS_VALUE=0
106973 +CONFIG_PANIC_TIMEOUT=0
107081 @@ -0,0 +1,2628 @@
107100 +CONFIG_VECTORS_BASE=0xffff0000
107319 +CONFIG_BASE_SMALL=0
107433 +CONFIG_HI_ZRELADDR=0x80008000
107434 +CONFIG_HI_PARAMS_PHYS=0x00000100
107435 +CONFIG_HI_INITRD_PHYS=0x00800000
107537 +CONFIG_PAGE_OFFSET=0xC0000000
107539 +CONFIG_ARCH_NR_GPIO=0
107543 +CONFIG_HZ_FIXED=0
107599 +CONFIG_ZBOOT_ROM_TEXT=0
107600 +CONFIG_ZBOOT_ROM_BSS=0
107858 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
108157 +CONFIG_HISI_SATA_IOBASE=0x11010000
108223 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
108224 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
109237 +CONFIG_JFFS2_FS_DEBUG=0
109405 +CONFIG_PANIC_ON_OOPS_VALUE=0
109406 +CONFIG_PANIC_TIMEOUT=0
109715 @@ -0,0 +1,3201 @@
109722 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
109726 +CONFIG_CLANG_VERSION=0
109967 +CONFIG_HI_ZRELADDR=0x40008000
109968 +CONFIG_HI_PARAMS_PHYS=0x00000100
109969 +CONFIG_HI_INITRD_PHYS=0x00800000
110086 +CONFIG_PAGE_OFFSET=0xC0000000
110090 +CONFIG_ARCH_NR_GPIO=0
110091 +CONFIG_HZ_FIXED=0
110123 +CONFIG_ZBOOT_ROM_TEXT=0
110124 +CONFIG_ZBOOT_ROM_BSS=0
110252 +CONFIG_BASE_SMALL=0
110522 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
110834 +CONFIG_HISI_SATA_IOBASE=0x10390000
110908 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
110909 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
112295 +CONFIG_HISI_SATA_MODE=0
112414 +CONFIG_JFFS2_FS_DEBUG=0
112814 +CONFIG_PANIC_ON_OOPS_VALUE=0
112815 +CONFIG_PANIC_TIMEOUT=0
112919 index 000000000..0de65f21f
112922 @@ -0,0 +1,3085 @@
112929 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
112933 +CONFIG_CLANG_VERSION=0
113174 +CONFIG_HI_ZRELADDR=0x40008000
113175 +CONFIG_HI_PARAMS_PHYS=0x00000100
113176 +CONFIG_HI_INITRD_PHYS=0x00800000
113293 +CONFIG_PAGE_OFFSET=0xC0000000
113297 +CONFIG_ARCH_NR_GPIO=0
113298 +CONFIG_HZ_FIXED=0
113330 +CONFIG_ZBOOT_ROM_TEXT=0
113331 +CONFIG_ZBOOT_ROM_BSS=0
113459 +CONFIG_BASE_SMALL=0
113729 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
113943 +CONFIG_HISI_SATA_IOBASE=0x10390000
114017 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
114018 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
115404 +CONFIG_HISI_SATA_MODE=0
115905 +CONFIG_PANIC_ON_OOPS_VALUE=0
115906 +CONFIG_PANIC_TIMEOUT=0
116013 @@ -0,0 +1,2628 @@
116032 +CONFIG_VECTORS_BASE=0xffff0000
116251 +CONFIG_BASE_SMALL=0
116365 +CONFIG_HI_ZRELADDR=0x80008000
116366 +CONFIG_HI_PARAMS_PHYS=0x00000100
116367 +CONFIG_HI_INITRD_PHYS=0x00800000
116469 +CONFIG_PAGE_OFFSET=0xC0000000
116471 +CONFIG_ARCH_NR_GPIO=0
116475 +CONFIG_HZ_FIXED=0
116531 +CONFIG_ZBOOT_ROM_TEXT=0
116532 +CONFIG_ZBOOT_ROM_BSS=0
116790 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
117089 +CONFIG_HISI_SATA_IOBASE=0x11010000
117155 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
117156 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
118169 +CONFIG_JFFS2_FS_DEBUG=0
118337 +CONFIG_PANIC_ON_OOPS_VALUE=0
118338 +CONFIG_PANIC_TIMEOUT=0
118647 @@ -0,0 +1,3201 @@
118654 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
118658 +CONFIG_CLANG_VERSION=0
118899 +CONFIG_HI_ZRELADDR=0x40008000
118900 +CONFIG_HI_PARAMS_PHYS=0x00000100
118901 +CONFIG_HI_INITRD_PHYS=0x00800000
119018 +CONFIG_PAGE_OFFSET=0xC0000000
119022 +CONFIG_ARCH_NR_GPIO=0
119023 +CONFIG_HZ_FIXED=0
119055 +CONFIG_ZBOOT_ROM_TEXT=0
119056 +CONFIG_ZBOOT_ROM_BSS=0
119184 +CONFIG_BASE_SMALL=0
119454 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
119766 +CONFIG_HISI_SATA_IOBASE=0x10390000
119840 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
119841 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
121227 +CONFIG_HISI_SATA_MODE=0
121346 +CONFIG_JFFS2_FS_DEBUG=0
121746 +CONFIG_PANIC_ON_OOPS_VALUE=0
121747 +CONFIG_PANIC_TIMEOUT=0
121854 @@ -0,0 +1,3085 @@
121861 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
121865 +CONFIG_CLANG_VERSION=0
122106 +CONFIG_HI_ZRELADDR=0x40008000
122107 +CONFIG_HI_PARAMS_PHYS=0x00000100
122108 +CONFIG_HI_INITRD_PHYS=0x00800000
122225 +CONFIG_PAGE_OFFSET=0xC0000000
122229 +CONFIG_ARCH_NR_GPIO=0
122230 +CONFIG_HZ_FIXED=0
122262 +CONFIG_ZBOOT_ROM_TEXT=0
122263 +CONFIG_ZBOOT_ROM_BSS=0
122391 +CONFIG_BASE_SMALL=0
122661 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
122875 +CONFIG_HISI_SATA_IOBASE=0x10390000
122949 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
122950 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
124336 +CONFIG_HISI_SATA_MODE=0
124837 +CONFIG_PANIC_ON_OOPS_VALUE=0
124838 +CONFIG_PANIC_TIMEOUT=0
124945 @@ -0,0 +1,2873 @@
124964 +CONFIG_VECTORS_BASE=0xffff0000
125191 +CONFIG_BASE_SMALL=0
125310 +CONFIG_HI_ZRELADDR=0x40008000
125311 +CONFIG_HI_PARAMS_PHYS=0x00000100
125312 +CONFIG_HI_INITRD_PHYS=0x00800000
125466 +CONFIG_PAGE_OFFSET=0xC0000000
125470 +CONFIG_ARCH_NR_GPIO=0
125474 +CONFIG_HZ_FIXED=0
125531 +CONFIG_ZBOOT_ROM_TEXT=0
125532 +CONFIG_ZBOOT_ROM_BSS=0
125745 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
126109 +CONFIG_HISI_SATA_IOBASE=0x11010000
126202 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
126203 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
127330 +CONFIG_JFFS2_FS_DEBUG=0
127482 +CONFIG_PANIC_ON_OOPS_VALUE=0
127483 +CONFIG_PANIC_TIMEOUT=0
127824 @@ -0,0 +1,2920 @@
127843 +CONFIG_VECTORS_BASE=0xffff0000
128070 +CONFIG_BASE_SMALL=0
128189 +CONFIG_HI_ZRELADDR=0x40008000
128190 +CONFIG_HI_PARAMS_PHYS=0x00000100
128191 +CONFIG_HI_INITRD_PHYS=0x00800000
128340 +CONFIG_PAGE_OFFSET=0xC0000000
128344 +CONFIG_ARCH_NR_GPIO=0
128348 +CONFIG_HZ_FIXED=0
128405 +CONFIG_ZBOOT_ROM_TEXT=0
128406 +CONFIG_ZBOOT_ROM_BSS=0
128619 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
128983 +CONFIG_HISI_SATA_IOBASE=0x11010000
129100 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
129101 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
130256 +CONFIG_JFFS2_FS_DEBUG=0
130408 +CONFIG_PANIC_ON_OOPS_VALUE=0
130409 +CONFIG_PANIC_TIMEOUT=0
130750 @@ -0,0 +1,2868 @@
130769 +CONFIG_VECTORS_BASE=0xffff0000
130996 +CONFIG_BASE_SMALL=0
131115 +CONFIG_HI_ZRELADDR=0x40008000
131116 +CONFIG_HI_PARAMS_PHYS=0x00000100
131117 +CONFIG_HI_INITRD_PHYS=0x00800000
131271 +CONFIG_PAGE_OFFSET=0xC0000000
131275 +CONFIG_ARCH_NR_GPIO=0
131279 +CONFIG_HZ_FIXED=0
131336 +CONFIG_ZBOOT_ROM_TEXT=0
131337 +CONFIG_ZBOOT_ROM_BSS=0
131550 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
131909 +CONFIG_HISI_SATA_IOBASE=0x11010000
132002 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
132003 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
133130 +CONFIG_JFFS2_FS_DEBUG=0
133282 +CONFIG_PANIC_ON_OOPS_VALUE=0
133283 +CONFIG_PANIC_TIMEOUT=0
133624 @@ -0,0 +1,2915 @@
133643 +CONFIG_VECTORS_BASE=0xffff0000
133870 +CONFIG_BASE_SMALL=0
133989 +CONFIG_HI_ZRELADDR=0x40008000
133990 +CONFIG_HI_PARAMS_PHYS=0x00000100
133991 +CONFIG_HI_INITRD_PHYS=0x00800000
134140 +CONFIG_PAGE_OFFSET=0xC0000000
134144 +CONFIG_ARCH_NR_GPIO=0
134148 +CONFIG_HZ_FIXED=0
134205 +CONFIG_ZBOOT_ROM_TEXT=0
134206 +CONFIG_ZBOOT_ROM_BSS=0
134419 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
134778 +CONFIG_HISI_SATA_IOBASE=0x11010000
134895 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
134896 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
136051 +CONFIG_JFFS2_FS_DEBUG=0
136203 +CONFIG_PANIC_ON_OOPS_VALUE=0
136204 +CONFIG_PANIC_TIMEOUT=0
136545 @@ -0,0 +1,2746 @@
136564 +CONFIG_VECTORS_BASE=0xffff0000
136782 +CONFIG_BASE_SMALL=0
136907 +CONFIG_HI_ZRELADDR=0x80008000
136908 +CONFIG_HI_PARAMS_PHYS=0x00000100
136909 +CONFIG_HI_INITRD_PHYS=0x00800000
137011 +CONFIG_PAGE_OFFSET=0xC0000000
137013 +CONFIG_ARCH_NR_GPIO=0
137017 +CONFIG_HZ_FIXED=0
137073 +CONFIG_ZBOOT_ROM_TEXT=0
137074 +CONFIG_ZBOOT_ROM_BSS=0
137292 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
137585 +CONFIG_HISI_SATA_IOBASE=0x10030000
138819 +CONFIG_JFFS2_FS_DEBUG=0
138979 +CONFIG_PANIC_ON_OOPS_VALUE=0
138980 +CONFIG_PANIC_TIMEOUT=0
139297 @@ -0,0 +1,3145 @@
139304 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
139308 +CONFIG_CLANG_VERSION=0
139558 +CONFIG_AMP_ZRELADDR=0x32008000
139559 +CONFIG_HI_ZRELADDR=0x22008000
139560 +CONFIG_HI_PARAMS_PHYS=0x00000100
139561 +CONFIG_HI_INITRD_PHYS=0x00800000
139669 +CONFIG_PAGE_OFFSET=0xC0000000
139671 +CONFIG_ARCH_NR_GPIO=0
139672 +CONFIG_HZ_FIXED=0
139704 +CONFIG_ZBOOT_ROM_TEXT=0
139705 +CONFIG_ZBOOT_ROM_BSS=0
139833 +CONFIG_BASE_SMALL=0
140036 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
140399 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
140400 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
141933 +CONFIG_JFFS2_FS_DEBUG=0
142343 +CONFIG_PANIC_ON_OOPS_VALUE=0
142344 +CONFIG_PANIC_TIMEOUT=0
142448 @@ -0,0 +1,2986 @@
142455 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
142459 +CONFIG_CLANG_VERSION=0
142709 +CONFIG_AMP_ZRELADDR=0x32008000
142710 +CONFIG_HI_ZRELADDR=0x22008000
142711 +CONFIG_HI_PARAMS_PHYS=0x00000100
142712 +CONFIG_HI_INITRD_PHYS=0x00800000
142820 +CONFIG_PAGE_OFFSET=0xC0000000
142822 +CONFIG_ARCH_NR_GPIO=0
142823 +CONFIG_HZ_FIXED=0
142855 +CONFIG_ZBOOT_ROM_TEXT=0
142856 +CONFIG_ZBOOT_ROM_BSS=0
142984 +CONFIG_BASE_SMALL=0
143186 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
143525 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
143526 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
144952 +CONFIG_JFFS2_FS_DEBUG=0
145334 +CONFIG_PANIC_ON_OOPS_VALUE=0
145335 +CONFIG_PANIC_TIMEOUT=0
145440 @@ -0,0 +1,3014 @@
145447 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
145451 +CONFIG_CLANG_VERSION=0
145701 +CONFIG_AMP_ZRELADDR=0x32008000
145702 +CONFIG_HI_ZRELADDR=0x22008000
145703 +CONFIG_HI_PARAMS_PHYS=0x00000100
145704 +CONFIG_HI_INITRD_PHYS=0x00800000
145812 +CONFIG_PAGE_OFFSET=0xC0000000
145814 +CONFIG_ARCH_NR_GPIO=0
145815 +CONFIG_HZ_FIXED=0
145847 +CONFIG_ZBOOT_ROM_TEXT=0
145848 +CONFIG_ZBOOT_ROM_BSS=0
145976 +CONFIG_BASE_SMALL=0
146178 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
146535 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
146536 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
147963 +CONFIG_JFFS2_FS_DEBUG=0
148354 +CONFIG_PANIC_ON_OOPS_VALUE=0
148355 +CONFIG_PANIC_TIMEOUT=0
148460 @@ -0,0 +1,3042 @@
148467 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
148471 +CONFIG_CLANG_VERSION=0
148720 +CONFIG_AMP_ZRELADDR=0x25008000
148721 +CONFIG_HI_ZRELADDR=0x22008000
148722 +CONFIG_HI_PARAMS_PHYS=0x00000100
148723 +CONFIG_HI_INITRD_PHYS=0x00800000
148831 +CONFIG_PAGE_OFFSET=0xC0000000
148833 +CONFIG_ARCH_NR_GPIO=0
148834 +CONFIG_HZ_FIXED=0
148866 +CONFIG_ZBOOT_ROM_TEXT=0
148867 +CONFIG_ZBOOT_ROM_BSS=0
148995 +CONFIG_BASE_SMALL=0
149196 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
151024 +CONFIG_JFFS2_FS_DEBUG=0
151403 +CONFIG_PANIC_ON_OOPS_VALUE=0
151404 +CONFIG_PANIC_TIMEOUT=0
151508 @@ -0,0 +1,2899 @@
151515 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
151519 +CONFIG_CLANG_VERSION=0
151765 +CONFIG_AMP_ZRELADDR=0x82008000
151766 +CONFIG_HI_ZRELADDR=0x82008000
151767 +CONFIG_HI_PARAMS_PHYS=0x00000100
151768 +CONFIG_HI_INITRD_PHYS=0x00800000
151876 +CONFIG_PAGE_OFFSET=0xC0000000
151878 +CONFIG_ARCH_NR_GPIO=0
151879 +CONFIG_HZ_FIXED=0
151911 +CONFIG_ZBOOT_ROM_TEXT=0
151912 +CONFIG_ZBOOT_ROM_BSS=0
152040 +CONFIG_BASE_SMALL=0
152255 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
153935 +CONFIG_JFFS2_FS_DEBUG=0
154307 +CONFIG_PANIC_ON_OOPS_VALUE=0
154308 +CONFIG_PANIC_TIMEOUT=0
154413 @@ -0,0 +1,2805 @@
154420 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
154424 +CONFIG_CLANG_VERSION=0
154670 +CONFIG_AMP_ZRELADDR=0x82008000
154671 +CONFIG_HI_ZRELADDR=0x82008000
154672 +CONFIG_HI_PARAMS_PHYS=0x00000100
154673 +CONFIG_HI_INITRD_PHYS=0x00800000
154781 +CONFIG_PAGE_OFFSET=0xC0000000
154783 +CONFIG_ARCH_NR_GPIO=0
154784 +CONFIG_HZ_FIXED=0
154816 +CONFIG_ZBOOT_ROM_TEXT=0
154817 +CONFIG_ZBOOT_ROM_BSS=0
154945 +CONFIG_BASE_SMALL=0
155160 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
157118 +CONFIG_PANIC_ON_OOPS_VALUE=0
157119 +CONFIG_PANIC_TIMEOUT=0
157224 @@ -0,0 +1,2902 @@
157231 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
157235 +CONFIG_CLANG_VERSION=0
157481 +CONFIG_AMP_ZRELADDR=0x82008000
157482 +CONFIG_HI_ZRELADDR=0x82008000
157483 +CONFIG_HI_PARAMS_PHYS=0x00000100
157484 +CONFIG_HI_INITRD_PHYS=0x00800000
157592 +CONFIG_PAGE_OFFSET=0xC0000000
157594 +CONFIG_ARCH_NR_GPIO=0
157595 +CONFIG_HZ_FIXED=0
157627 +CONFIG_ZBOOT_ROM_TEXT=0
157628 +CONFIG_ZBOOT_ROM_BSS=0
157756 +CONFIG_BASE_SMALL=0
157971 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
160026 +CONFIG_PANIC_ON_OOPS_VALUE=0
160027 +CONFIG_PANIC_TIMEOUT=0
160132 @@ -0,0 +1,2866 @@
160139 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
160143 +CONFIG_CLANG_VERSION=0
160398 +CONFIG_HI_ZRELADDR=0x80008000
160399 +CONFIG_HI_PARAMS_PHYS=0x00000100
160400 +CONFIG_HI_INITRD_PHYS=0x00800000
160517 +CONFIG_PAGE_OFFSET=0xC0000000
160521 +CONFIG_ARCH_NR_GPIO=0
160522 +CONFIG_HZ_FIXED=0
160554 +CONFIG_ZBOOT_ROM_TEXT=0
160555 +CONFIG_ZBOOT_ROM_BSS=0
160685 +CONFIG_BASE_SMALL=0
160896 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
162895 +CONFIG_PANIC_ON_OOPS_VALUE=0
162896 +CONFIG_PANIC_TIMEOUT=0
163004 @@ -0,0 +1,2985 @@
163011 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
163015 +CONFIG_CLANG_VERSION=0
163270 +CONFIG_HI_ZRELADDR=0x80008000
163271 +CONFIG_HI_PARAMS_PHYS=0x00000100
163272 +CONFIG_HI_INITRD_PHYS=0x00800000
163389 +CONFIG_PAGE_OFFSET=0xC0000000
163393 +CONFIG_ARCH_NR_GPIO=0
163394 +CONFIG_HZ_FIXED=0
163426 +CONFIG_ZBOOT_ROM_TEXT=0
163427 +CONFIG_ZBOOT_ROM_BSS=0
163557 +CONFIG_BASE_SMALL=0
163768 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
165491 +CONFIG_JFFS2_FS_DEBUG=0
165886 +CONFIG_PANIC_ON_OOPS_VALUE=0
165887 +CONFIG_PANIC_TIMEOUT=0
165995 @@ -0,0 +1,2917 @@
166002 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
166006 +CONFIG_CLANG_VERSION=0
166252 +CONFIG_AMP_ZRELADDR=0x82008000
166253 +CONFIG_HI_ZRELADDR=0x82008000
166254 +CONFIG_HI_PARAMS_PHYS=0x00000100
166255 +CONFIG_HI_INITRD_PHYS=0x00800000
166363 +CONFIG_PAGE_OFFSET=0xC0000000
166365 +CONFIG_ARCH_NR_GPIO=0
166366 +CONFIG_HZ_FIXED=0
166398 +CONFIG_ZBOOT_ROM_TEXT=0
166399 +CONFIG_ZBOOT_ROM_BSS=0
166527 +CONFIG_BASE_SMALL=0
166742 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
168440 +CONFIG_JFFS2_FS_DEBUG=0
168812 +CONFIG_PANIC_ON_OOPS_VALUE=0
168813 +CONFIG_PANIC_TIMEOUT=0
168918 @@ -0,0 +1,2823 @@
168925 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
168929 +CONFIG_CLANG_VERSION=0
169175 +CONFIG_AMP_ZRELADDR=0x82008000
169176 +CONFIG_HI_ZRELADDR=0x82008000
169177 +CONFIG_HI_PARAMS_PHYS=0x00000100
169178 +CONFIG_HI_INITRD_PHYS=0x00800000
169286 +CONFIG_PAGE_OFFSET=0xC0000000
169288 +CONFIG_ARCH_NR_GPIO=0
169289 +CONFIG_HZ_FIXED=0
169321 +CONFIG_ZBOOT_ROM_TEXT=0
169322 +CONFIG_ZBOOT_ROM_BSS=0
169450 +CONFIG_BASE_SMALL=0
169665 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
171641 +CONFIG_PANIC_ON_OOPS_VALUE=0
171642 +CONFIG_PANIC_TIMEOUT=0
171747 @@ -0,0 +1,2920 @@
171754 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
171758 +CONFIG_CLANG_VERSION=0
172004 +CONFIG_AMP_ZRELADDR=0x82008000
172005 +CONFIG_HI_ZRELADDR=0x82008000
172006 +CONFIG_HI_PARAMS_PHYS=0x00000100
172007 +CONFIG_HI_INITRD_PHYS=0x00800000
172115 +CONFIG_PAGE_OFFSET=0xC0000000
172117 +CONFIG_ARCH_NR_GPIO=0
172118 +CONFIG_HZ_FIXED=0
172150 +CONFIG_ZBOOT_ROM_TEXT=0
172151 +CONFIG_ZBOOT_ROM_BSS=0
172279 +CONFIG_BASE_SMALL=0
172494 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
174567 +CONFIG_PANIC_ON_OOPS_VALUE=0
174568 +CONFIG_PANIC_TIMEOUT=0
174673 @@ -0,0 +1,2866 @@
174680 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
174684 +CONFIG_CLANG_VERSION=0
174939 +CONFIG_HI_ZRELADDR=0x80008000
174940 +CONFIG_HI_PARAMS_PHYS=0x00000100
174941 +CONFIG_HI_INITRD_PHYS=0x00800000
175058 +CONFIG_PAGE_OFFSET=0xC0000000
175062 +CONFIG_ARCH_NR_GPIO=0
175063 +CONFIG_HZ_FIXED=0
175095 +CONFIG_ZBOOT_ROM_TEXT=0
175096 +CONFIG_ZBOOT_ROM_BSS=0
175226 +CONFIG_BASE_SMALL=0
175437 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
177436 +CONFIG_PANIC_ON_OOPS_VALUE=0
177437 +CONFIG_PANIC_TIMEOUT=0
177545 @@ -0,0 +1,2985 @@
177552 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
177556 +CONFIG_CLANG_VERSION=0
177811 +CONFIG_HI_ZRELADDR=0x80008000
177812 +CONFIG_HI_PARAMS_PHYS=0x00000100
177813 +CONFIG_HI_INITRD_PHYS=0x00800000
177930 +CONFIG_PAGE_OFFSET=0xC0000000
177934 +CONFIG_ARCH_NR_GPIO=0
177935 +CONFIG_HZ_FIXED=0
177967 +CONFIG_ZBOOT_ROM_TEXT=0
177968 +CONFIG_ZBOOT_ROM_BSS=0
178098 +CONFIG_BASE_SMALL=0
178309 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
180032 +CONFIG_JFFS2_FS_DEBUG=0
180427 +CONFIG_PANIC_ON_OOPS_VALUE=0
180428 +CONFIG_PANIC_TIMEOUT=0
180536 @@ -0,0 +1,2875 @@
180543 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
180547 +CONFIG_CLANG_VERSION=0
180792 +CONFIG_HI_ZRELADDR=0x82008000
180793 +CONFIG_HI_PARAMS_PHYS=0x00000100
180794 +CONFIG_HI_INITRD_PHYS=0x00800000
180902 +CONFIG_PAGE_OFFSET=0xC0000000
180904 +CONFIG_ARCH_NR_GPIO=0
180905 +CONFIG_HZ_FIXED=0
180937 +CONFIG_ZBOOT_ROM_TEXT=0
180938 +CONFIG_ZBOOT_ROM_BSS=0
181066 +CONFIG_BASE_SMALL=0
181300 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
182939 +CONFIG_JFFS2_FS_DEBUG=0
183311 +CONFIG_PANIC_ON_OOPS_VALUE=0
183312 +CONFIG_PANIC_TIMEOUT=0
183417 @@ -0,0 +1,2881 @@
183424 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
183428 +CONFIG_CLANG_VERSION=0
183673 +CONFIG_HI_ZRELADDR=0x82008000
183674 +CONFIG_HI_PARAMS_PHYS=0x00000100
183675 +CONFIG_HI_INITRD_PHYS=0x00800000
183783 +CONFIG_PAGE_OFFSET=0xC0000000
183785 +CONFIG_ARCH_NR_GPIO=0
183786 +CONFIG_HZ_FIXED=0
183818 +CONFIG_ZBOOT_ROM_TEXT=0
183819 +CONFIG_ZBOOT_ROM_BSS=0
183947 +CONFIG_BASE_SMALL=0
184182 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
186198 +CONFIG_PANIC_ON_OOPS_VALUE=0
186199 +CONFIG_PANIC_TIMEOUT=0
186304 @@ -0,0 +1,2978 @@
186311 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
186315 +CONFIG_CLANG_VERSION=0
186560 +CONFIG_HI_ZRELADDR=0x82008000
186561 +CONFIG_HI_PARAMS_PHYS=0x00000100
186562 +CONFIG_HI_INITRD_PHYS=0x00800000
186670 +CONFIG_PAGE_OFFSET=0xC0000000
186672 +CONFIG_ARCH_NR_GPIO=0
186673 +CONFIG_HZ_FIXED=0
186705 +CONFIG_ZBOOT_ROM_TEXT=0
186706 +CONFIG_ZBOOT_ROM_BSS=0
186834 +CONFIG_BASE_SMALL=0
187069 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
189182 +CONFIG_PANIC_ON_OOPS_VALUE=0
189183 +CONFIG_PANIC_TIMEOUT=0
189288 @@ -0,0 +1,2975 @@
189295 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
189299 +CONFIG_CLANG_VERSION=0
189544 +CONFIG_HI_ZRELADDR=0x82008000
189545 +CONFIG_HI_PARAMS_PHYS=0x00000100
189546 +CONFIG_HI_INITRD_PHYS=0x00800000
189654 +CONFIG_PAGE_OFFSET=0xC0000000
189656 +CONFIG_ARCH_NR_GPIO=0
189657 +CONFIG_HZ_FIXED=0
189689 +CONFIG_ZBOOT_ROM_TEXT=0
189690 +CONFIG_ZBOOT_ROM_BSS=0
189818 +CONFIG_BASE_SMALL=0
190053 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
191791 +CONFIG_JFFS2_FS_DEBUG=0
192163 +CONFIG_PANIC_ON_OOPS_VALUE=0
192164 +CONFIG_PANIC_TIMEOUT=0
192269 @@ -0,0 +1,2881 @@
192276 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
192280 +CONFIG_CLANG_VERSION=0
192525 +CONFIG_HI_ZRELADDR=0x82008000
192526 +CONFIG_HI_PARAMS_PHYS=0x00000100
192527 +CONFIG_HI_INITRD_PHYS=0x00800000
192635 +CONFIG_PAGE_OFFSET=0xC0000000
192637 +CONFIG_ARCH_NR_GPIO=0
192638 +CONFIG_HZ_FIXED=0
192670 +CONFIG_ZBOOT_ROM_TEXT=0
192671 +CONFIG_ZBOOT_ROM_BSS=0
192799 +CONFIG_BASE_SMALL=0
193034 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
195050 +CONFIG_PANIC_ON_OOPS_VALUE=0
195051 +CONFIG_PANIC_TIMEOUT=0
195156 @@ -0,0 +1,2978 @@
195163 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
195167 +CONFIG_CLANG_VERSION=0
195412 +CONFIG_HI_ZRELADDR=0x82008000
195413 +CONFIG_HI_PARAMS_PHYS=0x00000100
195414 +CONFIG_HI_INITRD_PHYS=0x00800000
195522 +CONFIG_PAGE_OFFSET=0xC0000000
195524 +CONFIG_ARCH_NR_GPIO=0
195525 +CONFIG_HZ_FIXED=0
195557 +CONFIG_ZBOOT_ROM_TEXT=0
195558 +CONFIG_ZBOOT_ROM_BSS=0
195686 +CONFIG_BASE_SMALL=0
195921 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
198034 +CONFIG_PANIC_ON_OOPS_VALUE=0
198035 +CONFIG_PANIC_TIMEOUT=0
198140 @@ -0,0 +1,3048 @@
198147 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
198151 +CONFIG_CLANG_VERSION=0
198399 +CONFIG_AMP_ZRELADDR=0x25008000
198400 +CONFIG_HI_ZRELADDR=0x22008000
198401 +CONFIG_HI_PARAMS_PHYS=0x00000100
198402 +CONFIG_HI_INITRD_PHYS=0x00800000
198510 +CONFIG_PAGE_OFFSET=0xC0000000
198512 +CONFIG_ARCH_NR_GPIO=0
198513 +CONFIG_HZ_FIXED=0
198545 +CONFIG_ZBOOT_ROM_TEXT=0
198546 +CONFIG_ZBOOT_ROM_BSS=0
198673 +CONFIG_BASE_SMALL=0
198891 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
199254 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
199255 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
200688 +CONFIG_JFFS2_FS_DEBUG=0
201089 +CONFIG_PANIC_ON_OOPS_VALUE=0
201090 +CONFIG_PANIC_TIMEOUT=0
201194 @@ -0,0 +1,3015 @@
201201 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
201205 +CONFIG_CLANG_VERSION=0
201453 +CONFIG_AMP_ZRELADDR=0x25008000
201454 +CONFIG_HI_ZRELADDR=0x22008000
201455 +CONFIG_HI_PARAMS_PHYS=0x00000100
201456 +CONFIG_HI_INITRD_PHYS=0x00800000
201564 +CONFIG_PAGE_OFFSET=0xC0000000
201566 +CONFIG_ARCH_NR_GPIO=0
201567 +CONFIG_HZ_FIXED=0
201599 +CONFIG_ZBOOT_ROM_TEXT=0
201600 +CONFIG_ZBOOT_ROM_BSS=0
201727 +CONFIG_BASE_SMALL=0
201947 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
202288 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
202289 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
204110 +CONFIG_PANIC_ON_OOPS_VALUE=0
204111 +CONFIG_PANIC_TIMEOUT=0
204215 @@ -0,0 +1,3038 @@
204222 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
204226 +CONFIG_CLANG_VERSION=0
204474 +CONFIG_AMP_ZRELADDR=0x25008000
204475 +CONFIG_HI_ZRELADDR=0x22008000
204476 +CONFIG_HI_PARAMS_PHYS=0x00000100
204477 +CONFIG_HI_INITRD_PHYS=0x00800000
204585 +CONFIG_PAGE_OFFSET=0xC0000000
204587 +CONFIG_ARCH_NR_GPIO=0
204588 +CONFIG_HZ_FIXED=0
204620 +CONFIG_ZBOOT_ROM_TEXT=0
204621 +CONFIG_ZBOOT_ROM_BSS=0
204748 +CONFIG_BASE_SMALL=0
204966 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
205325 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
205326 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
206759 +CONFIG_JFFS2_FS_DEBUG=0
207154 +CONFIG_PANIC_ON_OOPS_VALUE=0
207155 +CONFIG_PANIC_TIMEOUT=0
207315 @@ -0,0 +1,258 @@
207542 + default "0x32008000" if ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3568V100
207543 + default "0x82008000" if ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V20…
207544 + default "0x42008000" if ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI3516DV…
207547 + default "0x40008000" if ARCH_HI3521DV200
207548 + default "0x40008000" if ARCH_HI3520DV500
207549 + default "0x80008000" if ARCH_HI3516CV500
207550 + default "0x80008000" if ARCH_HI3516DV300
207551 + default "0x80008000" if ARCH_HI3556V200
207552 + default "0x80008000" if ARCH_HI3559V200
207553 + default "0x80008000" if ARCH_HI3562V100
207554 + default "0x80008000" if ARCH_HI3566V100
207555 + default "0x80008000" if ARCH_HI3516A
207556 + default "0x80008000" if ARCH_HI3518EV20X
207557 + default "0x80008000" if ARCH_HI3536DV100
207558 + default "0x80008000" if ARCH_HI3521A
207559 + default "0x40008000" if ARCH_HI3531A
207560 + default "0x40008000" if ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI…
207561 + default "0x22008000" if ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3568V100
207565 + default "0x00000100"
207569 + default "0x00800000"
207579 @@ -0,0 +1,27 @@
207612 @@ -0,0 +1,7 @@
207625 @@ -0,0 +1,23 @@
207630 + * phy: 0x20000000 ~ 0x20700000
207631 + * vir: 0xFE100000 ~ 0xFE800000
207633 +#define HI3516A_IOCH2_PHYS 0x20000000
207634 +#define IO_OFFSET_HIGH 0xDE100000
207636 +#define HI3516A_IOCH2_SIZE 0x700000
207638 +/* phy: 0x10000000 ~ 0x100D0000
207639 + * vir: 0xFE000000 ~ 0xFE0D0000
207641 +#define HI3516A_IOCH1_PHYS 0x10000000
207642 +#define IO_OFFSET_LOW 0xEE000000
207644 +#define HI3516A_IOCH1_SIZE 0xD0000
207654 @@ -0,0 +1,26 @@
207659 + * phy: 0x20000000 ~ 0x20700000
207660 + * vir: 0xFE100000 ~ 0xFE800000
207662 +#define HI3516CV500_IOCH2_PHYS 0x20000000
207663 +#define IO_OFFSET_HIGH 0xDE100000
207665 +#define HI3516CV500_IOCH2_SIZE 0x700000
207667 +/* phy: 0x10000000 ~ 0x100E0000
207668 + * vir: 0xFE000000 ~ 0xFE0E0000
207670 +#define HI3516CV500_IOCH1_PHYS 0x10000000
207671 +#define IO_OFFSET_LOW 0xEE000000
207673 +#define HI3516CV500_IOCH1_SIZE 0xE0000
207686 @@ -0,0 +1,4 @@
207696 @@ -0,0 +1,26 @@
207701 + * phy: 0x20000000 ~ 0x20700000
207702 + * vir: 0xFE100000 ~ 0xFE800000
207704 +#define HI3516DV300_IOCH2_PHYS 0x20000000
207705 +#define IO_OFFSET_HIGH 0xDE100000
207707 +#define HI3516DV300_IOCH2_SIZE 0x700000
207709 +/* phy: 0x10000000 ~ 0x100E0000
207710 + * vir: 0xFE000000 ~ 0xFE0E0000
207712 +#define HI3516DV300_IOCH1_PHYS 0x10000000
207713 +#define IO_OFFSET_LOW 0xEE000000
207715 +#define HI3516DV300_IOCH1_SIZE 0xE0000
207728 @@ -0,0 +1,4 @@
207738 @@ -0,0 +1,26 @@
207743 + * phy: 0x20000000 ~ 0x20700000
207744 + * vir: 0xFE100000 ~ 0xFE800000
207746 +#define HI3518EV20X_IOCH2_PHYS 0x20000000
207747 +#define IO_OFFSET_HIGH 0xDE100000
207749 +#define HI3518EV20X_IOCH2_SIZE 0x700000
207751 +/* phy: 0x10000000 ~ 0x100E0000
207752 + * vir: 0xFE000000 ~ 0xFE0E0000
207754 +#define HI3518EV20X_IOCH1_PHYS 0x10000000
207755 +#define IO_OFFSET_LOW 0xEE000000
207757 +#define HI3518EV20X_IOCH1_SIZE 0xE0000
207770 @@ -0,0 +1,11 @@
207775 +#define IO_SPACE_LIMIT 0xFFFFFFFF
207787 @@ -0,0 +1,94 @@
207794 +#define SRAM_BASE_ADDRESS 0x4010000
207796 +#define SYS_CTRL_BASE 0x04520000
207797 +#define REG_BASE_SCTL (SYS_CTRL_BASE + 0)
207798 +#define SYS_CTRL_SYSSTAT 0x8c
207802 +#define GET_SYS_BOOT_MODE(_reg) (((_reg) >> 4) & 0x3)
207803 +#define BOOT_FROM_SPI 0x0
207804 +#define BOOT_FROM_NAND 0x1
207805 +#define BOOT_FROM_EMMC 0x2
207806 +#define BOOT_FROM_SLAVE 0x3
207808 +#define GET_SYS_SPI_DEVICE_TYPE(_reg) (((_reg) & 0x1) >> 3)
207809 +#define DEVICE_TYPE_SPI_NOR 0
207812 +/* bit[5:4:3]=000; bit[7]:SPI nor address mode; bit[7]=(0:3-Byte | 1:4-Byte) */
207813 +#define SPI_NOR_ADDRESS_MODE_MASK (0x1 << 7)
207814 +/* bit[5:4:3]=001; bit[7]: SPI nand I/O widthe; bit[7]=(0: 1-I/O | 1: 4-I/O */
207815 +#define SPI_NAND_IO_WIDTHE_MASK (0x1 << 7)
207816 +/* bit[5:4:3]=10*; bit[7]: EMMC I/O widthe; bit[7]=(0: 4-I/O | 1: 8-I/O */
207817 +#define EMMC_IO_WIDTHE_MASK (0x1 << 7)
207819 +#define BOOT_MODE_MASK ((0x3) << 4)
207821 +#define REG_BASE_SCTL (SYS_CTRL_BASE + 0)
207823 +#define REG_BASE_TIMER01 0x04500000
207824 +#define REG_BASE_TIMER23 0x04501000
207827 +#define REG_BASE_CRG 0x04510000
207828 +#define REG_BASE_UART0 0x04540000
207829 +#define REG_BASE_UART1 0x04541000
207830 +#define REG_BASE_UART2 0x04542000
207831 +#define REG_BASE_UART3 0x04543000
207832 +#define REG_BASE_UART4 0x04544000
207836 +#define PMC_BASE 0x045a0000
207840 + * 0x1-> init item1
207841 + * 0x2-> init item2
207842 + * 0x3->init item1 & item2
207851 +#define CRG48_FMC 0xc0
207852 +#define CRG48_FMC_CLK_SEL(_clk) (((_clk) & 0x7) << 2)
207854 +#define CRG48_FMC_SOFT_RST_REQ (1 << 0)
207856 +#define FMC_CLK_SEL_MASK (0x7 << 2)
207859 +#define CLK_24M 0x00
207860 +#define CLK_75M 0x01
207861 +#define CLK_125M 0x02
207862 +#define CLK_150M 0x03
207863 +#define CLK_200M 0x04
207866 +#define CLK_250M 0x05
207867 +#define CLK_300M 0x06
207868 +#define CLK_400M 0x07
207887 @@ -0,0 +1,40 @@
207892 + * 0x1000_0000 <-----> 0xFE00_0000
207894 +#define HI3521A_IOCH1_VIRT (0xFE000000)
207895 +#define HI3521A_IOCH1_PHYS (0x10000000)
207896 +#define HI3521A_IOCH1_SIZE (0x00400000)
207899 + * 0x1200_0000 <-----> 0xFE40_0000
207901 +#define HI3521A_IOCH2_VIRT (0xFE400000)
207902 +#define HI3521A_IOCH2_PHYS (0x12000000)
207903 +#define HI3521A_IOCH2_SIZE (0x00230000)
207906 + * 0x1301_0000 <-----> 0xFE70_0000
207908 +#define HI3521A_IOCH3_VIRT (0xFE700000)
207909 +#define HI3521A_IOCH3_PHYS (0x13000000)
207910 +#define HI3521A_IOCH3_SIZE (0x00160000)
207912 +#define IO_OFFSET_LOW (0xEB700000)
207913 +#define IO_OFFSET_MID (0xEC400000)
207914 +#define IO_OFFSET_HIGH (0xEE000000)
207933 @@ -0,0 +1,27 @@
207940 +#define REG_CRG_BASE 0x12040000
207945 +#define HISI_SATA_PHY0_CTLL 0xA0
207946 +#define HISI_SATA_PHY0_CTLH 0xA4
207947 +#define HISI_SATA_PHY1_CTLL 0xAC
207948 +#define HISI_SATA_PHY1_CTLH 0xB0
207950 +#define HISI_SATA_PORT_FIFOTH 0x44
207951 +#define HISI_SATA_PORT_PHYCTL1 0x48
207952 +#define HISI_SATA_PORT_PHYCTL2 0x4C
207953 +#define HISI_SATA_PORT_PHYCTL 0x74
207955 +#define HISI_SATA_PHY_RESET BIT(0)
207966 @@ -0,0 +1,63 @@
207971 +#define IO_SPACE_LIMIT 0xFFFFFFFF
207978 + * 0x1000_0000 <-----> 0xFE00_0000
207979 + * 0x1071_0000 <-----> 0xFE71_0000
207981 +#define HI3531A_IOCH1_VIRT (0xFE000000)
207982 +#define HI3531A_IOCH1_PHYS (0x10000000)
207983 +#define HI3531A_IOCH1_SIZE (0x00710000)
207984 +#define IO_OFFSET_IOCH1 (0xEE000000)
207987 + * 0x1100_0000 <-----> 0xFE78_0000
207988 + * 0x1104_0000 <-----> 0xFE7C_0000
207990 +#define HI3531A_IOCH2_VIRT (0xFE780000)
207991 +#define HI3531A_IOCH2_PHYS (0x11000000)
207992 +#define HI3531A_IOCH2_SIZE (0x00040000)
207993 +#define IO_OFFSET_IOCH2 (0xED780000)
207996 + * 0x1200_0000 <-----> 0xFE80_0000
207997 + * 0x122F_0000 <-----> 0xFEAF_0000
207999 +#define HI3531A_IOCH3_VIRT (0xFE800000)
208000 +#define HI3531A_IOCH3_PHYS (0x12000000)
208001 +#define HI3531A_IOCH3_SIZE (0x002F0000)
208002 +#define IO_OFFSET_IOCH3 (0xEC800000)
208005 + * 0x1300_0000 <-----> 0xFEB0_0000
208006 + * 0x131A_0000 <-----> 0xFECA_0000
208008 +#define HI3531A_IOCH4_VIRT (0xFEB00000)
208009 +#define HI3531A_IOCH4_PHYS (0x13000000)
208010 +#define HI3531A_IOCH4_SIZE (0x001A0000)
208011 +#define IO_OFFSET_IOCH4 (0xEBB00000)
208035 @@ -0,0 +1,65 @@
208042 +#define CRG_REG_BASE 0x12040000
208044 +#define REG_CRG20 0x0050
208045 +#define REG_CRG32 0x0080
208046 +#define REG_CRG72 0x0120
208047 +#define REG_CRG75 0x012c
208048 +#define REG_CRG76 0x0130
208049 +#define REG_CRG77 0x0134
208050 +#define REG_CRG79 0x013c
208051 +#define REG_CRG81 0x0144
208052 +#define REG_CRG82 0x0148
208053 +#define REG_CRG83 0x014c
208054 +#define REG_CRG85 0x0154
208055 +#define REG_CRG87 0x015c
208056 +#define REG_CRG91 0x016c
208061 +#define SYS_CTRL_REG_BASE 0x12050000
208066 +#define MISC_CTRL_REG_BASE 0x12120000
208079 +#define A9_PERI_BASE 0x10300000
208080 +#define REG_A9_PERI_SCU 0x0000
208083 +#define REG_BASE_L2CACHE 0x10700000
208088 +#define HISI_SATA_PORT_FIFOTH 0x44
208089 +#define HISI_SATA_PORT_PHYCTL1 0x48
208090 +#define HISI_SATA_PORT_PHYCTL 0x74
208092 +#define HISI_SATA_PHY_CTL0 0xA0
208093 +#define HISI_SATA_PHY_CTL1 0xA4
208094 +#define HISI_SATA_PHY_CTL2 0xB0
208095 +#define HISI_SATA_RST_PHY_MASK 0xAC
208097 +#define HISI_SATA_FIFOTH_VALUE 0x6ED9F24
208106 @@ -0,0 +1,44 @@
208111 + * 0x1100_0000 <-----> 0xFE00_0000
208112 + * 0x1104_0000 <-----> 0xFE04_0000
208114 +#define HI3536DV100_IOCH1_VIRT (0xFE000000)
208115 +#define HI3536DV100_IOCH1_PHYS (0x11000000)
208116 +#define HI3536DV100_IOCH1_SIZE (0x00040000)
208119 + * 0x1200_0000 <-----> 0xFE10_0000
208120 + * 0x121B_0000 <-----> 0xFE2B_0000
208122 +#define HI3536DV100_IOCH2_VIRT (0xFE100000)
208123 +#define HI3536DV100_IOCH2_PHYS (0x12000000)
208124 +#define HI3536DV100_IOCH2_SIZE (0x001B0000)
208127 + * 0x1300_0000 <-----> 0xFE30_0000
208128 + * 0x1321_0000 <-----> 0xFE51_0000
208130 +#define HI3536DV100_IOCH3_VIRT (0xFE300000)
208131 +#define HI3536DV100_IOCH3_PHYS (0x13000000)
208132 +#define HI3536DV100_IOCH3_SIZE (0x00210000)
208134 +#define IO_OFFSET_LOW (0xEB300000)
208135 +#define IO_OFFSET_MID (0xEC100000)
208136 +#define IO_OFFSET_HIGH (0xED000000)
208156 @@ -0,0 +1,14 @@
208163 +#define REG_CRG_BASE 0x12040000
208168 +#define REG_MISC_CTRL_BASE 0x12120000
208176 @@ -0,0 +1,94 @@
208183 +#define SRAM_BASE_ADDRESS 0x4010000
208185 +#define SYS_CTRL_BASE 0x04520000
208186 +#define REG_BASE_SCTL (SYS_CTRL_BASE + 0)
208187 +#define SYS_CTRL_SYSSTAT 0x8c
208191 +#define GET_SYS_BOOT_MODE(_reg) (((_reg) >> 4) & 0x3)
208192 +#define BOOT_FROM_SPI 0x0
208193 +#define BOOT_FROM_NAND 0x1
208194 +#define BOOT_FROM_EMMC 0x2
208195 +#define BOOT_FROM_SLAVE 0x3
208197 +#define GET_SYS_SPI_DEVICE_TYPE(_reg) (((_reg) & 0x1) >> 3)
208198 +#define DEVICE_TYPE_SPI_NOR 0
208201 +/* bit[5:4:3]=000; bit[7]:SPI nor address mode; bit[7]=(0:3-Byte | 1:4-Byte) */
208202 +#define SPI_NOR_ADDRESS_MODE_MASK (0x1 << 7)
208203 +/* bit[5:4:3]=001; bit[7]: SPI nand I/O widthe; bit[7]=(0: 1-I/O | 1: 4-I/O */
208204 +#define SPI_NAND_IO_WIDTHE_MASK (0x1 << 7)
208205 +/* bit[5:4:3]=10*; bit[7]: EMMC I/O widthe; bit[7]=(0: 4-I/O | 1: 8-I/O */
208206 +#define EMMC_IO_WIDTHE_MASK (0x1 << 7)
208208 +#define BOOT_MODE_MASK ((0x3) << 4)
208210 +#define REG_BASE_SCTL (SYS_CTRL_BASE + 0)
208212 +#define REG_BASE_TIMER01 0x04500000
208213 +#define REG_BASE_TIMER23 0x04501000
208216 +#define REG_BASE_CRG 0x04510000
208217 +#define REG_BASE_UART0 0x04540000
208218 +#define REG_BASE_UART1 0x04541000
208219 +#define REG_BASE_UART2 0x04542000
208220 +#define REG_BASE_UART3 0x04543000
208221 +#define REG_BASE_UART4 0x04544000
208225 +#define PMC_BASE 0x045a0000
208229 + * 0x1-> init item1
208230 + * 0x2-> init item2
208231 + * 0x3->init item1 & item2
208240 +#define CRG48_FMC 0xc0
208241 +#define CRG48_FMC_CLK_SEL(_clk) (((_clk) & 0x7) << 2)
208243 +#define CRG48_FMC_SOFT_RST_REQ (1 << 0)
208245 +#define FMC_CLK_SEL_MASK (0x7 << 2)
208248 +#define CLK_24M 0x00
208249 +#define CLK_75M 0x01
208250 +#define CLK_125M 0x02
208251 +#define CLK_150M 0x03
208252 +#define CLK_200M 0x04
208255 +#define CLK_250M 0x05
208256 +#define CLK_300M 0x06
208257 +#define CLK_400M 0x07
208276 @@ -0,0 +1,26 @@
208281 + * phy: 0x20000000 ~ 0x20700000
208282 + * vir: 0xFE100000 ~ 0xFE800000
208284 +#define HI3556V200_IOCH2_PHYS 0x20000000
208285 +#define IO_OFFSET_HIGH 0xDE100000
208287 +#define HI3556V200_IOCH2_SIZE 0x700000
208289 +/* phy: 0x10000000 ~ 0x100E0000
208290 + * vir: 0xFE000000 ~ 0xFE0E0000
208292 +#define HI3556V200_IOCH1_PHYS 0x10000000
208293 +#define IO_OFFSET_LOW 0xEE000000
208295 +#define HI3556V200_IOCH1_SIZE 0xE0000
208308 @@ -0,0 +1,4 @@
208318 @@ -0,0 +1,26 @@
208323 + * phy: 0x20000000 ~ 0x20700000
208324 + * vir: 0xFE100000 ~ 0xFE800000
208326 +#define HI3559V200_IOCH2_PHYS 0x20000000
208327 +#define IO_OFFSET_HIGH 0xDE100000
208329 +#define HI3559V200_IOCH2_SIZE 0x700000
208331 +/* phy: 0x10000000 ~ 0x100E0000
208332 + * vir: 0xFE000000 ~ 0xFE0E0000
208334 +#define HI3559V200_IOCH1_PHYS 0x10000000
208335 +#define IO_OFFSET_LOW 0xEE000000
208337 +#define HI3559V200_IOCH1_SIZE 0xE0000
208350 @@ -0,0 +1,4 @@
208360 @@ -0,0 +1,52 @@
208418 @@ -0,0 +1,52 @@
208476 @@ -0,0 +1,9 @@
208491 @@ -0,0 +1,64 @@
208561 @@ -0,0 +1,68 @@
208587 +#define REG_CPU_SRST_CRG 0x78
208603 + crg_base = of_iomap(np, 0);
208635 @@ -0,0 +1,67 @@
208661 +#define REG_CPU_SRST_CRG 0x78
208677 + crg_base = of_iomap(np, 0);
208708 @@ -0,0 +1,68 @@
208734 +#define REG_CPU_SRST_CRG 0x78
208750 + crg_base = of_iomap(np, 0);
208782 @@ -0,0 +1,67 @@
208808 +#define REG_CPU_SRST_CRG 0x78
208824 + crg_base = of_iomap(np, 0);
208855 @@ -0,0 +1,67 @@
208881 +#define REG_CPU_SRST_CRG 0x78
208897 + crg_base = of_iomap(np, 0);
208928 @@ -0,0 +1,64 @@
208998 @@ -0,0 +1,67 @@
209024 +#define REG_CPU_SRST_CRG 0x78
209040 + crg_base = of_iomap(np, 0);
209071 @@ -0,0 +1,88 @@
209105 + crg_base = ioremap_nocache(0x04510000, 0x1000);
209108 + val = readl_relaxed(crg_base + 0xcc);
209109 + val &= ~((0x1 << 25) | (0x1 << 1));
209110 + writel_relaxed(val, crg_base + 0xcc);
209131 + virt = ioremap_nocache(start_addr, 0x1000);
209133 + writel_relaxed(0xe51ff004, virt);
209145 + hi3519av100_set_boot_addr(0x04200000, jumpaddr);
209149 + return 0;
209165 @@ -0,0 +1,68 @@
209239 @@ -0,0 +1,110 @@
209265 +#define REG_CPU1_SRST_CRG 0x204c
209267 +#define DBG1_SRST_REQ BIT(0)
209269 +#define REG_CPU2_SRST_CRG 0x2050
209271 +#define DBG2_SRST_REQ BIT(0)
209273 +#define REG_CPU3_SRST_CRG 0x2054
209275 +#define DBG3_SRST_REQ BIT(0)
209289 + crg_base = of_iomap(np, 0);
209355 @@ -0,0 +1,185 @@
209442 + " mrc p15, 0, r0, c1, c0, 1\n"
209443 + " orr r0, r0, #0x104\n"
209444 + " mcr p15, 0, r0, c1, c0, 1\n"
209475 + crg_base = of_iomap(np, 0);
209506 + " mrc p15, 0, r0, c1, c0, 1\n"
209507 + " orr r0, r0, #0x0104\n"
209508 + " orr r0, r0, #0x02\n"
209509 + " mcr p15, 0, r0, c1, c0, 1\n"
209525 + return 0;
209546 @@ -0,0 +1,71 @@
209623 @@ -0,0 +1,91 @@
209658 + crg_base = ioremap_nocache(0x04510000, 0x1000);
209661 + val = readl_relaxed(crg_base + 0xcc);
209662 + val &= ~((0x1 << 25) | (0x1 << 1));
209663 + writel_relaxed(val, crg_base + 0xcc);
209684 + virt = ioremap_nocache(start_addr, 0x1000);
209686 + writel_relaxed(0xe51ff004, virt);
209696 + unsigned int remap_reg_value = 0;
209700 + hi3556av100_set_boot_addr(0x04200000, jumpaddr);
209704 + return 0;
209720 @@ -0,0 +1,67 @@
209746 +#define REG_CPU_SRST_CRG 0x78
209762 + crg_base = of_iomap(np, 0);
209793 @@ -0,0 +1,67 @@
209819 +#define REG_CPU_SRST_CRG 0x78
209835 + crg_base = of_iomap(np, 0);
209866 @@ -0,0 +1,62 @@
209883 +#define HI35XX_BOOT_ADDRESS 0x00000000
209887 + unsigned long base = 0;
209913 + writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */
209926 + return 0;
209979 @@ -0,0 +1,7 @@
209992 @@ -0,0 +1,1187 @@
210024 +#define PLL_TEST_NR 0xffffffff
210027 +#define PINMUX_BASE_PHYS0 0x4058000
210028 +#define PINMUX_BASE_PHYS1 0x47b8000
210029 +#define PINMUX_BASE_PHYS2 0x47e0000
210030 +#define PINMUX_BASE_PHYS3 0x47e8000
210032 +#define THE_CRG_BASE 0x4510000
210033 +#define PERI_CRG_PLL7 0x1c
210034 +#define PERI_CRG58 0xe8
210035 +#define PERI_CRG91 0x16C
210036 +#define PERI_CRG102 0x198
210037 +#define PERI_CRG105 0x1a4
210041 +#define MISC_REG_BASE 0x4528000
210042 +#define MISC_CTRL73 0x124
210043 +#define MISC_CTRL74 0x128
210044 +#define MISC_CTRL75 0x12c
210045 +#define MISC_CTRL76 0x130
210046 +#define MISC_CTRL77 0x134
210047 +#define MISC_CTRL78 0x138
210048 +#define MISC_CTRL79 0x13c
210049 +#define MISC_CTRL80 0x140
210051 +#define SVB_CTRL_BASE 0x4528000
210052 +#define SVB_SYS_VOLTAGE_OFFSET 0x60
210054 +#define UART0_REG_PHYS 0x4540000
210055 +#define UART1_REG_PHYS 0x4541000
210056 +#define UART2_REG_PHYS 0x4542000
210057 +#define UART3_REG_PHYS 0x4543000
210058 +#define UART4_REG_PHYS 0x4544000
210059 +#define UART5_REG_PHYS 0x4545000
210060 +#define UART6_REG_PHYS 0x4546000
210061 +#define UART7_REG_PHYS 0x4547000
210062 +#define UART8_REG_PHYS 0x4548000
210064 +#define UART_DR 0x0
210065 +#define UART_CR 0x30
210067 +#define SPI0_REG_PHYS 0x4570000
210068 +#define SPI1_REG_PHYS 0x4571000
210069 +#define SPI2_REG_PHYS 0x4572000
210070 +#define SPI3_REG_PHYS 0x4573000
210071 +#define SPI4_REG_PHYS 0x4574000
210073 +#define HIEDMA0_REG_BASE 0x04040000
210074 +#define INT_TC1 0x4
210075 +#define INT_TC1_RAW 0x600
210077 +#define DMA_CHNL0_DONE (1<<0)
210105 + .pins[0] = {0x047B8000, 0x30, 0x1, 0x0, 0},
210106 + .pins[1] = {0x047B8000, 0x34, 0x1, 0x0, 0},
210107 + .pins[2] = {0x047B8000, 0x38, 0x1, 0x0, 0},
210108 + .pins[3] = {0x047B8000, 0x3c, 0x1, 0x0, 0},
210113 + .pins[0] = {0x047B8000, 0x40, 0x1, 0x0, 0},
210114 + .pins[1] = {0x047B8000, 0x44, 0x1, 0x0, 0},
210119 + .pins[0] = {0x047e8000, 0x00, 0x1, 0x0, 0},
210120 + .pins[1] = {0x047e8000, 0x04, 0x1, 0x0, 0},
210121 + .pins[2] = {0x047e8000, 0x08, 0x1, 0x0, 0},
210122 + .pins[3] = {0x047e8000, 0x0c, 0x1, 0x0, 0},
210123 + .pins[4] = {0x047e0000, 0x00, 0x1, 0x0, 0},
210124 + .pins[5] = {0x047e0000, 0x04, 0x1, 0x0, 0},
210125 + .pins[6] = {0x047e0000, 0x08, 0x1, 0x0, 0},
210126 + .pins[7] = {0x047e0000, 0x0c, 0x1, 0x0, 0},
210127 + .pins[8] = {0x047e0000, 0x34, 0x4, 0x0, 0},
210128 + .pins[9] = {0x047e0000, 0x38, 0x4, 0x0, 0},
210129 + .pins[10] = {0x047e0000, 0x3c, 0x4, 0x0, 0},
210130 + .pins[11] = {0x047e0000, 0x40, 0x4, 0x0, 0},
210135 + .pins[0] = {0x047B8000, 0x38, 0x2, 0x0, 0},
210136 + .pins[1] = {0x047B8000, 0x3c, 0x2, 0x0, 0},
210141 + .pins[0] = {0x047e8000, 0x10, 0x1, 0x0, 0},
210142 + .pins[1] = {0x047e8000, 0x14, 0x1, 0x0, 0},
210143 + .pins[2] = {0x047e0000, 0x10, 0x1, 0x0, 0},
210144 + .pins[3] = {0x047e0000, 0x14, 0x1, 0x0, 0},
210145 + .pins[4] = {0x047e0000, 0x24, 0x6, 0x0, 0},
210146 + .pins[5] = {0x047e0000, 0x28, 0x6, 0x0, 0},
210151 + .pins[0] = {0x047e8000, 0x08, 0x2, 0x0, 0},
210152 + .pins[1] = {0x047e8000, 0x0c, 0x2, 0x0, 0},
210153 + .pins[2] = {0x047e0000, 0x08, 0x2, 0x0, 0},
210154 + .pins[3] = {0x047e0000, 0x0c, 0x2, 0x0, 0},
210155 + .pins[4] = {0x047e0000, 0x18, 0x1, 0x0, 0},
210156 + .pins[5] = {0x047e0000, 0x1c, 0x1, 0x0, 0},
210157 + .pins[6] = {0x047e8000, 0x18, 0x1, 0x0, 0},
210158 + .pins[7] = {0x047e8000, 0x1c, 0x1, 0x0, 0},
210159 + .pins[8] = {0x047e0000, 0x2c, 0x6, 0x0, 0},
210160 + .pins[9] = {0x047e0000, 0x30, 0x6, 0x0, 0},
210161 + .pins[10] = {0x047e0000, 0x3c, 0x6, 0x0, 0},
210162 + .pins[11] = {0x047e0000, 0x40, 0x6, 0x0, 0},
210167 + .pins[0] = {0x04058000, 0x30, 0x3, 0x0, 0},
210168 + .pins[1] = {0x04058000, 0x34, 0x3, 0x0, 0},
210169 + .pins[2] = {0x04058000, 0x38, 0x3, 0x0, 0},
210170 + .pins[3] = {0x04058000, 0x3c, 0x3, 0x0, 0},
210175 + .pins[0] = {0x04058000, 0x40, 0x3, 0x0, 0},
210176 + .pins[1] = {0x04058000, 0x44, 0x3, 0x0, 0},
210177 + .pins[2] = {0x04058000, 0x48, 0x3, 0x0, 0},
210178 + .pins[3] = {0x04058000, 0x4c, 0x3, 0x0, 0},
210183 + .pins[0] = {0x04058000, 0x54, 0x1, 0x0, 0},
210184 + .pins[1] = {0x04058000, 0x58, 0x1, 0x0, 0},
210185 + .pins[2] = {0x04058000, 0x5c, 0x1, 0x0, 0},
210186 + .pins[3] = {0x04058000, 0x60, 0x1, 0x0, 0},
210191 + .pins[0] = {0x04058000, 0x64, 0x1, 0x0, 0},
210192 + .pins[1] = {0x04058000, 0x68, 0x1, 0x0, 0},
210193 + .pins[2] = {0x04058000, 0x6c, 0x1, 0x0, 0},
210194 + .pins[3] = {0x04058000, 0x70, 0x1, 0x0, 0},
210199 + .pins[0] = {0x04058000, 0xc4, 0x1, 0x0, 0},
210200 + .pins[1] = {0x04058000, 0xc8, 0x1, 0x0, 0},
210201 + .pins[2] = {0x04058000, 0xcc, 0x1, 0x0, 0},
210202 + .pins[3] = {0x04058000, 0xd0, 0x1, 0x0, 0},
210207 + .pins[0] = {0x047e0000, 0x24, 0x2, 0x0, 0},
210208 + .pins[1] = {0x047e0000, 0x28, 0x2, 0x0, 0},
210209 + .pins[2] = {0x047e0000, 0x2c, 0x2, 0x0, 0},
210210 + .pins[3] = {0x047e0000, 0x30, 0x2, 0x0, 0},
210211 + .pins[4] = {0x047e0000, 0x38, 0x3, 0x0, 0},
210212 + .pins[5] = {0x047e0000, 0x44, 0x3, 0x0, 0},
210213 + .pins[6] = {0x047e0000, 0x5c, 0x3, 0x0, 0},
210214 + .pins[7] = {0x047e0000, 0x60, 0x3, 0x0, 0},
210215 + .pins[8] = {0x047e0000, 0x44, 0x4, 0x0, 0},
210216 + .pins[9] = {0x047e0000, 0x48, 0x4, 0x0, 0},
210217 + .pins[10] = {0x047e0000, 0x4c, 0x4, 0x0, 0},
210218 + .pins[11] = {0x047e0000, 0x50, 0x4, 0x0, 0},
210223 + .pins[0] = {0x04058000, 0x7c, 0x2, 0x0, 0},
210224 + .pins[1] = {0x04058000, 0x80, 0x2, 0x0, 0},
210225 + .pins[2] = {0x04058000, 0x84, 0x2, 0x0, 0},
210226 + .pins[3] = {0x04058000, 0x88, 0x2, 0x0, 0},
210233 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
210237 + if ((val & 0xf) == pin->pinmx_func_num) {
210239 + val &= 0xfffffff0; // set as gpio
210243 + pin->pinmx_func_changed = 0;
210252 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
210264 + for (i = 0; i < pmx_ctrl_nr; i++) {
210272 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
210286 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
210298 + for (i = 0; i < pmx_ctrl_nr; i++) {
210342 + val = old & 0xffffffe6;
210361 + if (select == 0) {
210427 + writel(0x0, edma0_reg_base + 0x688);
210428 + writel(0xff, edma0_reg_base + 0x600);
210429 + writel(0xff, edma0_reg_base + 0x608);
210430 + writel(0xff, edma0_reg_base + 0x610);
210431 + writel(0xff, edma0_reg_base + 0x618);
210432 + writel(0xff, edma0_reg_base + 0x620);
210433 + writel(0x0, edma0_reg_base + 0x18);
210434 + writel(0x0, edma0_reg_base + 0x1c);
210435 + writel(0x0, edma0_reg_base + 0x20);
210436 + writel(0x0, edma0_reg_base + 0x24);
210437 + writel(0x0, edma0_reg_base + 0x28);
210438 + writel(0x0, edma0_reg_base + 0x830);
210439 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x820); // dma src address
210440 + writel(0, edma0_reg_base + 0x824);
210441 + writel(dma_phys + 0x800, edma0_reg_base + 0x828); // dma dest address
210442 + writel(0, edma0_reg_base + 0x82c);
210443 + writel(0x20, edma0_reg_base + 0x81c); // len
210445 + writel(0x0, edma0_reg_base + 0x870);
210446 + writel(dma_phys, edma0_reg_base + 0x860); // dma src address
210447 + writel(0, edma0_reg_base + 0x864);
210448 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x868); // dma dest address
210449 + writel(0, edma0_reg_base + 0x86c);
210450 + writel(0x20, edma0_reg_base + 0x85c); // len
210453 + writel(0x7ff, dev->ctrlreg_base + 0x44);
210454 + writel(0x1, dev->ctrlreg_base + 0x24);
210455 + writel(0x0, dev->ctrlreg_base + 0x28);
210456 + writel(0x70, dev->ctrlreg_base + 0x2c);
210457 + writel(0x0, dev->ctrlreg_base + 0x34);
210458 + writel(0x40, dev->ctrlreg_base + 0x38);
210459 + writel(0x3, dev->ctrlreg_base + 0x48);
210461 + writel(0x381, dev->ctrlreg_base + 0x30);
210489 + val = 0x30303030;
210494 + val &= ~(0xffff << shift);
210500 + val &= ~(0xffff << shift);
210507 + for (i = 0; i < 1; i++) {
210511 + writel(0x47700005 + (req_line << 5) + 16, edma0_reg_base + 0x830);
210512 + writel(0x87700005 + (req_line << 5), edma0_reg_base + 0x870);
210514 + writel(0x47700005 + (req_line << 5), edma0_reg_base + 0x830);
210515 + writel(0x87700005 + (req_line << 5) + 16, edma0_reg_base + 0x870);
210518 + for (j = 0; j < 1000; j++) {
210521 + ret = 0;
210522 + writel(0x3, edma0_reg_base + INT_TC1_RAW);
210529 + pr_debug("DMA time out[0x%x]!\n", val);
210533 + return 0;
210539 + int ret = 0;
210540 + for (i = 0; i < 16; i++) {
210545 + ret = do_uart_dma_rx_tst(dev, i, 0);
210548 + pr_debug("dma[req line=%d] revert = %d, rx tst failed", i, 0);
210570 + for (i = 0; i < dev_nr; i++) {
210575 + pass = 0;
210584 + pass = 0;
210604 + writel(0x0, edma0_reg_base + 0x688);
210605 + writel(0xff, edma0_reg_base + 0x600);
210606 + writel(0xff, edma0_reg_base + 0x608);
210607 + writel(0xff, edma0_reg_base + 0x610);
210608 + writel(0xff, edma0_reg_base + 0x618);
210609 + writel(0xff, edma0_reg_base + 0x620);
210610 + writel(0x0, edma0_reg_base + 0x18);
210611 + writel(0x0, edma0_reg_base + 0x1c);
210612 + writel(0x0, edma0_reg_base + 0x20);
210613 + writel(0x0, edma0_reg_base + 0x24);
210614 + writel(0x0, edma0_reg_base + 0x28);
210617 + writel(0x0, edma0_reg_base + 0x830);
210618 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x820); // dma src address
210619 + writel(0, edma0_reg_base + 0x824);
210620 + writel(dma_phys + 0x800, edma0_reg_base + 0x828); // dma dest address
210621 + writel(0, edma0_reg_base + 0x82c);
210622 + writel(0x407, edma0_reg_base + 0x81c); // len
210625 + writel(0x0, edma0_reg_base + 0x870);
210626 + writel(dma_phys, edma0_reg_base + 0x860); // dma src address
210627 + writel(0, edma0_reg_base + 0x864);
210628 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x868); // dma dest address
210629 + writel(0, edma0_reg_base + 0x86c);
210630 + writel(0x407, edma0_reg_base + 0x85c); // len
210633 + writel(0x4, dev->ctrlreg_base + 0x10);
210634 + writel(0x1f, dev->ctrlreg_base);
210635 + writel(0x0, dev->ctrlreg_base + 0x14);
210636 + writel(0x2, dev->ctrlreg_base + 0x28);
210637 + writel(0x2, dev->ctrlreg_base + 0x2c);
210638 + writel(0x3, dev->ctrlreg_base + 0x24);
210661 + val = 0x30303030;
210666 + val &= ~(0xffff << shift);
210672 + val &= ~(0xffff << shift);
210677 + for (i = 0; i < 1; i++) {
210679 + writel(0x0, dev->ctrlreg_base + 0x4);
210681 + writel(0x47711005 + (req_line << 5) + 16, edma0_reg_base + 0x830);
210682 + writel(0x87711005 + (req_line << 5), edma0_reg_base + 0x870);
210684 + writel(0x47711005 + (req_line << 5), edma0_reg_base + 0x830);
210685 + writel(0x87711005 + (req_line << 5) + 16, edma0_reg_base + 0x870);
210687 + writel(0x3, dev->ctrlreg_base + 0x4);
210689 + for (j = 0; j < 1000; j++) {
210692 + ret = 0;
210693 + writel(0x3, edma0_reg_base + INT_TC1_RAW);
210700 + pr_debug("DMA time out[0x%x]!\n", val);
210704 + return 0;
210710 + int ret = 0;
210711 + for (i = 0; i < 16; i++) {
210716 + ret = do_spi_dma_rx_tst(dev, i, 0);
210719 + pr_debug("dma[req line=%d] revert = %d, rx tst failed", i, 0);
210740 + .tx_dma_reqline_val = 0x26,
210741 + .rx_dma_reqline_val = 0x27,
210752 + .tx_dma_reqline_val = 0x28,
210753 + .rx_dma_reqline_val = 0x29,
210764 + .tx_dma_reqline_val = 0x2a,
210765 + .rx_dma_reqline_val = 0x2b,
210776 + .tx_dma_reqline_val = 0x2c,
210777 + .rx_dma_reqline_val = 0x2d,
210788 + .tx_dma_reqline_val = 0x2e,
210789 + .rx_dma_reqline_val = 0x2f,
210803 + .tx_dma_reqline_val = 0x3c,
210804 + .rx_dma_reqline_val = 0x3d,
210815 + .tx_dma_reqline_val = 0x2,
210816 + .rx_dma_reqline_val = 0x3,
210828 + .tx_dma_reqline_val = 0x4,
210829 + .rx_dma_reqline_val = 0x5,
210840 + .tx_dma_reqline_val = 0x6,
210841 + .rx_dma_reqline_val = 0x7,
210852 + .tx_dma_reqline_val = 0x8,
210853 + .rx_dma_reqline_val = 0x9,
210864 + .tx_dma_reqline_val = 0xa,
210865 + .rx_dma_reqline_val = 0xb,
210876 + .tx_dma_reqline_val = 0xc,
210877 + .rx_dma_reqline_val = 0xd,
210889 + .tx_dma_reqline_val = 0x3e,
210890 + .rx_dma_reqline_val = 0x3f,
210904 + regulator->reg_virt = ioremap_nocache(regulator->reg_base, 0x1000);
210906 + regulator->curr = (val >> 16) & 0xff;
210908 + regulator->steps[0] = regulator->curr + 74;
210914 + regulator->steps[3] = 0;
210920 + regulator->steps[4] = 0;
210924 + regulator->steps[0] = 0xffffffff;
210925 + regulator->steps[1] = 0xffffffff;
210930 + regulator->steps[3] = 0xffffffff;
210931 + regulator->steps[4] = 0xffffffff;
210936 + regulator->steps[0] = 0xffffffff;
210942 + regulator->steps[0] = regulator->max;
210948 + regulator->steps[4] = 0xffffffff;
210963 + pr_debug("svb voltage min/max[0x%x/0x%x] steps: ",
210965 + for (i = 0; i < 5; i++) {
210966 + pr_debug(" 0x%x ", regulator->steps[i]);
210975 + if (regulator->steps[step] == 0xffffffff) {
210980 + val &= 0xff00ffff;
210982 + val |= (0x1 << 2);
210985 + return 0;
210991 + val &= 0xff00ffff;
210993 + val |= (0x1 << 2);
211003 + .min = 0,
211004 + .max = 0x19f,
211005 + .reg_base = 0x4528060,
211006 + .steps = {0},
211015 + int ret = 0, i, j;
211026 + crg_base = ioremap_nocache(THE_CRG_BASE, 0x1000);
211031 + misc_base = ioremap_nocache(MISC_REG_BASE, 0x1000);
211037 + edma0_reg_base = ioremap_nocache(HIEDMA0_REG_BASE, 0x1000);
211046 + writel(0x0, crg_base + PERI_CRG105);
211050 + dma_data = dma_alloc_coherent(NULL, 0x1000, &dma_phys, GFP_KERNEL);
211051 + memset(dma_data, 0x5e, 0x800);
211053 + for (i = 0; i < ssp_dev_nr; i++) {
211055 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
211058 + for (i = 0; i < dev_nr; i++) {
211060 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
211071 + for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
211072 + for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) &&
211097 + pll_reset(0);
211113 + for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
211114 + for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) &&
211154 + for (i = 0; i < ssp_dev_nr; i++) {
211159 + for (i = 0; i < dev_nr; i++) {
211167 + dma_free_coherent(NULL, 0x1000, dma_data, dma_phys);
211185 @@ -0,0 +1,7 @@
211198 @@ -0,0 +1,1179 @@
211230 +#define PLL_TEST_NR 0xffffffff
211233 +#define PINMUX_BASE_PHYS0 0x4058000
211234 +#define PINMUX_BASE_PHYS1 0x47b8000
211235 +#define PINMUX_BASE_PHYS2 0x47e0000
211236 +#define PINMUX_BASE_PHYS3 0x47e8000
211238 +#define THE_CRG_BASE 0x4510000
211239 +#define PERI_CRG_PLL7 0x1c
211240 +#define PERI_CRG58 0xe8
211241 +#define PERI_CRG91 0x16C
211242 +#define PERI_CRG102 0x198
211243 +#define PERI_CRG105 0x1a4
211247 +#define MISC_REG_BASE 0x4528000
211248 +#define MISC_CTRL73 0x124
211249 +#define MISC_CTRL74 0x128
211250 +#define MISC_CTRL75 0x12c
211251 +#define MISC_CTRL76 0x130
211252 +#define MISC_CTRL77 0x134
211253 +#define MISC_CTRL78 0x138
211254 +#define MISC_CTRL79 0x13c
211255 +#define MISC_CTRL80 0x140
211257 +#define SVB_CTRL_BASE 0x4528000
211258 +#define SVB_SYS_VOLTAGE_OFFSET 0x60
211260 +#define UART0_REG_PHYS 0x4540000
211261 +#define UART1_REG_PHYS 0x4541000
211262 +#define UART2_REG_PHYS 0x4542000
211263 +#define UART3_REG_PHYS 0x4543000
211264 +#define UART4_REG_PHYS 0x4544000
211265 +#define UART5_REG_PHYS 0x4545000
211266 +#define UART6_REG_PHYS 0x4546000
211267 +#define UART7_REG_PHYS 0x4547000
211268 +#define UART8_REG_PHYS 0x4548000
211270 +#define UART_DR 0x0
211271 +#define UART_CR 0x30
211273 +#define SPI0_REG_PHYS 0x4570000
211274 +#define SPI1_REG_PHYS 0x4571000
211275 +#define SPI2_REG_PHYS 0x4572000
211276 +#define SPI3_REG_PHYS 0x4573000
211277 +#define SPI4_REG_PHYS 0x4574000
211279 +#define HIEDMA0_REG_BASE 0x04040000
211280 +#define INT_TC1 0x4
211281 +#define INT_TC1_RAW 0x600
211283 +#define DMA_CHNL0_DONE (1<<0)
211311 + .pins[0] = {0x047B8000, 0x30, 0x1, 0x0, 0},
211312 + .pins[1] = {0x047B8000, 0x34, 0x1, 0x0, 0},
211313 + .pins[2] = {0x047B8000, 0x38, 0x1, 0x0, 0},
211314 + .pins[3] = {0x047B8000, 0x3c, 0x1, 0x0, 0},
211319 + .pins[0] = {0x047B8000, 0x40, 0x1, 0x0, 0},
211320 + .pins[1] = {0x047B8000, 0x44, 0x1, 0x0, 0},
211325 + .pins[0] = {0x047e8000, 0x00, 0x1, 0x0, 0},
211326 + .pins[1] = {0x047e8000, 0x04, 0x1, 0x0, 0},
211327 + .pins[2] = {0x047e8000, 0x08, 0x1, 0x0, 0},
211328 + .pins[3] = {0x047e8000, 0x0c, 0x1, 0x0, 0},
211329 + .pins[4] = {0x047e0000, 0x00, 0x1, 0x0, 0},
211330 + .pins[5] = {0x047e0000, 0x04, 0x1, 0x0, 0},
211331 + .pins[6] = {0x047e0000, 0x08, 0x1, 0x0, 0},
211332 + .pins[7] = {0x047e0000, 0x0c, 0x1, 0x0, 0},
211333 + .pins[8] = {0x047e0000, 0x34, 0x4, 0x0, 0},
211334 + .pins[9] = {0x047e0000, 0x38, 0x4, 0x0, 0},
211335 + .pins[10] = {0x047e0000, 0x3c, 0x4, 0x0, 0},
211336 + .pins[11] = {0x047e0000, 0x40, 0x4, 0x0, 0},
211341 + .pins[0] = {0x047B8000, 0x38, 0x2, 0x0, 0},
211342 + .pins[1] = {0x047B8000, 0x3c, 0x2, 0x0, 0},
211347 + .pins[0] = {0x047e8000, 0x10, 0x1, 0x0, 0},
211348 + .pins[1] = {0x047e8000, 0x14, 0x1, 0x0, 0},
211349 + .pins[2] = {0x047e0000, 0x10, 0x1, 0x0, 0},
211350 + .pins[3] = {0x047e0000, 0x14, 0x1, 0x0, 0},
211351 + .pins[4] = {0x047e0000, 0x24, 0x6, 0x0, 0},
211352 + .pins[5] = {0x047e0000, 0x28, 0x6, 0x0, 0},
211357 + .pins[0] = {0x047e8000, 0x08, 0x2, 0x0, 0},
211358 + .pins[1] = {0x047e8000, 0x0c, 0x2, 0x0, 0},
211359 + .pins[2] = {0x047e0000, 0x08, 0x2, 0x0, 0},
211360 + .pins[3] = {0x047e0000, 0x0c, 0x2, 0x0, 0},
211361 + .pins[4] = {0x047e0000, 0x18, 0x1, 0x0, 0},
211362 + .pins[5] = {0x047e0000, 0x1c, 0x1, 0x0, 0},
211363 + .pins[6] = {0x047e8000, 0x18, 0x1, 0x0, 0},
211364 + .pins[7] = {0x047e8000, 0x1c, 0x1, 0x0, 0},
211365 + .pins[8] = {0x047e0000, 0x2c, 0x6, 0x0, 0},
211366 + .pins[9] = {0x047e0000, 0x30, 0x6, 0x0, 0},
211367 + .pins[10] = {0x047e0000, 0x3c, 0x6, 0x0, 0},
211368 + .pins[11] = {0x047e0000, 0x40, 0x6, 0x0, 0},
211373 + .pins[0] = {0x04058000, 0x30, 0x3, 0x0, 0},
211374 + .pins[1] = {0x04058000, 0x34, 0x3, 0x0, 0},
211375 + .pins[2] = {0x04058000, 0x38, 0x3, 0x0, 0},
211376 + .pins[3] = {0x04058000, 0x3c, 0x3, 0x0, 0},
211381 + .pins[0] = {0x04058000, 0x40, 0x3, 0x0, 0},
211382 + .pins[1] = {0x04058000, 0x44, 0x3, 0x0, 0},
211383 + .pins[2] = {0x04058000, 0x48, 0x3, 0x0, 0},
211384 + .pins[3] = {0x04058000, 0x4c, 0x3, 0x0, 0},
211389 + .pins[0] = {0x04058000, 0x54, 0x1, 0x0, 0},
211390 + .pins[1] = {0x04058000, 0x58, 0x1, 0x0, 0},
211391 + .pins[2] = {0x04058000, 0x5c, 0x1, 0x0, 0},
211392 + .pins[3] = {0x04058000, 0x60, 0x1, 0x0, 0},
211397 + .pins[0] = {0x04058000, 0x64, 0x1, 0x0, 0},
211398 + .pins[1] = {0x04058000, 0x68, 0x1, 0x0, 0},
211399 + .pins[2] = {0x04058000, 0x6c, 0x1, 0x0, 0},
211400 + .pins[3] = {0x04058000, 0x70, 0x1, 0x0, 0},
211405 + .pins[0] = {0x04058000, 0xc4, 0x1, 0x0, 0},
211406 + .pins[1] = {0x04058000, 0xc8, 0x1, 0x0, 0},
211407 + .pins[2] = {0x04058000, 0xcc, 0x1, 0x0, 0},
211408 + .pins[3] = {0x04058000, 0xd0, 0x1, 0x0, 0},
211413 + .pins[0] = {0x047e0000, 0x24, 0x2, 0x0, 0},
211414 + .pins[1] = {0x047e0000, 0x28, 0x2, 0x0, 0},
211415 + .pins[2] = {0x047e0000, 0x2c, 0x2, 0x0, 0},
211416 + .pins[3] = {0x047e0000, 0x30, 0x2, 0x0, 0},
211417 + .pins[4] = {0x047e0000, 0x38, 0x3, 0x0, 0},
211418 + .pins[5] = {0x047e0000, 0x44, 0x3, 0x0, 0},
211419 + .pins[6] = {0x047e0000, 0x5c, 0x3, 0x0, 0},
211420 + .pins[7] = {0x047e0000, 0x60, 0x3, 0x0, 0},
211421 + .pins[8] = {0x047e0000, 0x44, 0x4, 0x0, 0},
211422 + .pins[9] = {0x047e0000, 0x48, 0x4, 0x0, 0},
211423 + .pins[10] = {0x047e0000, 0x4c, 0x4, 0x0, 0},
211424 + .pins[11] = {0x047e0000, 0x50, 0x4, 0x0, 0},
211429 + .pins[0] = {0x04058000, 0x7c, 0x2, 0x0, 0},
211430 + .pins[1] = {0x04058000, 0x80, 0x2, 0x0, 0},
211431 + .pins[2] = {0x04058000, 0x84, 0x2, 0x0, 0},
211432 + .pins[3] = {0x04058000, 0x88, 0x2, 0x0, 0},
211439 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
211443 + if ((val & 0xf) == pin->pinmx_func_num) {
211445 + val &= 0xfffffff0; // set as gpio
211449 + pin->pinmx_func_changed = 0;
211458 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
211470 + for (i = 0; i < pmx_ctrl_nr; i++) {
211478 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
211492 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
211504 + for (i = 0; i < pmx_ctrl_nr; i++) {
211548 + val = old & 0xffffffe6;
211567 + if (select == 0) {
211633 + writel(0x0, edma0_reg_base + 0x688);
211634 + writel(0xff, edma0_reg_base + 0x600);
211635 + writel(0xff, edma0_reg_base + 0x608);
211636 + writel(0xff, edma0_reg_base + 0x610);
211637 + writel(0xff, edma0_reg_base + 0x618);
211638 + writel(0xff, edma0_reg_base + 0x620);
211639 + writel(0x0, edma0_reg_base + 0x18);
211640 + writel(0x0, edma0_reg_base + 0x1c);
211641 + writel(0x0, edma0_reg_base + 0x20);
211642 + writel(0x0, edma0_reg_base + 0x24);
211643 + writel(0x0, edma0_reg_base + 0x28);
211644 + writel(0x0, edma0_reg_base + 0x830);
211645 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x820);
211646 + writel(0, edma0_reg_base + 0x824);
211647 + writel(dma_phys + 0x800, edma0_reg_base + 0x828);
211648 + writel(0, edma0_reg_base + 0x82c);
211649 + writel(0x20, edma0_reg_base + 0x81c);
211651 + writel(0x0, edma0_reg_base + 0x870);
211652 + writel(dma_phys, edma0_reg_base + 0x860);
211653 + writel(0, edma0_reg_base + 0x864);
211654 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x868);
211655 + writel(0, edma0_reg_base + 0x86c);
211656 + writel(0x20, edma0_reg_base + 0x85c);
211659 + writel(0x7ff, dev->ctrlreg_base + 0x44);
211660 + writel(0x1, dev->ctrlreg_base + 0x24);
211661 + writel(0x0, dev->ctrlreg_base + 0x28);
211662 + writel(0x70, dev->ctrlreg_base + 0x2c);
211663 + writel(0x0, dev->ctrlreg_base + 0x34);
211664 + writel(0x40, dev->ctrlreg_base + 0x38);
211665 + writel(0x3, dev->ctrlreg_base + 0x48);
211667 + writel(0x381, dev->ctrlreg_base + 0x30);
211695 + val = 0x30303030;
211700 + val &= ~(0xffff << shift);
211706 + val &= ~(0xffff << shift);
211713 + for (i = 0; i < 1; i++) {
211717 + writel(0x47700005 + (req_line << 5) + 16, edma0_reg_base + 0x830);
211718 + writel(0x87700005 + (req_line << 5), edma0_reg_base + 0x870);
211720 + writel(0x47700005 + (req_line << 5), edma0_reg_base + 0x830);
211721 + writel(0x87700005 + (req_line << 5) + 16, edma0_reg_base + 0x870);
211724 + for (j = 0; j < 1000; j++) {
211727 + ret = 0;
211728 + writel(0x3, edma0_reg_base + INT_TC1_RAW);
211735 + pr_debug("DMA time out[0x%x]!\n", val);
211739 + return 0;
211745 + int ret = 0;
211746 + for (i = 0; i < 16; i++) {
211751 + ret = do_uart_dma_rx_tst(dev, i, 0);
211754 + pr_debug("dma[req line=%d] revert = %d, rx tst failed", i, 0);
211776 + for (i = 0; i < dev_nr; i++) {
211781 + pass = 0;
211790 + pass = 0;
211810 + writel(0x0, edma0_reg_base + 0x688);
211811 + writel(0xff, edma0_reg_base + 0x600);
211812 + writel(0xff, edma0_reg_base + 0x608);
211813 + writel(0xff, edma0_reg_base + 0x610);
211814 + writel(0xff, edma0_reg_base + 0x618);
211815 + writel(0xff, edma0_reg_base + 0x620);
211816 + writel(0x0, edma0_reg_base + 0x18);
211817 + writel(0x0, edma0_reg_base + 0x1c);
211818 + writel(0x0, edma0_reg_base + 0x20);
211819 + writel(0x0, edma0_reg_base + 0x24);
211820 + writel(0x0, edma0_reg_base + 0x28);
211823 + writel(0x0, edma0_reg_base + 0x830);
211824 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x820);
211825 + writel(0, edma0_reg_base + 0x824);
211826 + writel(dma_phys + 0x800, edma0_reg_base + 0x828);
211827 + writel(0, edma0_reg_base + 0x82c);
211828 + writel(0x407, edma0_reg_base + 0x81c);
211831 + writel(0x0, edma0_reg_base + 0x870);
211832 + writel(dma_phys, edma0_reg_base + 0x860);
211833 + writel(0, edma0_reg_base + 0x864);
211834 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x868);
211835 + writel(0, edma0_reg_base + 0x86c);
211836 + writel(0x407, edma0_reg_base + 0x85c);
211839 + writel(0x4, dev->ctrlreg_base + 0x10);
211840 + writel(0x1f, dev->ctrlreg_base);
211841 + writel(0x0, dev->ctrlreg_base + 0x14);
211842 + writel(0x2, dev->ctrlreg_base + 0x28);
211843 + writel(0x2, dev->ctrlreg_base + 0x2c);
211844 + writel(0x3, dev->ctrlreg_base + 0x24);
211867 + val = 0x30303030;
211872 + val &= ~(0xffff << shift);
211878 + val &= ~(0xffff << shift);
211883 + for (i = 0; i < 1; i++) {
211885 + writel(0x0, dev->ctrlreg_base + 0x4);
211887 + writel(0x47711005 + (req_line << 5) + 16, edma0_reg_base + 0x830);
211888 + writel(0x87711005 + (req_line << 5), edma0_reg_base + 0x870);
211890 + writel(0x47711005 + (req_line << 5), edma0_reg_base + 0x830);
211891 + writel(0x87711005 + (req_line << 5) + 16, edma0_reg_base + 0x870);
211893 + writel(0x3, dev->ctrlreg_base + 0x4);
211895 + for (j = 0; j < 1000; j++) {
211898 + ret = 0;
211899 + writel(0x3, edma0_reg_base + INT_TC1_RAW);
211906 + pr_debug("DMA time out[0x%x]!\n", val);
211910 + return 0;
211916 + int ret = 0;
211917 + for (i = 0; i < 16; i++) {
211922 + ret = do_spi_dma_rx_tst(dev, i, 0);
211925 + pr_debug("dma[req line=%d] revert = %d, rx tst failed", i, 0);
211946 + .tx_dma_reqline_val = 0x26,
211947 + .rx_dma_reqline_val = 0x27,
211958 + .tx_dma_reqline_val = 0x28,
211959 + .rx_dma_reqline_val = 0x29,
211970 + .tx_dma_reqline_val = 0x2a,
211971 + .rx_dma_reqline_val = 0x2b,
211982 + .tx_dma_reqline_val = 0x2c,
211983 + .rx_dma_reqline_val = 0x2d,
211994 + .tx_dma_reqline_val = 0x2e,
211995 + .rx_dma_reqline_val = 0x2f,
212009 + .tx_dma_reqline_val = 0x3c,
212010 + .rx_dma_reqline_val = 0x3d,
212021 + .tx_dma_reqline_val = 0x2,
212022 + .rx_dma_reqline_val = 0x3,
212034 + .tx_dma_reqline_val = 0x4,
212035 + .rx_dma_reqline_val = 0x5,
212046 + .tx_dma_reqline_val = 0x6,
212047 + .rx_dma_reqline_val = 0x7,
212058 + .tx_dma_reqline_val = 0x8,
212059 + .rx_dma_reqline_val = 0x9,
212070 + .tx_dma_reqline_val = 0xa,
212071 + .rx_dma_reqline_val = 0xb,
212082 + .tx_dma_reqline_val = 0xc,
212083 + .rx_dma_reqline_val = 0xd,
212095 + .tx_dma_reqline_val = 0x3e,
212096 + .rx_dma_reqline_val = 0x3f,
212110 + regulator->reg_virt = ioremap_nocache(regulator->reg_base, 0x1000);
212112 + regulator->curr = (val >> 16) & 0xff;
212115 + regulator->steps[0] = regulator->curr + 37;
212117 + regulator->steps[0] = regulator->max;
212141 + regulator->steps[4] = 0xffffffff;
212145 + regulator->steps[3] = 0xffffffff;
212149 + regulator->steps[2] = 0xffffffff;
212152 + if (regulator->steps[0] <= regulator->steps[1]) {
212153 + regulator->steps[0] = 0xffffffff;
212161 + pr_warn("svb voltage min/max[0x%x/0x%x] steps: ",
212163 + for (i = 0; i < 5; i++) {
212164 + pr_warn(" 0x%x ", regulator->steps[i]);
212173 + if (regulator->steps[step] == 0xffffffff) {
212178 + val &= 0xff00ffff;
212180 + val |= (0x1 << 2);
212183 + return 0;
212189 + val &= 0xff00ffff;
212191 + val |= (0x1 << 2);
212201 + .min = 0,
212202 + .max = 0x19f,
212203 + .reg_base = 0x4528060,
212204 + .steps = {0},
212213 + int ret = 0, i, j;
212224 + crg_base = ioremap_nocache(THE_CRG_BASE, 0x1000);
212229 + misc_base = ioremap_nocache(MISC_REG_BASE, 0x1000);
212235 + edma0_reg_base = ioremap_nocache(HIEDMA0_REG_BASE, 0x1000);
212244 + writel(0x0, crg_base + PERI_CRG105);
212248 + dma_data = dma_alloc_coherent(NULL, 0x1000, &dma_phys, GFP_KERNEL);
212249 + memset(dma_data, 0x5e, 0x800);
212251 + for (i = 0; i < ssp_dev_nr; i++) {
212253 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
212256 + for (i = 0; i < dev_nr; i++) {
212258 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
212269 + for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
212270 + for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) &&
212295 + pll_reset(0);
212311 + for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
212312 + for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) &&
212352 + for (i = 0; i < ssp_dev_nr; i++) {
212357 + for (i = 0; i < dev_nr; i++) {
212365 + dma_free_coherent(NULL, 0x1000, dma_data, dma_phys);
212383 @@ -0,0 +1,7 @@
212396 @@ -0,0 +1,1187 @@
212428 +#define PLL_TEST_NR 0xffffffff
212431 +#define PINMUX_BASE_PHYS0 0x4058000
212432 +#define PINMUX_BASE_PHYS1 0x47b8000
212433 +#define PINMUX_BASE_PHYS2 0x47e0000
212434 +#define PINMUX_BASE_PHYS3 0x47e8000
212436 +#define THE_CRG_BASE 0x4510000
212437 +#define PERI_CRG_PLL7 0x1c
212438 +#define PERI_CRG58 0xe8
212439 +#define PERI_CRG91 0x16C
212440 +#define PERI_CRG102 0x198
212441 +#define PERI_CRG105 0x1a4
212445 +#define MISC_REG_BASE 0x4528000
212446 +#define MISC_CTRL73 0x124
212447 +#define MISC_CTRL74 0x128
212448 +#define MISC_CTRL75 0x12c
212449 +#define MISC_CTRL76 0x130
212450 +#define MISC_CTRL77 0x134
212451 +#define MISC_CTRL78 0x138
212452 +#define MISC_CTRL79 0x13c
212453 +#define MISC_CTRL80 0x140
212455 +#define SVB_CTRL_BASE 0x4528000
212456 +#define SVB_SYS_VOLTAGE_OFFSET 0x60
212458 +#define UART0_REG_PHYS 0x4540000
212459 +#define UART1_REG_PHYS 0x4541000
212460 +#define UART2_REG_PHYS 0x4542000
212461 +#define UART3_REG_PHYS 0x4543000
212462 +#define UART4_REG_PHYS 0x4544000
212463 +#define UART5_REG_PHYS 0x4545000
212464 +#define UART6_REG_PHYS 0x4546000
212465 +#define UART7_REG_PHYS 0x4547000
212466 +#define UART8_REG_PHYS 0x4548000
212468 +#define UART_DR 0x0
212469 +#define UART_CR 0x30
212471 +#define SPI0_REG_PHYS 0x4570000
212472 +#define SPI1_REG_PHYS 0x4571000
212473 +#define SPI2_REG_PHYS 0x4572000
212474 +#define SPI3_REG_PHYS 0x4573000
212475 +#define SPI4_REG_PHYS 0x4574000
212477 +#define HIEDMA0_REG_BASE 0x04040000
212478 +#define INT_TC1 0x4
212479 +#define INT_TC1_RAW 0x600
212481 +#define DMA_CHNL0_DONE (1<<0)
212509 + .pins[0] = {0x047B8000, 0x30, 0x1, 0x0, 0},
212510 + .pins[1] = {0x047B8000, 0x34, 0x1, 0x0, 0},
212511 + .pins[2] = {0x047B8000, 0x38, 0x1, 0x0, 0},
212512 + .pins[3] = {0x047B8000, 0x3c, 0x1, 0x0, 0},
212517 + .pins[0] = {0x047B8000, 0x40, 0x1, 0x0, 0},
212518 + .pins[1] = {0x047B8000, 0x44, 0x1, 0x0, 0},
212523 + .pins[0] = {0x047e8000, 0x00, 0x1, 0x0, 0},
212524 + .pins[1] = {0x047e8000, 0x04, 0x1, 0x0, 0},
212525 + .pins[2] = {0x047e8000, 0x08, 0x1, 0x0, 0},
212526 + .pins[3] = {0x047e8000, 0x0c, 0x1, 0x0, 0},
212527 + .pins[4] = {0x047e0000, 0x00, 0x1, 0x0, 0},
212528 + .pins[5] = {0x047e0000, 0x04, 0x1, 0x0, 0},
212529 + .pins[6] = {0x047e0000, 0x08, 0x1, 0x0, 0},
212530 + .pins[7] = {0x047e0000, 0x0c, 0x1, 0x0, 0},
212531 + .pins[8] = {0x047e0000, 0x34, 0x4, 0x0, 0},
212532 + .pins[9] = {0x047e0000, 0x38, 0x4, 0x0, 0},
212533 + .pins[10] = {0x047e0000, 0x3c, 0x4, 0x0, 0},
212534 + .pins[11] = {0x047e0000, 0x40, 0x4, 0x0, 0},
212539 + .pins[0] = {0x047B8000, 0x38, 0x2, 0x0, 0},
212540 + .pins[1] = {0x047B8000, 0x3c, 0x2, 0x0, 0},
212545 + .pins[0] = {0x047e8000, 0x10, 0x1, 0x0, 0},
212546 + .pins[1] = {0x047e8000, 0x14, 0x1, 0x0, 0},
212547 + .pins[2] = {0x047e0000, 0x10, 0x1, 0x0, 0},
212548 + .pins[3] = {0x047e0000, 0x14, 0x1, 0x0, 0},
212549 + .pins[4] = {0x047e0000, 0x24, 0x6, 0x0, 0},
212550 + .pins[5] = {0x047e0000, 0x28, 0x6, 0x0, 0},
212555 + .pins[0] = {0x047e8000, 0x08, 0x2, 0x0, 0},
212556 + .pins[1] = {0x047e8000, 0x0c, 0x2, 0x0, 0},
212557 + .pins[2] = {0x047e0000, 0x08, 0x2, 0x0, 0},
212558 + .pins[3] = {0x047e0000, 0x0c, 0x2, 0x0, 0},
212559 + .pins[4] = {0x047e0000, 0x18, 0x1, 0x0, 0},
212560 + .pins[5] = {0x047e0000, 0x1c, 0x1, 0x0, 0},
212561 + .pins[6] = {0x047e8000, 0x18, 0x1, 0x0, 0},
212562 + .pins[7] = {0x047e8000, 0x1c, 0x1, 0x0, 0},
212563 + .pins[8] = {0x047e0000, 0x2c, 0x6, 0x0, 0},
212564 + .pins[9] = {0x047e0000, 0x30, 0x6, 0x0, 0},
212565 + .pins[10] = {0x047e0000, 0x3c, 0x6, 0x0, 0},
212566 + .pins[11] = {0x047e0000, 0x40, 0x6, 0x0, 0},
212571 + .pins[0] = {0x04058000, 0x30, 0x3, 0x0, 0},
212572 + .pins[1] = {0x04058000, 0x34, 0x3, 0x0, 0},
212573 + .pins[2] = {0x04058000, 0x38, 0x3, 0x0, 0},
212574 + .pins[3] = {0x04058000, 0x3c, 0x3, 0x0, 0},
212579 + .pins[0] = {0x04058000, 0x40, 0x3, 0x0, 0},
212580 + .pins[1] = {0x04058000, 0x44, 0x3, 0x0, 0},
212581 + .pins[2] = {0x04058000, 0x48, 0x3, 0x0, 0},
212582 + .pins[3] = {0x04058000, 0x4c, 0x3, 0x0, 0},
212587 + .pins[0] = {0x04058000, 0x54, 0x1, 0x0, 0},
212588 + .pins[1] = {0x04058000, 0x58, 0x1, 0x0, 0},
212589 + .pins[2] = {0x04058000, 0x5c, 0x1, 0x0, 0},
212590 + .pins[3] = {0x04058000, 0x60, 0x1, 0x0, 0},
212595 + .pins[0] = {0x04058000, 0x64, 0x1, 0x0, 0},
212596 + .pins[1] = {0x04058000, 0x68, 0x1, 0x0, 0},
212597 + .pins[2] = {0x04058000, 0x6c, 0x1, 0x0, 0},
212598 + .pins[3] = {0x04058000, 0x70, 0x1, 0x0, 0},
212603 + .pins[0] = {0x04058000, 0xc4, 0x1, 0x0, 0},
212604 + .pins[1] = {0x04058000, 0xc8, 0x1, 0x0, 0},
212605 + .pins[2] = {0x04058000, 0xcc, 0x1, 0x0, 0},
212606 + .pins[3] = {0x04058000, 0xd0, 0x1, 0x0, 0},
212611 + .pins[0] = {0x047e0000, 0x24, 0x2, 0x0, 0},
212612 + .pins[1] = {0x047e0000, 0x28, 0x2, 0x0, 0},
212613 + .pins[2] = {0x047e0000, 0x2c, 0x2, 0x0, 0},
212614 + .pins[3] = {0x047e0000, 0x30, 0x2, 0x0, 0},
212615 + .pins[4] = {0x047e0000, 0x38, 0x3, 0x0, 0},
212616 + .pins[5] = {0x047e0000, 0x44, 0x3, 0x0, 0},
212617 + .pins[6] = {0x047e0000, 0x5c, 0x3, 0x0, 0},
212618 + .pins[7] = {0x047e0000, 0x60, 0x3, 0x0, 0},
212619 + .pins[8] = {0x047e0000, 0x44, 0x4, 0x0, 0},
212620 + .pins[9] = {0x047e0000, 0x48, 0x4, 0x0, 0},
212621 + .pins[10] = {0x047e0000, 0x4c, 0x4, 0x0, 0},
212622 + .pins[11] = {0x047e0000, 0x50, 0x4, 0x0, 0},
212627 + .pins[0] = {0x04058000, 0x7c, 0x2, 0x0, 0},
212628 + .pins[1] = {0x04058000, 0x80, 0x2, 0x0, 0},
212629 + .pins[2] = {0x04058000, 0x84, 0x2, 0x0, 0},
212630 + .pins[3] = {0x04058000, 0x88, 0x2, 0x0, 0},
212637 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
212641 + if ((val & 0xf) == pin->pinmx_func_num) {
212643 + val &= 0xfffffff0; // set as gpio
212647 + pin->pinmx_func_changed = 0;
212656 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
212668 + for (i = 0; i < pmx_ctrl_nr; i++) {
212676 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
212690 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
212702 + for (i = 0; i < pmx_ctrl_nr; i++) {
212746 + val = old & 0xffffffe6;
212765 + if (select == 0) {
212831 + writel(0x0, edma0_reg_base + 0x688);
212832 + writel(0xff, edma0_reg_base + 0x600);
212833 + writel(0xff, edma0_reg_base + 0x608);
212834 + writel(0xff, edma0_reg_base + 0x610);
212835 + writel(0xff, edma0_reg_base + 0x618);
212836 + writel(0xff, edma0_reg_base + 0x620);
212837 + writel(0x0, edma0_reg_base + 0x18);
212838 + writel(0x0, edma0_reg_base + 0x1c);
212839 + writel(0x0, edma0_reg_base + 0x20);
212840 + writel(0x0, edma0_reg_base + 0x24);
212841 + writel(0x0, edma0_reg_base + 0x28);
212842 + writel(0x0, edma0_reg_base + 0x830);
212843 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x820);
212844 + writel(0, edma0_reg_base + 0x824);
212845 + writel(dma_phys + 0x800, edma0_reg_base + 0x828);
212846 + writel(0, edma0_reg_base + 0x82c);
212847 + writel(0x20, edma0_reg_base + 0x81c);
212849 + writel(0x0, edma0_reg_base + 0x870);
212850 + writel(dma_phys, edma0_reg_base + 0x860);
212851 + writel(0, edma0_reg_base + 0x864);
212852 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x868);
212853 + writel(0, edma0_reg_base + 0x86c);
212854 + writel(0x20, edma0_reg_base + 0x85c);
212857 + writel(0x7ff, dev->ctrlreg_base + 0x44);
212858 + writel(0x1, dev->ctrlreg_base + 0x24);
212859 + writel(0x0, dev->ctrlreg_base + 0x28);
212860 + writel(0x70, dev->ctrlreg_base + 0x2c);
212861 + writel(0x0, dev->ctrlreg_base + 0x34);
212862 + writel(0x40, dev->ctrlreg_base + 0x38);
212863 + writel(0x3, dev->ctrlreg_base + 0x48);
212865 + writel(0x381, dev->ctrlreg_base + 0x30);
212893 + val = 0x30303030;
212898 + val &= ~(0xffff << shift);
212904 + val &= ~(0xffff << shift);
212911 + for (i = 0; i < 1; i++) {
212915 + writel(0x47700005 + (req_line << 5) + 16, edma0_reg_base + 0x830);
212916 + writel(0x87700005 + (req_line << 5), edma0_reg_base + 0x870);
212918 + writel(0x47700005 + (req_line << 5), edma0_reg_base + 0x830);
212919 + writel(0x87700005 + (req_line << 5) + 16, edma0_reg_base + 0x870);
212922 + for (j = 0; j < 1000; j++) {
212925 + ret = 0;
212926 + writel(0x3, edma0_reg_base + INT_TC1_RAW);
212933 + pr_debug("DMA time out[0x%x]!\n", val);
212937 + return 0;
212943 + int ret = 0;
212944 + for (i = 0; i < 16; i++) {
212949 + ret = do_uart_dma_rx_tst(dev, i, 0);
212952 + pr_debug("dma[req line=%d] revert = %d, rx tst failed", i, 0);
212974 + for (i = 0; i < dev_nr; i++) {
212979 + pass = 0;
212988 + pass = 0;
213008 + writel(0x0, edma0_reg_base + 0x688);
213009 + writel(0xff, edma0_reg_base + 0x600);
213010 + writel(0xff, edma0_reg_base + 0x608);
213011 + writel(0xff, edma0_reg_base + 0x610);
213012 + writel(0xff, edma0_reg_base + 0x618);
213013 + writel(0xff, edma0_reg_base + 0x620);
213014 + writel(0x0, edma0_reg_base + 0x18);
213015 + writel(0x0, edma0_reg_base + 0x1c);
213016 + writel(0x0, edma0_reg_base + 0x20);
213017 + writel(0x0, edma0_reg_base + 0x24);
213018 + writel(0x0, edma0_reg_base + 0x28);
213021 + writel(0x0, edma0_reg_base + 0x830);
213022 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x820);
213023 + writel(0, edma0_reg_base + 0x824);
213024 + writel(dma_phys + 0x800, edma0_reg_base + 0x828);
213025 + writel(0, edma0_reg_base + 0x82c);
213026 + writel(0x407, edma0_reg_base + 0x81c);
213029 + writel(0x0, edma0_reg_base + 0x870);
213030 + writel(dma_phys, edma0_reg_base + 0x860);
213031 + writel(0, edma0_reg_base + 0x864);
213032 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x868);
213033 + writel(0, edma0_reg_base + 0x86c);
213034 + writel(0x407, edma0_reg_base + 0x85c);
213037 + writel(0x4, dev->ctrlreg_base + 0x10);
213038 + writel(0x1f, dev->ctrlreg_base);
213039 + writel(0x0, dev->ctrlreg_base + 0x14);
213040 + writel(0x2, dev->ctrlreg_base + 0x28);
213041 + writel(0x2, dev->ctrlreg_base + 0x2c);
213042 + writel(0x3, dev->ctrlreg_base + 0x24);
213065 + val = 0x30303030;
213070 + val &= ~(0xffff << shift);
213076 + val &= ~(0xffff << shift);
213081 + for (i = 0; i < 1; i++) {
213083 + writel(0x0, dev->ctrlreg_base + 0x4);
213085 + writel(0x47711005 + (req_line << 5) + 16, edma0_reg_base + 0x830);
213086 + writel(0x87711005 + (req_line << 5), edma0_reg_base + 0x870);
213088 + writel(0x47711005 + (req_line << 5), edma0_reg_base + 0x830);
213089 + writel(0x87711005 + (req_line << 5) + 16, edma0_reg_base + 0x870);
213091 + writel(0x3, dev->ctrlreg_base + 0x4);
213093 + for (j = 0; j < 1000; j++) {
213096 + ret = 0;
213097 + writel(0x3, edma0_reg_base + INT_TC1_RAW);
213104 + pr_debug("DMA time out[0x%x]!\n", val);
213108 + return 0;
213114 + int ret = 0;
213115 + for (i = 0; i < 16; i++) {
213120 + ret = do_spi_dma_rx_tst(dev, i, 0);
213123 + pr_debug("dma[req line=%d] revert = %d, rx tst failed", i, 0);
213144 + .tx_dma_reqline_val = 0x26,
213145 + .rx_dma_reqline_val = 0x27,
213156 + .tx_dma_reqline_val = 0x28,
213157 + .rx_dma_reqline_val = 0x29,
213168 + .tx_dma_reqline_val = 0x2a,
213169 + .rx_dma_reqline_val = 0x2b,
213180 + .tx_dma_reqline_val = 0x2c,
213181 + .rx_dma_reqline_val = 0x2d,
213192 + .tx_dma_reqline_val = 0x2e,
213193 + .rx_dma_reqline_val = 0x2f,
213207 + .tx_dma_reqline_val = 0x3c,
213208 + .rx_dma_reqline_val = 0x3d,
213219 + .tx_dma_reqline_val = 0x2,
213220 + .rx_dma_reqline_val = 0x3,
213232 + .tx_dma_reqline_val = 0x4,
213233 + .rx_dma_reqline_val = 0x5,
213244 + .tx_dma_reqline_val = 0x6,
213245 + .rx_dma_reqline_val = 0x7,
213256 + .tx_dma_reqline_val = 0x8,
213257 + .rx_dma_reqline_val = 0x9,
213268 + .tx_dma_reqline_val = 0xa,
213269 + .rx_dma_reqline_val = 0xb,
213280 + .tx_dma_reqline_val = 0xc,
213281 + .rx_dma_reqline_val = 0xd,
213293 + .tx_dma_reqline_val = 0x3e,
213294 + .rx_dma_reqline_val = 0x3f,
213308 + regulator->reg_virt = ioremap_nocache(regulator->reg_base, 0x1000);
213310 + regulator->curr = (val >> 16) & 0xff;
213312 + regulator->steps[0] = regulator->curr + 74;
213318 + regulator->steps[3] = 0;
213324 + regulator->steps[4] = 0;
213328 + regulator->steps[0] = 0xffffffff;
213329 + regulator->steps[1] = 0xffffffff;
213334 + regulator->steps[3] = 0xffffffff;
213335 + regulator->steps[4] = 0xffffffff;
213340 + regulator->steps[0] = 0xffffffff;
213346 + regulator->steps[0] = regulator->max;
213352 + regulator->steps[4] = 0xffffffff;
213367 + pr_debug("svb voltage min/max[0x%x/0x%x] steps: ",
213369 + for (i = 0; i < 5; i++) {
213370 + pr_debug(" 0x%x ", regulator->steps[i]);
213379 + if (regulator->steps[step] == 0xffffffff) {
213384 + val &= 0xff00ffff;
213386 + val |= (0x1 << 2);
213389 + return 0;
213395 + val &= 0xff00ffff;
213397 + val |= (0x1 << 2);
213407 + .min = 0,
213408 + .max = 0x19f,
213409 + .reg_base = 0x4528060,
213410 + .steps = {0},
213419 + int ret = 0, i, j;
213430 + crg_base = ioremap_nocache(THE_CRG_BASE, 0x1000);
213435 + misc_base = ioremap_nocache(MISC_REG_BASE, 0x1000);
213441 + edma0_reg_base = ioremap_nocache(HIEDMA0_REG_BASE, 0x1000);
213450 + writel(0x0, crg_base + PERI_CRG105);
213454 + dma_data = dma_alloc_coherent(NULL, 0x1000, &dma_phys, GFP_KERNEL);
213455 + memset(dma_data, 0x5e, 0x800);
213457 + for (i = 0; i < ssp_dev_nr; i++) {
213459 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
213462 + for (i = 0; i < dev_nr; i++) {
213464 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
213475 + for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
213476 + for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) &&
213501 + pll_reset(0);
213517 + for (j = 0; (j < LOOP_COUNT) && (trainning_pass == 1); j++) {
213518 + for (i = 0; (i < ARRAY_SIZE(volt_regulator.steps)) &&
213558 + for (i = 0; i < ssp_dev_nr; i++) {
213563 + for (i = 0; i < dev_nr; i++) {
213571 + dma_free_coherent(NULL, 0x1000, dma_data, dma_phys);
213591 return 0;
213715 @@ -0,0 +1,338 @@
213737 +/memreserve/ 0x43000000 0x00200000;
213786 + bootargs = "earlycon=pl011,0x11040000 mem=512M console=ttyAMA0,115200 clk_ignore_unused root=/de…
213788 + linux,initrd-start = <0x60000040>;
213789 + linux,initrd-end = <0x61000000>;
213794 + #size-cells = <0>;
213796 + cpu@0 {
213799 + reg = <0x0 0x0>;
213807 + reg = <0x0 0x1>;
213815 + reg = <0x0 0x2>;
213822 + reg = <0x0 0x3>;
213829 + reg = <0x0 0x40000000 0x2 0x0>; /* system memory base */
213864 + spidev@0 {
213866 + reg = <0>;
213867 + pl022,interface = <0>;
213868 + pl022,com-mode = <0>;
213875 + pl022,interface = <0>;
213876 + pl022,com-mode = <0>;
213883 + pl022,interface = <0>;
213884 + pl022,com-mode = <0>;
213891 + pl022,interface = <0>;
213892 + pl022,com-mode = <0>;
214008 + reg = <0>;
214017 + reg = <0>;
214059 @@ -0,0 +1,918 @@
214091 + #address-cells = <0>;
214093 + reg = <0x0 0x12400000 0x0 0x10000>, /* gic distributor base */
214094 + <0x0 0x12440000 0x0 0x140000>; /* gic redistributor base */
214104 + interrupts = <GIC_PPI 23 0xf04>;
214113 + reg = <0x0 0x11010000 0x0 0x4490>;
214122 + ranges = <0x0 0x00000000 0x0 0xffffffff>;
214126 + #clock-cells = <0>;
214138 + interrupts = <GIC_PPI 13 0xf04>,
214139 + <GIC_PPI 14 0xf04>;
214146 + reg = <0x11040000 0x1000>;
214155 + reg = <0x11041000 0x1000>;
214166 + reg = <0x11042000 0x1000>;
214177 + reg = <0x11043000 0x1000>;
214188 + reg = <0x11044000 0x1000>;
214199 + reg = <0x11060000 0x1000>;
214202 + dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
214211 + reg = <0x11061000 0x1000>;
214223 + arm,primecell-periphid = <0x00800022>;
214224 + reg = <0x11070000 0x1000>, <0x1102401c 0x4>;
214229 + #size-cells = <0>;
214232 + hisi,spi_cs_mask_bit = <0x6>;
214240 + reg = <0x11090000 0x1000>;
214250 + reg = <0x11091000 0x1000>;
214260 + reg = <0x11092000 0x1000>;
214270 + reg = <0x11093000 0x1000>;
214280 + reg = <0x11094000 0x1000>;
214290 + reg = <0x11095000 0x1000>;
214300 + reg = <0x11096000 0x1000>;
214310 + reg = <0x11097000 0x1000>;
214320 + reg = <0x11098000 0x1000>;
214330 + reg = <0x11099000 0x1000>;
214340 + reg = <0x1109A000 0x1000>;
214350 + reg = <0x1109B000 0x1000>;
214360 + reg = <0x1109C000 0x1000>;
214370 + reg = <0x1109D000 0x1000>;
214380 + reg = <0x1109E000 0x1000>;
214390 + reg = <0x1109F000 0x1000>;
214400 + reg = <0x110A0000 0x1000>;
214410 + reg = <0x110A1000 0x1000>;
214420 + reg = <0x110A2000 0x1000>;
214430 + reg = <0x110A3000 0x1000>;
214440 + reg = <0x110A4000 0x1000>;
214450 + reg = <0x110A5000 0x1000>;
214460 + reg = <0x110A6000 0x1000>;
214470 + reg = <0x110A7000 0x1000>;
214480 + reg = <0x110A8000 0x1000>;
214490 + reg = <0x110A9000 0x1000>;
214500 + reg = <0x11110000 0x10000>;
214509 + reg = <0x11024000 0x5000>;
214514 + reg = <0x10ff0000 0x10000>;
214520 + reg = <0x10000000 0x1000>, <0x0f000000 0x1000000>;
214523 + max-dma-size = <0x2000>;
214525 + #size-cells = <0>;
214532 + #size-cells = <0>;
214540 + #size-cells = <0>;
214547 + reg = <0x102903c0 0x20>;
214549 + resets = <&clock 0x37cc 0>;
214553 + #size-cells = <0>;
214558 + reg = <0x102a03c0 0x20>;
214560 + resets = <&clock 0x380c 0>;
214564 + #size-cells = <0>;
214569 + reg = <0x10290000 0x1000>,<0x1029300c 0x4>;
214580 + resets = <&clock 0x37c4 0>,
214581 + <&clock 0x37c0 0>;
214590 + reg = <0x102a0000 0x1000>,<0x102a300c 0x4>;
214601 + resets = <&clock 0x3804 0>,
214602 + <&clock 0x3800 0>;
214611 + reg = <0x110138c0 0x180>, <0x11024188 0x44>, <0x11020444 0x4>;
214614 + xhci_0:xhci_0@0x10300000 {
214616 + reg = <0x10300000 0x10000>;
214621 + xhci_1:xhci_1@0x10340000 {
214623 + reg = <0x10340000 0x10000>;
214629 + mmc0: eMMC@0x10020000 {
214631 + reg = <0x10020000 0x1000>;
214635 + resets = <&clock 0x34c0 16>, <&clock 0x34c4 1>;
214650 + devid = <0>;
214654 + mmc1: SDIO@0x10200000 {
214656 + reg = <0x10020000 0x1000>;
214660 + resets = <&clock 0x34c0 16>, <&clock 0x34c4 1>;
214673 + pcie0: pcie0@0x103d0000 {
214679 + bus-range = <0x0 0xff>;
214680 + reg = <0x00 0x103d0000 0x00 0x2000>;
214681 + ranges = <0x02000000 0x00 0x28000000 0x28000000 0x00 0x8000000>;
214682 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
214683 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH
214684 + 0x0 0x0 0x0 0x2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
214685 + 0x0 0x0 0x0 0x3 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
214686 + 0x0 0x0 0x0 0x4 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
214691 + pcie_controller = <0>;
214692 + dev_mem_size = <0x8000000>;
214693 + dev_conf_size = <0x8000000>;
214694 + sys_ctrl_base = <0x11020000>;
214695 + pcie_dbi_base = <0x103d0000>;
214696 + ep_conf_base = <0x20000000>;
214697 + pcie_clk_rest_reg = <0x3a40>;
214701 + pcie1: pcie1@0x103e0000 {
214707 + bus-range = <0x0 0xff>;
214708 + reg = <0x00 0x103e0000 0x00 0x2000>;
214709 + ranges = <0x02000000 0x00 0x38000000 0x38000000 0x00 0x8000000>;
214710 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
214711 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH
214712 + 0x0 0x0 0x0 0x2 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH
214713 + 0x0 0x0 0x0 0x3 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH
214714 + 0x0 0x0 0x0 0x4 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
214721 + dev_mem_size = <0x8000000>;
214722 + dev_conf_size = <0x8000000>;
214723 + sys_ctrl_base = <0x11020000>;
214724 + pcie_dbi_base = <0x103e0000>;
214725 + ep_conf_base = <0x30000000>;
214726 + pcie_clk_rest_reg = <0x3a60>;
214730 + pcie_mcc: pcie_mcc@0x0 {
214737 + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* global soft irq */
214745 + sata_phy: phy@0x10390000 {
214747 + reg = <0x10390000 0x10000>;
214749 + #phy-cells = <0>;
214752 + ahci: sata@0x10390000 {
214754 + reg = <0x10390000 0x1000>;
214759 + #size-cells = <0>;
214764 + reg = <0x10280000 0x1000>;
214769 + resets = <&clock 0x2A80 0>;
214773 + devid = <0>;
214781 + reg = <0x10280000 0x1000>;
214786 + resets = <&clock 0x2A80 0>;
214790 + devid = <0>;
214798 + reg = <0x11014500 0xBB00>,
214799 + <0x11020000 0x4000>,
214800 + <0x11130000 0x10000>,
214801 + <0X11024000 0x5000>;
214805 + vi: vi@0x17400000 {
214807 + reg = <0x17400000 0x40000>,
214808 + <0x11003020 0x20>;
214816 + mipi: mipi@0x173c0000 {
214818 + reg = <0x173c0000 0x1000>, <0x173c1000 0xF000>;
214824 + vpss: vpss@0x17900000 {
214826 + reg = <0x17900000 0x10000>, <0x17910000 0x10000>, <0x17920000 0x10000>;
214834 + vgs: vgs@0x17240000 {
214836 + reg = <0x17240000 0x10000>;
214842 + vo: vo@0x17A00000 {
214844 + reg = <0x17A00000 0x40000>;
214850 + hifb: hifb@0x17A00000 {
214857 + hdmi: hdmi@0x17B40000 {
214859 + reg = <0x17B40000 0x20000>,<0x17BC0000 0x10000>;
214867 + venc: venc@0x17140000 {
214869 + reg = <0x17140000 0x10000>,<0x17150000 0x10000>,<0x17160000 0x10000>,<0x171c0000 0x10000>;
214878 + vdh: vdh@0x17100000 {
214880 + reg = <0x17100000 0x10000>;
214888 + jpegd: jpegd@0x17180000 {
214890 + reg = <0x17180000 0x10000>;
214895 + vda: vda@0x170c0000 {
214897 + reg = <0x170c0000 0x10000>;
214902 + nnie: nnie@0x170D0000 {
214904 + reg = <0x170D0000 0x10000>;
214910 + ive: ive@0x17000000 {
214912 + reg = <0x17000000 0x10000>;
214918 + mau: mau@0x170E0000 {
214920 + reg = <0x170E0000 0x10000>;
214928 + reg = <0x17c40000 0x10000>,<0x17c00000 0x10000>;
214935 + tde: tde@0x17280000 {
214937 + reg = <0x17280000 0x10000>;
214943 + cipher: cipher@0x10100000 {
214945 + reg = <0x10100000 0x10000>;
214954 + otp: otp@0x10200000 {
214956 + reg = <0x10200000 0x1000>;
214960 + ir: ir@0x110F0000 {
214962 + reg = <0x110F0000 0x10000>;
214968 + wdg: wdg@0x11030000 {
214970 + reg = <0x11030000 0x1000>;
214983 @@ -0,0 +1,334 @@
215005 +/memreserve/ 0x43000000 0x00200000;
215054 + bootargs = "earlycon=pl011,0x11040000 mem=512M console=ttyAMA0,115200 clk_ignore_unused root=/de…
215056 + linux,initrd-start = <0x60000040>;
215057 + linux,initrd-end = <0x61000000>;
215062 + #size-cells = <0>;
215064 + cpu@0 {
215067 + reg = <0x0 0x0>;
215075 + reg = <0x0 0x1>;
215083 + reg = <0x0 0x2>;
215090 + reg = <0x0 0x3>;
215097 + reg = <0x0 0x40000000 0x2 0x0>; /* system memory base */
215132 + spidev@0 {
215134 + reg = <0>;
215135 + pl022,interface = <0>;
215136 + pl022,com-mode = <0>;
215143 + pl022,interface = <0>;
215144 + pl022,com-mode = <0>;
215151 + pl022,interface = <0>;
215152 + pl022,com-mode = <0>;
215159 + pl022,interface = <0>;
215160 + pl022,com-mode = <0>;
215276 + reg = <0>;
215285 + reg = <0>;
215323 @@ -0,0 +1,856 @@
215354 + #address-cells = <0>;
215356 + reg = <0x0 0x12400000 0x0 0x10000>, /* gic distributor base */
215357 + <0x0 0x12440000 0x0 0x140000>; /* gic redistributor base */
215367 + interrupts = <GIC_PPI 23 0xf04>;
215376 + reg = <0x0 0x11010000 0x0 0x4490>;
215385 + ranges = <0x0 0x00000000 0x0 0xffffffff>;
215389 + #clock-cells = <0>;
215401 + interrupts = <GIC_PPI 13 0xf04>,
215402 + <GIC_PPI 14 0xf04>;
215409 + reg = <0x11040000 0x1000>;
215418 + reg = <0x11041000 0x1000>;
215429 + reg = <0x11042000 0x1000>;
215440 + reg = <0x11043000 0x1000>;
215451 + reg = <0x11044000 0x1000>;
215462 + reg = <0x11060000 0x1000>;
215470 + reg = <0x11061000 0x1000>;
215478 + arm,primecell-periphid = <0x00800022>;
215479 + reg = <0x11070000 0x1000>, <0x1102401c 0x4>;
215484 + #size-cells = <0>;
215487 + hisi,spi_cs_mask_bit = <0x6>;
215495 + reg = <0x11090000 0x1000>;
215505 + reg = <0x11091000 0x1000>;
215515 + reg = <0x11092000 0x1000>;
215525 + reg = <0x11093000 0x1000>;
215535 + reg = <0x11094000 0x1000>;
215545 + reg = <0x11095000 0x1000>;
215555 + reg = <0x11096000 0x1000>;
215565 + reg = <0x11097000 0x1000>;
215575 + reg = <0x11098000 0x1000>;
215585 + reg = <0x11099000 0x1000>;
215595 + reg = <0x1109A000 0x1000>;
215605 + reg = <0x1109B000 0x1000>;
215615 + reg = <0x1109C000 0x1000>;
215625 + reg = <0x1109D000 0x1000>;
215635 + reg = <0x1109E000 0x1000>;
215645 + reg = <0x1109F000 0x1000>;
215655 + reg = <0x110A0000 0x1000>;
215665 + reg = <0x110A1000 0x1000>;
215675 + reg = <0x110A2000 0x1000>;
215685 + reg = <0x110A3000 0x1000>;
215695 + reg = <0x110A4000 0x1000>;
215705 + reg = <0x110A5000 0x1000>;
215715 + reg = <0x110A6000 0x1000>;
215725 + reg = <0x110A7000 0x1000>;
215735 + reg = <0x110A8000 0x1000>;
215745 + reg = <0x110A9000 0x1000>;
215755 + reg = <0x11110000 0x10000>;
215764 + reg = <0x11024000 0x5000>;
215769 + reg = <0x10ff0000 0x10000>;
215775 + reg = <0x10000000 0x1000>, <0x0f000000 0x1000000>;
215778 + max-dma-size = <0x2000>;
215780 + #size-cells = <0>;
215787 + #size-cells = <0>;
215795 + #size-cells = <0>;
215802 + reg = <0x102903c0 0x20>;
215804 + resets = <&clock 0x37cc 0>;
215808 + #size-cells = <0>;
215813 + reg = <0x102a03c0 0x20>;
215815 + resets = <&clock 0x380c 0>;
215819 + #size-cells = <0>;
215824 + reg = <0x10290000 0x1000>,<0x1029300c 0x4>;
215835 + resets = <&clock 0x37c4 0>,
215836 + <&clock 0x37c0 0>;
215845 + reg = <0x102a0000 0x1000>,<0x102a300c 0x4>;
215856 + resets = <&clock 0x3804 0>,
215857 + <&clock 0x3800 0>;
215866 + reg = <0x110138c0 0x180>, <0x11024188 0x44>, <0x11020444 0x4>;
215869 + xhci_0:xhci_0@0x10300000 {
215871 + reg = <0x10300000 0x10000>;
215876 + xhci_1:xhci_1@0x10340000 {
215878 + reg = <0x10340000 0x10000>;
215884 + mmc0: eMMC@0x10020000 {
215886 + reg = <0x10020000 0x1000>;
215890 + resets = <&clock 0x34c0 16>, <&clock 0x34c4 1>;
215905 + devid = <0>;
215909 + mmc1: SDIO@0x10200000 {
215911 + reg = <0x10020000 0x1000>;
215915 + resets = <&clock 0x34c0 16>, <&clock 0x34c4 1>;
215928 + pcie0: pcie@0x103d0000 {
215934 + bus-range = <0x0 0xff>;
215935 + reg = <0x00 0x103d0000 0x00 0x2000>;
215936 + ranges = <0x02000000 0x00 0x28000000 0x28000000 0x00 0x8000000>;
215937 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
215938 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH
215939 + 0x0 0x0 0x0 0x2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
215940 + 0x0 0x0 0x0 0x3 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
215941 + 0x0 0x0 0x0 0x4 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
215946 + pcie_controller = <0>;
215947 + dev_mem_size = <0x8000000>;
215948 + dev_conf_size = <0x8000000>;
215949 + sys_ctrl_base = <0x11020000>;
215950 + pcie_dbi_base = <0x103d0000>;
215951 + ep_conf_base = <0x20000000>;
215952 + pcie_clk_rest_reg = <0x3a40>;
215957 + pcie_mcc: pcie_mcc@0x0 {
215964 + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; /* global soft irq */
215967 + sata_phy: phy@0x10390000 {
215969 + reg = <0x10390000 0x10000>;
215971 + #phy-cells = <0>;
215974 + ahci: sata@0x10390000 {
215976 + reg = <0x10390000 0x1000>;
215981 + #size-cells = <0>;
215986 + reg = <0x10280000 0x1000>;
215991 + resets = <&clock 0x2A80 0>;
215995 + devid = <0>;
216003 + reg = <0x11014500 0xBB00>,
216004 + <0x11020000 0x4000>,
216005 + <0x11130000 0x10000>,
216006 + <0X11024000 0x5000>;
216010 + vi: vi@0x17400000 {
216012 + reg = <0x17400000 0x40000>,
216013 + <0x11003020 0x20>;
216021 + mipi: mipi@0x173c0c00 {
216023 + reg = <0x173c0c00 0x200>,<0x173c1900 0x4fc>,<0x173c7000 0xffc>;
216029 + vpss: vpss@0x17910000 {
216031 + reg = <0x17910000 0x10000>, <0x17920000 0x10000>;
216038 + vgs: vgs@0x17240000 {
216040 + reg = <0x17240000 0x10000>;
216046 + vo: vo@0x17A00000 {
216048 + reg = <0x17A00000 0x40000>;
216054 + hifb: hifb@0x17A00000 {
216061 + hdmi: hdmi@0x17B40000 {
216063 + reg = <0x17B40000 0x20000>,<0x17BC0000 0x10000>;
216071 + venc: venc@0x17140000 {
216073 + reg = <0x17140000 0x10000>,<0x171c0000 0x10000>;
216080 + vdh: vdh@0x17100000 {
216082 + reg = <0x17100000 0x10000>;
216090 + jpegd: jpegd@0x17180000 {
216092 + reg = <0x17180000 0x10000>;
216097 + vda: vda@0x170c0000 {
216099 + reg = <0x170c0000 0x10000>;
216104 + nnie: nnie@0x170D0000 {
216106 + reg = <0x170D0000 0x10000>;
216112 + ive: ive@0x17000000 {
216114 + reg = <0x17000000 0x10000>;
216120 + mau: mau@0x170E0000 {
216122 + reg = <0x170E0000 0x10000>;
216130 + reg = <0x17c40000 0x10000>,<0x17c00000 0x10000>;
216137 + tde: tde@0x17280000 {
216139 + reg = <0x17280000 0x10000>;
216145 + cipher: cipher@0x10100000 {
216147 + reg = <0x10100000 0x10000>;
216156 + otp: otp@0x10200000 {
216158 + reg = <0x10200000 0x1000>;
216162 + ir: ir@0x110F0000 {
216164 + reg = <0x110F0000 0x10000>;
216170 + wdg: wdg@0x11030000 {
216172 + reg = <0x11030000 0x1000>;
216185 @@ -0,0 +1,596 @@
216207 +/memreserve/ 0x53000000 0x00200000;
216280 + linux,initrd-start = <0x60000040>;
216281 + linux,initrd-end = <0x61000000>;
216286 + #size-cells = <0>;
216288 + cpu@0 {
216291 + reg = <0x0 0x0>;
216299 + reg = <0x0 0x1>;
216306 + reg = <0x0 0x100>;
216313 + reg = <0x0 0x101>;
216322 + reg = <0x0 0x50000000 0x2 0x0>; /* system memory base */
216453 + spidev@0 {
216455 + reg = <0>;
216456 + pl022,interface = <0>;
216457 + pl022,com-mode = <0>;
216464 + pl022,interface = <0>;
216465 + pl022,com-mode = <0>;
216473 + spidev@0 {
216475 + reg = <0>;
216476 + pl022,interface = <0>;
216477 + pl022,com-mode = <0>;
216484 + pl022,interface = <0>;
216485 + pl022,com-mode = <0>;
216493 + spidev@0 {
216495 + reg = <0>;
216496 + pl022,interface = <0>;
216497 + pl022,com-mode = <0>;
216504 + pl022,interface = <0>;
216505 + pl022,com-mode = <0>;
216513 + spidev@0 {
216515 + reg = <0>;
216516 + pl022,interface = <0>;
216517 + pl022,com-mode = <0>;
216524 + pl022,interface = <0>;
216525 + pl022,com-mode = <0>;
216533 + spidev@0 {
216535 + reg = <0>;
216536 + pl022,interface = <0>;
216537 + pl022,com-mode = <0>;
216544 + pl022,interface = <0>;
216545 + pl022,com-mode = <0>;
216552 + pl022,interface = <0>;
216553 + pl022,com-mode = <0>;
216560 + pl022,interface = <0>;
216561 + pl022,com-mode = <0>;
216569 + spidev@0 {
216571 + reg = <0>;
216572 + pl022,interface = <0>;
216573 + pl022,com-mode = <0>;
216580 + pl022,interface = <0>;
216581 + pl022,com-mode = <0>;
216587 + pl022,interface = <0>;
216588 + pl022,com-mode = <0>;
216596 + spidev@0 {
216598 + reg = <0>;
216599 + pl022,interface = <0>;
216600 + pl022,com-mode = <0>;
216607 + pl022,interface = <0>;
216608 + pl022,com-mode = <0>;
216614 + pl022,interface = <0>;
216615 + pl022,com-mode = <0>;
216623 + spidev@0 {
216625 + reg = <0>;
216626 + pl022,interface = <0>;
216627 + pl022,com-mode = <0>;
216715 + reg = <0>;
216724 + reg = <0>;
216732 + reg = <0>;
216743 +#if 0
216756 +#if 0
216787 @@ -0,0 +1,32 @@
216825 @@ -0,0 +1,32 @@
216863 @@ -0,0 +1,32 @@
216901 @@ -0,0 +1,655 @@
216923 +/memreserve/ 0x47000000 0x00200000;
216996 + linux,initrd-start = <0x60000040>;
216997 + linux,initrd-end = <0x61000000>;
217002 + #size-cells = <0>;
217004 + cpu@0 {
217007 + reg = <0x0 0x0>;
217016 + reg = <0x0 0x1>;
217024 + reg = <0x0 0x100>;
217032 + reg = <0x0 0x101>;
217097 + reg = <0x0 0x44000000 0x2 0x0>; /* system memory base */
217228 + spidev@0 {
217230 + reg = <0>;
217231 + pl022,interface = <0>;
217232 + pl022,com-mode = <0>;
217239 + pl022,interface = <0>;
217240 + pl022,com-mode = <0>;
217248 + spidev@0 {
217250 + reg = <0>;
217251 + pl022,interface = <0>;
217252 + pl022,com-mode = <0>;
217259 + pl022,interface = <0>;
217260 + pl022,com-mode = <0>;
217268 + spidev@0 {
217270 + reg = <0>;
217271 + pl022,interface = <0>;
217272 + pl022,com-mode = <0>;
217279 + pl022,interface = <0>;
217280 + pl022,com-mode = <0>;
217288 + spidev@0 {
217290 + reg = <0>;
217291 + pl022,interface = <0>;
217292 + pl022,com-mode = <0>;
217299 + pl022,interface = <0>;
217300 + pl022,com-mode = <0>;
217308 + spidev@0 {
217310 + reg = <0>;
217311 + pl022,interface = <0>;
217312 + pl022,com-mode = <0>;
217319 + pl022,interface = <0>;
217320 + pl022,com-mode = <0>;
217327 + pl022,interface = <0>;
217328 + pl022,com-mode = <0>;
217335 + pl022,interface = <0>;
217336 + pl022,com-mode = <0>;
217344 + spidev@0 {
217346 + reg = <0>;
217347 + pl022,interface = <0>;
217348 + pl022,com-mode = <0>;
217355 + pl022,interface = <0>;
217356 + pl022,com-mode = <0>;
217362 + pl022,interface = <0>;
217363 + pl022,com-mode = <0>;
217371 + spidev@0 {
217373 + reg = <0>;
217374 + pl022,interface = <0>;
217375 + pl022,com-mode = <0>;
217382 + pl022,interface = <0>;
217383 + pl022,com-mode = <0>;
217389 + pl022,interface = <0>;
217390 + pl022,com-mode = <0>;
217398 + spidev@0 {
217400 + reg = <0>;
217401 + pl022,interface = <0>;
217402 + pl022,com-mode = <0>;
217490 + reg = <0>;
217499 + reg = <0>;
217507 + reg = <0>;
217562 @@ -0,0 +1,1374 @@
217592 + #address-cells = <0>;
217595 + reg = <0x0 0x1F101000 0x0 0x1000>, <0x0 0x1F102000 0x0 0x100>;
217605 + interrupts = <0 117 4>,
217606 + <0 118 4>,
217607 + <0 127 4>,
217608 + <0 128 4>;
217617 + reg = <0x0 0x12010000 0x0 0x10000>;
217625 + reg = <0x0 0x18020000 0x0 0x10000>;
217634 + arm,psci-suspend-param = <0x0010000>;
217641 + arm,psci-suspend-param = <0x0000000>;
217642 + entry-latency-us = <0x3fffffff>;
217643 + exit-latency-us = <0x40000000>;
217644 + min-residency-us = <0xffffffff>;
217650 + interrupts = <0 211 4>, <0 212 4>;
217651 + reg = <0x0 0x12090000 0x0 0x1000>;
217660 + ranges = <0x0 0x00000000 0x0 0xffffffff>;
217664 + #clock-cells = <0>;
217677 + interrupts = <1 13 0xf04>,
217678 + <1 14 0xf04>;
217684 + reg = <0x12000000 0x20>, /* clocksource */
217685 + <0x1d840000 0x20>, /* local timer for each cpu */
217686 + <0x1d840020 0x20>,
217687 + <0x1d850000 0x20>,
217688 + <0x1d850020 0x20>;
217689 + interrupts = <0 113 4>, /* irq of local timer0/1 */
217690 + <0 114 4>, /* irq of local timer2/3 */
217691 + <0 115 4>, /* irq of local timer4/5 */
217692 + <0 116 4>; /* irq of local timer6/7 */
217699 + reg = <0x12100000 0x1000>;
217700 + interrupts = <0 6 4>;
217708 + reg = <0x12101000 0x1000>;
217709 + interrupts = <0 7 4>;
217717 + reg = <0x12102000 0x1000>;
217718 + interrupts = <0 8 4>;
217726 + reg = <0x12103000 0x1000>;
217727 + interrupts = <0 9 4>;
217735 + reg = <0x12104000 0x1000>;
217736 + interrupts = <0 10 4>;
217744 + reg = <0x18060000 0x1000>;
217745 + interrupts = <0 185 4>;
217757 + reg = <0x18061000 0x1000>;
217758 + interrupts = <0 186 4>;
217770 + reg = <0x18062000 0x1000>;
217771 + interrupts = <0 187 4>;
217783 + reg = <0x18063000 0x1000>;
217784 + interrupts = <0 188 4>;
217796 + reg = <0x18064000 0x1000>;
217797 + interrupts = <0 189 4>;
217809 + reg = <0x12110000 0x1000>;
217813 + dmas = <&hiedmacv310_1 0 10>, <&hiedmacv310_1 1 11>;
217819 + reg = <0x12111000 0x1000>;
217829 + reg = <0x12112000 0x1000>;
217839 + reg = <0x12113000 0x1000>;
217849 + reg = <0x12114000 0x1000>;
217859 + reg = <0x12115000 0x1000>;
217869 + reg = <0x12116000 0x1000>;
217879 + reg = <0x12117000 0x1000>;
217889 + reg = <0x12118000 0x1000>;
217899 + reg = <0x12119000 0x1000>;
217909 + reg = <0x1211a000 0x1000>;
217919 + reg = <0x1211b000 0x1000>;
217929 + reg = <0x18070000 0x1000>;
217937 + reg = <0x18071000 0x1000>;
217945 + reg = <0x18072000 0x1000>;
217953 + reg = <0x18073000 0x1000>;
217961 + reg = <0x18074000 0x1000>;
217969 + reg = <0x18075000 0x1000>;
217977 + reg = <0x18076000 0x1000>;
217985 + reg = <0x18077000 0x1000>;
217993 + arm,primecell-periphid = <0x00800022>;
217994 + reg = <0x12120000 0x1000>, <0x1203004c 0x4>;
217995 + interrupts = <0 31 4>;
217999 + #size-cells = <0>;
218002 + hisi,spi_cs_sb = <0>;
218008 + arm,primecell-periphid = <0x00800022>;
218009 + reg = <0x12121000 0x1000>, <0x12030050 0x4>;
218010 + interrupts = <0 32 4>;
218014 + #size-cells = <0>;
218017 + hisi,spi_cs_sb = <0>;
218023 + arm,primecell-periphid = <0x00800022>;
218024 + reg = <0x12122000 0x1000>, <0x12030054 0x4>;
218025 + interrupts = <0 33 4>;
218029 + #size-cells = <0>;
218032 + hisi,spi_cs_sb = <0>;
218038 + arm,primecell-periphid = <0x00800022>;
218039 + reg = <0x12123000 0x1000>, <0x12030058 0x4>;
218040 + interrupts = <0 34 4>;
218044 + #size-cells = <0>;
218047 + hisi,spi_cs_sb = <0>;
218053 + arm,primecell-periphid = <0x00800022>;
218054 + reg = <0x12124000 0x1000>, <0x1203005c 0x4>;
218055 + interrupts = <0 35 4>;
218059 + #size-cells = <0>;
218062 + hisi,spi_cs_sb = <0>;
218063 + hisi,spi_cs_mask_bit = <0x3>;
218068 + arm,primecell-periphid = <0x00800022>;
218069 + reg = <0x18080000 0x1000>, <0x18030088 0x4>;
218070 + interrupts = <0 198 4>;
218074 + #size-cells = <0>;
218077 + dmas = <&hiedmacv310_2 1 1>, <&hiedmacv310_2 0 0>;
218079 + hisi,spi_cs_sb = <0>;
218080 + hisi,spi_cs_mask_bit = <0x3>;
218085 + arm,primecell-periphid = <0x00800022>;
218086 + reg = <0x18081000 0x1000>, <0x18030088 0x4>;
218087 + interrupts = <0 199 4>;
218091 + #size-cells = <0>;
218097 + hisi,spi_cs_mask_bit = <0x3>;
218102 + arm,primecell-periphid = <0x00800022>;
218103 + reg = <0x18082000 0x1000>;
218104 + interrupts = <0 200 4>;
218108 + #size-cells = <0>;
218119 + reg = <0x12140000 0x1000>;
218120 + interrupts = <0 160 4>;
218129 + reg = <0x12141000 0x1000>;
218130 + interrupts = <0 161 4>;
218139 + reg = <0x12142000 0x1000>;
218140 + interrupts = <0 162 4>;
218149 + reg = <0x12143000 0x1000>;
218150 + interrupts = <0 163 4>;
218159 + reg = <0x12144000 0x1000>;
218160 + interrupts = <0 164 4>;
218169 + reg = <0x12145000 0x1000>;
218170 + interrupts = <0 165 4>;
218179 + reg = <0x12146000 0x1000>;
218180 + interrupts = <0 166 4>;
218189 + reg = <0x12147000 0x1000>;
218190 + interrupts = <0 167 4>;
218199 + reg = <0x12148000 0x1000>;
218200 + interrupts = <0 168 4>;
218209 + reg = <0x12149000 0x1000>;
218210 + interrupts = <0 169 4>;
218219 + reg = <0x1214a000 0x1000>;
218220 + interrupts = <0 170 4>;
218229 + reg = <0x1214b000 0x1000>;
218230 + interrupts = <0 171 4>;
218239 + reg = <0x1214c000 0x1000>;
218240 + interrupts = <0 172 4>;
218249 + reg = <0x1214d000 0x1000>;
218250 + interrupts = <0 173 4>;
218259 + reg = <0x1214e000 0x1000>;
218260 + interrupts = <0 174 4>;
218269 + reg = <0x1214f000 0x1000>;
218270 + interrupts = <0 175 4>;
218279 + reg = <0x12150000 0x1000>;
218280 + interrupts = <0 176 4>;
218289 + reg = <0x12151000 0x1000>;
218290 + interrupts = <0 177 4>;
218299 + reg = <0x12152000 0x1000>;
218300 + interrupts = <0 178 4>;
218309 + reg = <0x180b0000 0x1000>;
218310 + interrupts = <0 11 4>;
218316 + reg = <0x12010000 0x10000>, <0x12020000 0x10000>,
218317 + <0x12060000 0x10000>, <0X12030000 0x10000>;
218327 + reg = <0x12020000 0x1000>;
218328 + reboot-offset = <0x4>;
218333 + reg = <0x12030000 0x10000>;
218338 + reg = <0x18030000 0x1000>;
218343 + reg = <0x1f000000 0x10000>;
218349 + reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
218352 + max-dma-size = <0x2000>;
218354 + #size-cells = <0>;
218361 + #size-cells = <0>;
218369 + #size-cells = <0>;
218377 + #size-cells = <0>;
218381 + ufs: hiufs@0x10010000 {
218383 …0x10010000 0x1000>, <0x12010180 4>, <0x12030044 4>; /*for asci versionUFSbase:0x10010000 ufsCRG…
218384 + interrupts = <0 83 4>; //after +32 == datasheet value
218390 + cd-gpio = <&gpio_chip0 4 0>; /* card detect pin */
218398 + reg = <0x101c03c0 0x20>;
218400 + resets = <&clock 0x174 14>;
218403 + #size-cells = <0>;
218409 + reg = <0x101e03c0 0x20>;
218411 + resets = <&clock 0x174 15>;
218414 + #size-cells = <0>;
218419 + reg = <0x101c0000 0x1000>,<0x101c300c 0x4>;
218420 + interrupts = <0 36 4>;
218427 + resets = <&clock 0x174 0>,
218428 + <&clock 0x174 4>;
218437 + reg = <0x101e0000 0x1000>,<0x101e300c 0x4>;
218438 + interrupts = <0 37 4>;
218445 + resets = <&clock 0x174 2>,
218446 + <&clock 0x174 6>;
218457 + reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12020000 0x10000>, <0x12300000 0x…
218458 + phyid = <0>;
218463 + reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12020000 0x10000>, <0x12310000 0x…
218468 + xhci_0:xhci_0@0x12300000 {
218470 + reg = <0x12300000 0x10000>;
218471 + interrupts = <0 84 4>;
218476 + xhci_1:xhci_1@0x12310000 {
218478 + reg = <0x12310000 0x10000>;
218479 + interrupts = <0 85 4>;
218484 + hidwc3_0:hiudc3_0@0x12300000 {
218486 + reg = <0x12300000 0x10000>, <0x12010000 0x1000>, <0x12020000 0x1000>;
218487 + interrupts = <0 84 4>;
218488 + port_speed = <0>;
218497 + hidwc3_1:hiudc3_1@0x12310000 {
218499 + reg = <0x12310000 0x10000>, <0x12010000 0x1000>, <0x12020000 0x1000>;
218500 + interrupts = <0 85 4>;
218510 + mmc0: eMMC@0x100f0000 {
218512 + reg = <0x100f0000 0x1000>, <0x10290000 0x1000>;
218513 + interrupts = <0 26 4>;
218516 + resets = <&clock 0x1a8 27>, <&clock 0x1a8 29>, <&clock 0x1a8 30>;
218527 + devid = <0>;
218531 + mmc1: SD@0x10100000 {
218533 + reg = <0x10100000 0x1000>;
218534 + interrupts = <0 74 4>;
218537 + resets = <&clock 0x1ec 27>, <&clock 0x1ec 29>, <&clock 0x1ec 30>;
218552 + mmc2: SD@0x10110000 {
218554 + reg = <0x10110000 0x1000>;
218555 + interrupts = <0 75 4>;
218558 + resets = <&clock 0x214 27>, <&clock 0x214 29>, <&clock 0x214 30>;
218572 + mmc3: SDIO@0x10120000 {
218574 + reg = <0x10120000 0x1000>;
218575 + interrupts = <0 76 4>;
218578 + resets = <&clock 0x23c 27>, <&clock 0x23c 29>, <&clock 0x23c 30>;
218591 + pcie0: pcie@0x12200000 {
218597 + bus-range = <0x0 0xff>;
218598 + reg = <0x00 0x12200000 0x00 0x2000>;
218599 + ranges = <0x02000000 0x00 0x30000000 0x30000000 0x00 0xff00000>;
218600 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
218601 + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 143 0x4
218602 + 0x0 0x0 0x0 0x2 &gic 0x0 144 0x4
218603 + 0x0 0x0 0x0 0x3 &gic 0x0 145 0x4
218604 + 0x0 0x0 0x0 0x4 &gic 0x0 146 0x4>;
218605 + interrupts = <0 148 4>;
218607 + pcie_controller = <0>;
218608 + dev_mem_size = <0x8000000>;
218609 + dev_conf_size = <0x8000000>;
218610 + sys_ctrl_base = <0x12020000>;
218612 + pcie_mcc: pcie_mcc@0x0 {
218614 + interrupts = <0 143 4>,<0 144 4>,< 0 145 4>
218615 + ,< 0 146 4>,< 0 147 4>,< 0 38 4>;
218620 + reg = <0x1f010000 0x1000>;
218621 + interrupts = <0 27 4>;
218624 + resets = <&clock 0x14c 4>;
218632 + reg = <0x10040000 0x1000>;
218634 + misc_ctrl_base = <0x144>;
218635 + interrupts = <0 82 4>;
218639 + resets = <&clock 0x16c 7>;
218651 + reg = <0x180f0000 0x1000>;
218653 + misc_ctrl_base = <0x6c>;
218654 + interrupts = <0 202 4>;
218658 + resets = <&clock_shub 0x24 0>;
218668 + vi: vi@0x11800000 {
218670 + reg = <0x11800000 0x30000>, <0x11a80000 0x40000>, <0x11ac0000 0x40000>;
218672 + interrupts = <0 60 4>, <0 61 4>, <0 62 4>;
218676 + isp: isp@0x11820000 {
218678 + reg = <0x11820000 0x100000>;
218680 + interrupts = <0 60 4>;
218684 + mipi: mipi@0x11a00000 {
218686 + reg = <0x11a00000 0x20000>, <0x11a40000 0x10000>;
218688 + interrupts = <0 86 4>, <0 88 4>;
218692 + vpss: vpss@0x11420000 {
218694 + reg = <0x11420000 0x20000>, <0x11440000 0x20000>;
218696 + interrupts = <0 45 4>, <0 46 4>;
218700 + vgs: vgs@0x11E20000 {
218702 + reg = <0x11E20000 0x10000>, <0x11260000 0x10000>;
218704 + interrupts = <0 43 4>, <0 44 4>;
218708 + gdc: gdc@0x11240000 {
218710 + reg = <0x11240000 0x10000>, <0x11250000 0x10000>;
218712 + interrupts = <0 47 4>, <0 48 4>;
218716 + dis: dis@0x11200000 {
218718 + reg = <0x11200000 0x10000>;
218720 + interrupts = <0 51 4>;
218724 + avs: avs@0x11d00000 {
218726 + reg = <0x11d00000 0x10000>;
218728 + interrupts = <0 152 4>;
218732 + vo: vo@0x11100000 {
218734 + reg = <0x11100000 0x20000>;
218736 + interrupts = <0 67 4>;
218739 + hifb: hifb@0x11100000 {
218741 + reg = <0x11100000 0x20000>;
218743 + interrupts = <0 68 4>;
218746 + mipi_tx: mipi_tx@0x11170000 {
218748 + reg = <0x11170000 0x10000>;
218750 + interrupts = <0 63 4>;
218753 + hdmi: hdmi@0x11140000 {
218755 + reg = <0x11140000 0x30000>, <0x12010000 0x10000>, <0x12000000 0x6000>;
218757 + interrupts = <0 5 4>;
218761 + vedu: vedu@0x11300000 {
218763 + reg = <0x11300000 0x10000>, <0x11310000 0x10000>,<0x11400000 0x10000>,<0x11320000 0x10…
218765 + interrupts = <0 39 4>, <0 40 4>,<0 41 4>,<0 49 4>;
218773 + vdh: vdh@0x11e10000 {
218775 + reg = <0x11e10000 0x10000>;
218777 + interrupts = <0 91 4>,<0 92 4>,<0 94 4>;
218781 + jpegd: jpegd@0x11210000 {
218783 + reg = <0x11210000 0x10000>;
218785 + interrupts = <0 52 4>;
218789 + nnie: nnie@0x11500000 {
218791 + reg = <0x11500000 0x10000>,<0x11600000 0x10000>;
218793 + interrupts = <0 58 4>,<0 59 4>;
218796 + dpu_rect: dpu_rect@0x11630000 {
218798 + reg = <0x11630000 0x10000>;
218800 + interrupts = <0 208 4>;
218803 + dpu_match: dpu_match@0x11630000 {
218805 + reg = <0x11630000 0x10000>;
218807 + interrupts = <0 209 4>;
218810 + dsp: dsp@0x11510000 {
218812 + reg = <0x11510000 0x10000>,<0x11520000 0x10000>,<0x11610000 0x10000>,<0x11620000 0…
218815 + ive: ive@0x11530000 {
218817 + reg = <0x11530000 0x10000>;
218819 + interrupts = <0 56 4>;
218822 + fd: fd@0x11E00000 {
218824 + reg = <0x11E00000 0x10000>;
218826 + interrupts = <0 57 4>;
218831 + reg = <0x11180000 0x10000>,<0x11190000 0x10000>,<0x12010000 0x10000>;
218833 + interrupts = <0 69 4>,<0 102 4>;
218837 + tde: tde@0x11230000 {
218839 + reg = <0x11230000 0x10000>;
218841 + interrupts = <0 53 4>;
218845 + vddgpu: regulator@0x12030064 {
218847 + reg = <0x12030064 0x4>;
218858 + reg = <0x12030000 0x1000>;
218867 + reg_offset = <0x6c>;
218875 + reg_offset = <0x64>;
218883 + reg_offset = <0x68>;
218888 + gpu:gpu@0x11C00000 {
218890 + reg = <0x11C00000 0x4000>;
218891 + interrupts = <0 102 4>, <0 103 4>, <0 101 4>;
218906 + cipher: cipher@0x10200000 {
218908 + reg = <0x10200000 0x10000>,<0x10220000 0x10000>;
218910 + interrupts = <0 30 4>,<0 30 4>,<0 104 4>;
218914 + ir: ir@0x120F0000 {
218916 + reg = <0x120F0000 0x10000>;
218918 + interrupts = <0 24 4>;
218921 + wdg: wdg@0x12080000 {
218923 + reg = <0x12080000 0x1000>,<0x12081000 0x1000>,<0x12082000 0x1000>;
218925 + interrupts = <0 105 4>;
218928 + irq: irq@0x120F0000 {
218930 …0x11800000 0x30000>,<0x11a80000 0x40000>,<0x11ac0000 0x40000>,<0x11820000 0x100000>,<0x11420000 0x…
218932 …0 60 4>, <0 61 4>, <0 62 4>, <0 60 4>,<0 45 4>,<0 46 4>,<0 43 4>,<0 44 4>,<0 47 4>,<0 48 4>,<0 5…
218943 @@ -0,0 +1,596 @@
218965 +/memreserve/ 0x53000000 0x00200000;
219038 + linux,initrd-start = <0x60000040>;
219039 + linux,initrd-end = <0x61000000>;
219044 + #size-cells = <0>;
219046 + cpu@0 {
219049 + reg = <0x0 0x0>;
219057 + reg = <0x0 0x1>;
219064 + reg = <0x0 0x100>;
219071 + reg = <0x0 0x101>;
219080 + reg = <0x0 0x50000000 0x2 0x0>; /* system memory base */
219211 + spidev@0 {
219213 + reg = <0>;
219214 + pl022,interface = <0>;
219215 + pl022,com-mode = <0>;
219222 + pl022,interface = <0>;
219223 + pl022,com-mode = <0>;
219231 + spidev@0 {
219233 + reg = <0>;
219234 + pl022,interface = <0>;
219235 + pl022,com-mode = <0>;
219242 + pl022,interface = <0>;
219243 + pl022,com-mode = <0>;
219251 + spidev@0 {
219253 + reg = <0>;
219254 + pl022,interface = <0>;
219255 + pl022,com-mode = <0>;
219262 + pl022,interface = <0>;
219263 + pl022,com-mode = <0>;
219271 + spidev@0 {
219273 + reg = <0>;
219274 + pl022,interface = <0>;
219275 + pl022,com-mode = <0>;
219282 + pl022,interface = <0>;
219283 + pl022,com-mode = <0>;
219291 + spidev@0 {
219293 + reg = <0>;
219294 + pl022,interface = <0>;
219295 + pl022,com-mode = <0>;
219302 + pl022,interface = <0>;
219303 + pl022,com-mode = <0>;
219310 + pl022,interface = <0>;
219311 + pl022,com-mode = <0>;
219318 + pl022,interface = <0>;
219319 + pl022,com-mode = <0>;
219327 + spidev@0 {
219329 + reg = <0>;
219330 + pl022,interface = <0>;
219331 + pl022,com-mode = <0>;
219338 + pl022,interface = <0>;
219339 + pl022,com-mode = <0>;
219345 + pl022,interface = <0>;
219346 + pl022,com-mode = <0>;
219354 + spidev@0 {
219356 + reg = <0>;
219357 + pl022,interface = <0>;
219358 + pl022,com-mode = <0>;
219365 + pl022,interface = <0>;
219366 + pl022,com-mode = <0>;
219372 + pl022,interface = <0>;
219373 + pl022,com-mode = <0>;
219381 + spidev@0 {
219383 + reg = <0>;
219384 + pl022,interface = <0>;
219385 + pl022,com-mode = <0>;
219473 + reg = <0>;
219482 + reg = <0>;
219490 + reg = <0>;
219501 +#if 0
219514 +#if 0
219545 @@ -0,0 +1,32 @@
219583 @@ -0,0 +1,32 @@
219621 @@ -0,0 +1,32 @@
219659 @@ -0,0 +1,655 @@
219681 +/memreserve/ 0x47000000 0x00200000;
219754 + linux,initrd-start = <0x60000040>;
219755 + linux,initrd-end = <0x61000000>;
219760 + #size-cells = <0>;
219762 + cpu@0 {
219765 + reg = <0x0 0x0>;
219774 + reg = <0x0 0x1>;
219782 + reg = <0x0 0x100>;
219790 + reg = <0x0 0x101>;
219855 + reg = <0x0 0x44000000 0x2 0x0>; /* system memory base */
219986 + spidev@0 {
219988 + reg = <0>;
219989 + pl022,interface = <0>;
219990 + pl022,com-mode = <0>;
219997 + pl022,interface = <0>;
219998 + pl022,com-mode = <0>;
220006 + spidev@0 {
220008 + reg = <0>;
220009 + pl022,interface = <0>;
220010 + pl022,com-mode = <0>;
220017 + pl022,interface = <0>;
220018 + pl022,com-mode = <0>;
220026 + spidev@0 {
220028 + reg = <0>;
220029 + pl022,interface = <0>;
220030 + pl022,com-mode = <0>;
220037 + pl022,interface = <0>;
220038 + pl022,com-mode = <0>;
220046 + spidev@0 {
220048 + reg = <0>;
220049 + pl022,interface = <0>;
220050 + pl022,com-mode = <0>;
220057 + pl022,interface = <0>;
220058 + pl022,com-mode = <0>;
220066 + spidev@0 {
220068 + reg = <0>;
220069 + pl022,interface = <0>;
220070 + pl022,com-mode = <0>;
220077 + pl022,interface = <0>;
220078 + pl022,com-mode = <0>;
220085 + pl022,interface = <0>;
220086 + pl022,com-mode = <0>;
220093 + pl022,interface = <0>;
220094 + pl022,com-mode = <0>;
220102 + spidev@0 {
220104 + reg = <0>;
220105 + pl022,interface = <0>;
220106 + pl022,com-mode = <0>;
220113 + pl022,interface = <0>;
220114 + pl022,com-mode = <0>;
220120 + pl022,interface = <0>;
220121 + pl022,com-mode = <0>;
220129 + spidev@0 {
220131 + reg = <0>;
220132 + pl022,interface = <0>;
220133 + pl022,com-mode = <0>;
220140 + pl022,interface = <0>;
220141 + pl022,com-mode = <0>;
220147 + pl022,interface = <0>;
220148 + pl022,com-mode = <0>;
220156 + spidev@0 {
220158 + reg = <0>;
220159 + pl022,interface = <0>;
220160 + pl022,com-mode = <0>;
220248 + reg = <0>;
220257 + reg = <0>;
220265 + reg = <0>;
220320 @@ -0,0 +1,1364 @@
220350 + #address-cells = <0>;
220353 + reg = <0x0 0x1F101000 0x0 0x1000>, <0x0 0x1F102000 0x0 0x100>;
220363 + interrupts = <0 117 4>,
220364 + <0 118 4>,
220365 + <0 127 4>,
220366 + <0 128 4>;
220375 + reg = <0x0 0x12010000 0x0 0x10000>;
220383 + reg = <0x0 0x18020000 0x0 0x10000>;
220392 + arm,psci-suspend-param = <0x0010000>;
220399 + arm,psci-suspend-param = <0x0000000>;
220400 + entry-latency-us = <0x3fffffff>;
220401 + exit-latency-us = <0x40000000>;
220402 + min-residency-us = <0xffffffff>;
220408 + interrupts = <0 211 4>, <0 212 4>;
220409 + reg = <0x0 0x12090000 0x0 0x1000>;
220418 + ranges = <0x0 0x00000000 0x0 0xffffffff>;
220422 + #clock-cells = <0>;
220435 + interrupts = <1 13 0xf04>,
220436 + <1 14 0xf04>;
220442 + reg = <0x12000000 0x20>, /* clocksource */
220443 + <0x1d840000 0x20>, /* local timer for each cpu */
220444 + <0x1d840020 0x20>,
220445 + <0x1d850000 0x20>,
220446 + <0x1d850020 0x20>;
220447 + interrupts = <0 113 4>, /* irq of local timer0/1 */
220448 + <0 114 4>, /* irq of local timer2/3 */
220449 + <0 115 4>, /* irq of local timer4/5 */
220450 + <0 116 4>; /* irq of local timer6/7 */
220457 + reg = <0x12100000 0x1000>;
220458 + interrupts = <0 6 4>;
220466 + reg = <0x12101000 0x1000>;
220467 + interrupts = <0 7 4>;
220475 + reg = <0x12102000 0x1000>;
220476 + interrupts = <0 8 4>;
220484 + reg = <0x12103000 0x1000>;
220485 + interrupts = <0 9 4>;
220493 + reg = <0x12104000 0x1000>;
220494 + interrupts = <0 10 4>;
220502 + reg = <0x18060000 0x1000>;
220503 + interrupts = <0 185 4>;
220515 + reg = <0x18061000 0x1000>;
220516 + interrupts = <0 186 4>;
220528 + reg = <0x18062000 0x1000>;
220529 + interrupts = <0 187 4>;
220541 + reg = <0x18063000 0x1000>;
220542 + interrupts = <0 188 4>;
220554 + reg = <0x18064000 0x1000>;
220555 + interrupts = <0 189 4>;
220567 + reg = <0x12110000 0x1000>;
220571 + dmas = <&hiedmacv310_1 0 10>, <&hiedmacv310_1 1 11>;
220577 + reg = <0x12111000 0x1000>;
220587 + reg = <0x12112000 0x1000>;
220597 + reg = <0x12113000 0x1000>;
220607 + reg = <0x12114000 0x1000>;
220617 + reg = <0x12115000 0x1000>;
220627 + reg = <0x12116000 0x1000>;
220637 + reg = <0x12117000 0x1000>;
220647 + reg = <0x12118000 0x1000>;
220657 + reg = <0x12119000 0x1000>;
220667 + reg = <0x1211a000 0x1000>;
220677 + reg = <0x1211b000 0x1000>;
220687 + reg = <0x18070000 0x1000>;
220695 + reg = <0x18071000 0x1000>;
220703 + reg = <0x18072000 0x1000>;
220711 + reg = <0x18073000 0x1000>;
220719 + reg = <0x18074000 0x1000>;
220727 + reg = <0x18075000 0x1000>;
220735 + reg = <0x18076000 0x1000>;
220743 + reg = <0x18077000 0x1000>;
220751 + arm,primecell-periphid = <0x00800022>;
220752 + reg = <0x12120000 0x1000>, <0x1203004c 0x4>;
220753 + interrupts = <0 31 4>;
220757 + #size-cells = <0>;
220760 + hisi,spi_cs_sb = <0>;
220766 + arm,primecell-periphid = <0x00800022>;
220767 + reg = <0x12121000 0x1000>, <0x12030050 0x4>;
220768 + interrupts = <0 32 4>;
220772 + #size-cells = <0>;
220775 + hisi,spi_cs_sb = <0>;
220781 + arm,primecell-periphid = <0x00800022>;
220782 + reg = <0x12122000 0x1000>, <0x12030054 0x4>;
220783 + interrupts = <0 33 4>;
220787 + #size-cells = <0>;
220790 + hisi,spi_cs_sb = <0>;
220796 + arm,primecell-periphid = <0x00800022>;
220797 + reg = <0x12123000 0x1000>, <0x12030058 0x4>;
220798 + interrupts = <0 34 4>;
220802 + #size-cells = <0>;
220805 + hisi,spi_cs_sb = <0>;
220811 + arm,primecell-periphid = <0x00800022>;
220812 + reg = <0x12124000 0x1000>, <0x1203005c 0x4>;
220813 + interrupts = <0 35 4>;
220817 + #size-cells = <0>;
220820 + hisi,spi_cs_sb = <0>;
220821 + hisi,spi_cs_mask_bit = <0x3>;
220826 + arm,primecell-periphid = <0x00800022>;
220827 + reg = <0x18080000 0x1000>, <0x18030088 0x4>;
220828 + interrupts = <0 198 4>;
220832 + #size-cells = <0>;
220835 + dmas = <&hiedmacv310_2 1 1>, <&hiedmacv310_2 0 0>;
220837 + hisi,spi_cs_sb = <0>;
220838 + hisi,spi_cs_mask_bit = <0x3>;
220843 + arm,primecell-periphid = <0x00800022>;
220844 + reg = <0x18081000 0x1000>, <0x18030088 0x4>;
220845 + interrupts = <0 199 4>;
220849 + #size-cells = <0>;
220855 + hisi,spi_cs_mask_bit = <0x3>;
220860 + arm,primecell-periphid = <0x00800022>;
220861 + reg = <0x18082000 0x1000>;
220862 + interrupts = <0 200 4>;
220866 + #size-cells = <0>;
220877 + reg = <0x12140000 0x1000>;
220878 + interrupts = <0 160 4>;
220887 + reg = <0x12141000 0x1000>;
220888 + interrupts = <0 161 4>;
220897 + reg = <0x12142000 0x1000>;
220898 + interrupts = <0 162 4>;
220907 + reg = <0x12143000 0x1000>;
220908 + interrupts = <0 163 4>;
220917 + reg = <0x12144000 0x1000>;
220918 + interrupts = <0 164 4>;
220927 + reg = <0x12145000 0x1000>;
220928 + interrupts = <0 165 4>;
220937 + reg = <0x12146000 0x1000>;
220938 + interrupts = <0 166 4>;
220947 + reg = <0x12147000 0x1000>;
220948 + interrupts = <0 167 4>;
220957 + reg = <0x12148000 0x1000>;
220958 + interrupts = <0 168 4>;
220967 + reg = <0x12149000 0x1000>;
220968 + interrupts = <0 169 4>;
220977 + reg = <0x1214a000 0x1000>;
220978 + interrupts = <0 170 4>;
220987 + reg = <0x1214b000 0x1000>;
220988 + interrupts = <0 171 4>;
220997 + reg = <0x1214c000 0x1000>;
220998 + interrupts = <0 172 4>;
221007 + reg = <0x1214d000 0x1000>;
221008 + interrupts = <0 173 4>;
221017 + reg = <0x1214e000 0x1000>;
221018 + interrupts = <0 174 4>;
221027 + reg = <0x1214f000 0x1000>;
221028 + interrupts = <0 175 4>;
221037 + reg = <0x12150000 0x1000>;
221038 + interrupts = <0 176 4>;
221047 + reg = <0x12151000 0x1000>;
221048 + interrupts = <0 177 4>;
221057 + reg = <0x12152000 0x1000>;
221058 + interrupts = <0 178 4>;
221067 + reg = <0x180b0000 0x1000>;
221068 + interrupts = <0 11 4>;
221074 + reg = <0x12010000 0x10000>, <0x12020000 0x10000>,
221075 + <0x12060000 0x10000>, <0X12030000 0x10000>;
221085 + reg = <0x12020000 0x1000>;
221086 + reboot-offset = <0x4>;
221091 + reg = <0x12030000 0x10000>;
221096 + reg = <0x18030000 0x1000>;
221101 + reg = <0x1f000000 0x10000>;
221107 + reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
221110 + max-dma-size = <0x2000>;
221112 + #size-cells = <0>;
221119 + #size-cells = <0>;
221127 + #size-cells = <0>;
221135 + #size-cells = <0>;
221139 + ufs: hiufs@0x10010000 {
221141 …0x10010000 0x1000>, <0x12010180 4>, <0x12030044 4>; /*for asci versionUFSbase:0x10010000 ufsCRG…
221142 + interrupts = <0 83 4>; //after +32 == datasheet value
221149 + cd-gpio = <&gpio_chip0 4 0>; /* card detect pin */
221156 + reg = <0x101c03c0 0x20>;
221158 + resets = <&clock 0x174 14>;
221161 + #size-cells = <0>;
221167 + reg = <0x101e03c0 0x20>;
221169 + resets = <&clock 0x174 15>;
221172 + #size-cells = <0>;
221177 + reg = <0x101c0000 0x1000>,<0x101c300c 0x4>;
221178 + interrupts = <0 36 4>;
221185 + resets = <&clock 0x174 0>,
221186 + <&clock 0x174 4>;
221195 + reg = <0x101e0000 0x1000>,<0x101e300c 0x4>;
221196 + interrupts = <0 37 4>;
221203 + resets = <&clock 0x174 2>,
221204 + <&clock 0x174 6>;
221215 + reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12020000 0x10000>, <0x12300000 0x…
221216 + phyid = <0>;
221221 + reg = <0x12010000 0x10000>, <0x12030000 0x10000>, <0x12020000 0x10000>, <0x12310000 0x…
221226 + xhci_0:xhci_0@0x12300000 {
221228 + reg = <0x12300000 0x10000>;
221229 + interrupts = <0 84 4>;
221234 + xhci_1:xhci_1@0x12310000 {
221236 + reg = <0x12310000 0x10000>;
221237 + interrupts = <0 85 4>;
221242 + hidwc3_0:hiudc3_0@0x12300000 {
221244 + reg = <0x12300000 0x10000>, <0x12010000 0x1000>, <0x12020000 0x1000>;
221245 + interrupts = <0 84 4>;
221246 + port_speed = <0>;
221255 + hidwc3_1:hiudc3_1@0x12310000 {
221257 + reg = <0x12310000 0x10000>, <0x12010000 0x1000>, <0x12020000 0x1000>;
221258 + interrupts = <0 85 4>;
221268 + mmc0: eMMC@0x100f0000 {
221270 + reg = <0x100f0000 0x1000>, <0x10290000 0x1000>;
221271 + interrupts = <0 26 4>;
221274 + resets = <&clock 0x1a8 27>, <&clock 0x1a8 29>, <&clock 0x1a8 30>;
221284 + devid = <0>;
221288 + mmc1: SD@0x10100000 {
221290 + reg = <0x10100000 0x1000>;
221291 + interrupts = <0 74 4>;
221294 + resets = <&clock 0x1ec 27>, <&clock 0x1ec 29>, <&clock 0x1ec 30>;
221309 + mmc2: SD@0x10110000 {
221311 + reg = <0x10110000 0x1000>;
221312 + interrupts = <0 75 4>;
221315 + resets = <&clock 0x214 27>, <&clock 0x214 29>, <&clock 0x214 30>;
221329 + mmc3: SDIO@0x10120000 {
221331 + reg = <0x10120000 0x1000>;
221332 + interrupts = <0 76 4>;
221335 + resets = <&clock 0x23c 27>, <&clock 0x23c 29>, <&clock 0x23c 30>;
221348 + pcie0: pcie@0x12200000 {
221354 + bus-range = <0x0 0xff>;
221355 + reg = <0x00 0x12200000 0x00 0x2000>;
221356 + ranges = <0x02000000 0x00 0x30000000 0x30000000 0x00 0xff00000>;
221357 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
221358 + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 143 0x4
221359 + 0x0 0x0 0x0 0x2 &gic 0x0 144 0x4
221360 + 0x0 0x0 0x0 0x3 &gic 0x0 145 0x4
221361 + 0x0 0x0 0x0 0x4 &gic 0x0 146 0x4>;
221362 + interrupts = <0 148 4>;
221364 + pcie_controller = <0>;
221365 + dev_mem_size = <0x8000000>;
221366 + dev_conf_size = <0x8000000>;
221367 + sys_ctrl_base = <0x12020000>;
221369 + pcie_mcc: pcie_mcc@0x0 {
221371 + interrupts = <0 143 4>,<0 144 4>,< 0 145 4>
221372 + ,< 0 146 4>,< 0 147 4>,< 0 38 4>;
221377 + reg = <0x1f010000 0x1000>;
221378 + interrupts = <0 27 4>;
221381 + resets = <&clock 0x14c 4>;
221389 + reg = <0x10040000 0x1000>;
221391 + misc_ctrl_base = <0x144>;
221392 + interrupts = <0 82 4>;
221396 + resets = <&clock 0x16c 7>;
221408 + reg = <0x180f0000 0x1000>;
221410 + misc_ctrl_base = <0x6c>;
221411 + interrupts = <0 202 4>;
221415 + resets = <&clock_shub 0x24 0>;
221425 + vi: vi@0x11800000 {
221427 + reg = <0x11800000 0x30000>, <0x11a80000 0x40000>, <0x11ac0000 0x40000>;
221429 + interrupts = <0 60 4>, <0 61 4>, <0 62 4>;
221433 + isp: isp@0x11820000 {
221435 + reg = <0x11820000 0x100000>;
221437 + interrupts = <0 60 4>;
221441 + mipi: mipi@0x11a00000 {
221443 + reg = <0x11a00000 0x20000>, <0x11a40000 0x10000>;
221445 + interrupts = <0 86 4>, <0 88 4>;
221449 + vpss: vpss@0x11420000 {
221451 + reg = <0x11420000 0x20000>, <0x11440000 0x20000>;
221453 + interrupts = <0 45 4>, <0 46 4>;
221457 + vgs: vgs@0x11E20000 {
221459 + reg = <0x11E20000 0x10000>, <0x11260000 0x10000>;
221461 + interrupts = <0 43 4>, <0 44 4>;
221465 + gdc: gdc@0x11240000 {
221467 + reg = <0x11240000 0x10000>, <0x11250000 0x10000>;
221469 + interrupts = <0 47 4>, <0 48 4>;
221473 + dis: dis@0x11200000 {
221475 + reg = <0x11200000 0x10000>;
221477 + interrupts = <0 51 4>;
221481 + avs: avs@0x11d00000 {
221483 + reg = <0x11d00000 0x10000>;
221485 + interrupts = <0 152 4>;
221489 + vo: vo@0x11100000 {
221491 + reg = <0x11100000 0x20000>;
221493 + interrupts = <0 67 4>;
221496 + hifb: hifb@0x11100000 {
221498 + reg = <0x11100000 0x20000>;
221500 + interrupts = <0 68 4>;
221503 + mipi_tx: mipi_tx@0x11170000 {
221505 + reg = <0x11170000 0x10000>;
221507 + interrupts = <0 63 4>;
221510 + hdmi: hdmi@0x11140000 {
221512 + reg = <0x11140000 0x30000>, <0x12010000 0x10000>, <0x12000000 0x6000>;
221514 + interrupts = <0 5 4>;
221518 + vedu: vedu@0x11300000 {
221520 + reg = <0x11300000 0x10000>, <0x11310000 0x10000>,<0x11400000 0x10000>,<0x11320000 0x10…
221522 + interrupts = <0 39 4>, <0 40 4>,<0 41 4>,<0 49 4>;
221530 + vdh: vdh@0x11e10000 {
221532 + reg = <0x11e10000 0x10000>;
221534 + interrupts = <0 91 4>,<0 92 4>,<0 94 4>;
221538 + jpegd: jpegd@0x11210000 {
221540 + reg = <0x11210000 0x10000>;
221542 + interrupts = <0 52 4>;
221546 + nnie: nnie@0x11500000 {
221548 + reg = <0x11500000 0x10000>,<0x11600000 0x10000>;
221550 + interrupts = <0 58 4>,<0 59 4>;
221553 + dpu_rect: dpu_rect@0x11630000 {
221555 + reg = <0x11630000 0x10000>;
221557 + interrupts = <0 208 4>;
221560 + dpu_match: dpu_match@0x11630000 {
221562 + reg = <0x11630000 0x10000>;
221564 + interrupts = <0 209 4>;
221567 + dsp: dsp@0x11510000 {
221569 + reg = <0x11510000 0x10000>,<0x11520000 0x10000>,<0x11610000 0x10000>,<0x11620000 0…
221572 + ive: ive@0x11530000 {
221574 + reg = <0x11530000 0x10000>;
221576 + interrupts = <0 56 4>;
221579 + fd: fd@0x11E00000 {
221581 + reg = <0x11E00000 0x10000>;
221583 + interrupts = <0 57 4>;
221588 + reg = <0x11180000 0x10000>,<0x11190000 0x10000>,<0x12010000 0x10000>;
221590 + interrupts = <0 69 4>,<0 102 4>;
221594 + tde: tde@0x11230000 {
221596 + reg = <0x11230000 0x10000>;
221598 + interrupts = <0 53 4>;
221602 + vddgpu: regulator@0x12030064 {
221604 + reg = <0x12030064 0x4>;
221615 + reg = <0x12030000 0x1000>;
221624 + reg_offset = <0x6c>;
221632 + reg_offset = <0x64>;
221640 + reg_offset = <0x68>;
221645 + gpu:gpu@0x11C00000 {
221647 + reg = <0x11C00000 0x4000>;
221648 + interrupts = <0 102 4>, <0 103 4>, <0 101 4>;
221660 + cipher: cipher@0x10200000 {
221662 + reg = <0x10200000 0x10000>,<0x10220000 0x10000>;
221664 + interrupts = <0 30 4>,<0 30 4>,<0 104 4>;
221668 + ir: ir@0x120F0000 {
221670 + reg = <0x120F0000 0x10000>;
221672 + interrupts = <0 24 4>;
221675 + wdg: wdg@0x12080000 {
221677 + reg = <0x12080000 0x1000>,<0x12081000 0x1000>,<0x12082000 0x1000>;
221679 + interrupts = <0 105 4>;
221690 @@ -0,0 +1,3458 @@
221697 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
221701 +CONFIG_CLANG_VERSION=0
221864 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
222212 +CONFIG_BASE_SMALL=0
222546 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
222927 +CONFIG_HISI_SATA_IOBASE=0x10390000
223021 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
223022 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
224628 +CONFIG_JFFS2_FS_DEBUG=0
225007 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
225043 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
225047 +CONFIG_PANIC_TIMEOUT=0
225154 @@ -0,0 +1,3491 @@
225161 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
225165 +CONFIG_CLANG_VERSION=0
225328 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
225676 +CONFIG_BASE_SMALL=0
226010 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
226389 +CONFIG_HISI_SATA_IOBASE=0x10390000
226483 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
226484 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
228125 +CONFIG_JFFS2_FS_DEBUG=0
228504 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
228540 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
228544 +CONFIG_PANIC_TIMEOUT=0
228651 @@ -0,0 +1,3458 @@
228658 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
228662 +CONFIG_CLANG_VERSION=0
228825 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
229173 +CONFIG_BASE_SMALL=0
229507 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
229888 +CONFIG_HISI_SATA_IOBASE=0x10390000
229982 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
229983 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
231589 +CONFIG_JFFS2_FS_DEBUG=0
231968 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
232004 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
232008 +CONFIG_PANIC_TIMEOUT=0
232115 @@ -0,0 +1,3491 @@
232122 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
232126 +CONFIG_CLANG_VERSION=0
232289 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
232637 +CONFIG_BASE_SMALL=0
232971 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
233350 +CONFIG_HISI_SATA_IOBASE=0x10390000
233444 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
233445 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
235086 +CONFIG_JFFS2_FS_DEBUG=0
235465 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
235501 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
235505 +CONFIG_PANIC_TIMEOUT=0
235612 @@ -0,0 +1,3530 @@
235619 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
235623 +CONFIG_CLANG_VERSION=0
235786 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
236138 +CONFIG_BASE_SMALL=0
236472 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
236926 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
236927 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
238623 +CONFIG_JFFS2_FS_DEBUG=0
239000 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
239036 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
239040 +CONFIG_PANIC_TIMEOUT=0
239148 @@ -0,0 +1,3530 @@
239155 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
239159 +CONFIG_CLANG_VERSION=0
239322 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
239674 +CONFIG_BASE_SMALL=0
240008 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
240462 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
240463 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
242159 +CONFIG_JFFS2_FS_DEBUG=0
242536 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
242572 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
242576 +CONFIG_PANIC_TIMEOUT=0
242684 @@ -0,0 +1,3530 @@
242691 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
242695 +CONFIG_CLANG_VERSION=0
242858 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
243210 +CONFIG_BASE_SMALL=0
243544 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
243998 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
243999 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
245695 +CONFIG_JFFS2_FS_DEBUG=0
246072 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
246108 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
246112 +CONFIG_PANIC_TIMEOUT=0
246220 @@ -0,0 +1,3530 @@
246227 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
246231 +CONFIG_CLANG_VERSION=0
246394 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
246746 +CONFIG_BASE_SMALL=0
247080 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
247534 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
247535 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
249231 +CONFIG_JFFS2_FS_DEBUG=0
249608 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
249644 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
249648 +CONFIG_PANIC_TIMEOUT=0
249756 @@ -0,0 +1,3643 @@
249763 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
249767 +CONFIG_CLANG_VERSION=0
249930 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
250282 +CONFIG_BASE_SMALL=0
250616 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
251070 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
251071 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
252856 +CONFIG_JFFS2_FS_DEBUG=0
253257 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
253293 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
253297 +CONFIG_PANIC_TIMEOUT=0
253405 @@ -0,0 +1,3526 @@
253412 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
253416 +CONFIG_CLANG_VERSION=0
253579 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
253931 +CONFIG_BASE_SMALL=0
254265 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
254715 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
254716 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
256412 +CONFIG_JFFS2_FS_DEBUG=0
256789 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
256825 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
256829 +CONFIG_PANIC_TIMEOUT=0
256937 @@ -0,0 +1,3526 @@
256944 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
256948 +CONFIG_CLANG_VERSION=0
257111 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
257463 +CONFIG_BASE_SMALL=0
257797 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
258247 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
258248 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
259944 +CONFIG_JFFS2_FS_DEBUG=0
260321 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
260357 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
260361 +CONFIG_PANIC_TIMEOUT=0
260469 @@ -0,0 +1,3497 @@
260476 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
260480 +CONFIG_CLANG_VERSION=0
260643 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
260995 +CONFIG_BASE_SMALL=0
261329 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
261787 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
261788 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
263447 +CONFIG_JFFS2_FS_DEBUG=0
263824 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
263860 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
263864 +CONFIG_PANIC_TIMEOUT=0
263972 @@ -0,0 +1,3497 @@
263979 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
263983 +CONFIG_CLANG_VERSION=0
264146 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
264498 +CONFIG_BASE_SMALL=0
264832 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
265290 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
265291 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
266950 +CONFIG_JFFS2_FS_DEBUG=0
267327 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
267363 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
267367 +CONFIG_PANIC_TIMEOUT=0
267475 @@ -0,0 +1,3530 @@
267482 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
267486 +CONFIG_CLANG_VERSION=0
267649 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
268001 +CONFIG_BASE_SMALL=0
268335 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
268789 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
268790 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
270486 +CONFIG_JFFS2_FS_DEBUG=0
270863 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
270899 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
270903 +CONFIG_PANIC_TIMEOUT=0
271011 @@ -0,0 +1,3530 @@
271018 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
271022 +CONFIG_CLANG_VERSION=0
271185 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
271537 +CONFIG_BASE_SMALL=0
271871 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
272325 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
272326 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
274022 +CONFIG_JFFS2_FS_DEBUG=0
274399 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
274435 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
274439 +CONFIG_PANIC_TIMEOUT=0
274547 @@ -0,0 +1,3530 @@
274554 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
274558 +CONFIG_CLANG_VERSION=0
274721 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
275073 +CONFIG_BASE_SMALL=0
275407 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
275861 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
275862 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
277558 +CONFIG_JFFS2_FS_DEBUG=0
277935 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
277971 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
277975 +CONFIG_PANIC_TIMEOUT=0
278083 @@ -0,0 +1,3530 @@
278090 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
278094 +CONFIG_CLANG_VERSION=0
278257 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
278609 +CONFIG_BASE_SMALL=0
278943 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
279397 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
279398 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
281094 +CONFIG_JFFS2_FS_DEBUG=0
281471 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
281507 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
281511 +CONFIG_PANIC_TIMEOUT=0
281619 @@ -0,0 +1,3526 @@
281626 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
281630 +CONFIG_CLANG_VERSION=0
281793 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
282145 +CONFIG_BASE_SMALL=0
282479 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
282929 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
282930 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
284626 +CONFIG_JFFS2_FS_DEBUG=0
285003 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
285039 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
285043 +CONFIG_PANIC_TIMEOUT=0
285151 @@ -0,0 +1,3526 @@
285158 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
285162 +CONFIG_CLANG_VERSION=0
285325 +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
285677 +CONFIG_BASE_SMALL=0
286011 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
286461 +CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF
286462 +CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF
288158 +CONFIG_JFFS2_FS_DEBUG=0
288535 +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
288571 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
288575 +CONFIG_PANIC_TIMEOUT=0
288683 @@ -0,0 +1,24 @@
288704 +#define GET_SYS_BOOT_MODE(_reg) (((_reg) >> 4) & 0x3)
288705 +#define BOOT_FROM_SPI 0
288713 @@ -0,0 +1,25 @@
288740 index 0e2ea1c78..a078a4b0e 100644
288745 return 0;
288754 + dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
288756 + return 0;
288869 @@ -0,0 +1,44 @@
288882 + default "0x10390000" if (ARCH_HI3531DV200 || ARCH_HI3535AV100)
288883 + default "0x10390000" if (ARCH_HI3521DV200 || ARCH_HI3520DV500)
288890 + range 0 1
288899 + range 0 1
288946 +#define PCI_AHCI 0
289002 @@ -0,0 +1,174 @@
289033 + for (ix = 0; ix < size; ix += 0x04, addr++) {
289034 + if (!(ix & 0x0F))
289055 + for (ix = 0; ix <= 0x28; ix += 0x04) {
289056 + if (!(ix & 0x0F))
289061 + regbase = CONFIG_HISI_SATA_IOBASE + 0x0100;
289062 + pr_debug("AHCI PORT 0 Register dump:");
289063 + for (ix = 0; ix <= 0x7F; ix += 0x04) {
289064 + if (!(ix & 0x0F))
289095 + pr_debug("flags:0x%08lX, protocol:0x%02X, command:0x%02X, device:0x%02X, ctl:0x%02X\n",
289097 + pr_debug("feature:0x%08X, nsect:0x%02X, lbal:0x%02X, lbam:0x%02X, lbah:0x%02X\n",
289099 + pr_debug("hob_feature:0x%08X, hob_nsect:0x%02X, hob_lbal:0x%02X, hob_lbam:0x%02X, hob_lbah:0x%02X…
289114 + for (i = 0; i < 16; i++) {
289129 + tmp = readl(port_base + 0x58);
289130 + pr_debug("txdmac_curr_st:0x%2x\n", (tmp >> 24) & 0xf);
289131 + tmp = readl(port_base + 0x64);
289132 + pr_debug("rxdmac_curr_st:0x%2x\n", (tmp >> 24) & 0xf);
289133 + tmp = readl(port_base + 0x70);
289134 + pr_debug("dmac tx fifo:count-0x%x-empty-%x-ful-%x\n",
289135 + (tmp >> 0) & 0xff,
289136 + (tmp >> 16) & 0x1, (tmp >> 17) & 0x1);
289137 + pr_debug("dmac rx fifo:count-0x%x-empty-%x-ful-%x\n",
289138 + (tmp >> 8) & 0xff,
289139 + (tmp >> 18) & 0x1, (tmp >> 19) & 0x1);
289143 + tmp = readl(port_base + 0x50);
289144 + pr_debug("pxxx_curr_st:0x%2x ndrx_curr_st:0x%2x\n",
289145 + (tmp >> 24) & 0xf,
289146 + (tmp >> 16) & 0xff);
289147 + pr_debug("cfis_curr_st:0x%2x piox_curr_st:0x%2x\n",
289148 + (tmp >> 12) & 0xf,
289149 + (tmp >> 8) & 0xf);
289150 + pr_debug("pmxx_curr_st:0x%2x errx_curr_st:0x%2x\n",
289151 + (tmp >> 4) & 0xf,
289152 + (tmp >> 0) & 0xf);
289156 + tmp = readl(port_base + 0x54);
289157 + pr_debug("link_curr_st:0x%2x\n", (tmp >> 24) & 0x1f);
289158 + pr_debug("link tx fifo:count-0x%x-empty-%x-ful-%x\n",
289159 + (tmp >> 0) & 0x1f,
289160 + (tmp >> 5) & 0x1, (tmp >> 6) & 0x1);
289161 + pr_debug("link rx fifo:count-0x%x-empty-%x-ful-%x\n",
289162 + (tmp >> 8) & 0x1f,
289163 + (tmp >> 13) & 0x1, (tmp >> 14) & 0x1);
289164 + pr_debug("link df fifo:count-0x%x-empty-%x-ful-%x\n\n",
289165 + (tmp >> 16) & 0x1f,
289166 + (tmp >> 21) & 0x1, (tmp >> 22) & 0x1);
289169 + tmp = readl(port_base + 0x0);
289171 + __hisi_ahci_st_md(phys_to_virt(tmp + 0x100));
289172 + __hisi_ahci_st_md(phys_to_virt(tmp + 0x200));
289173 + __hisi_ahci_st_md(phys_to_virt(tmp + 0x300));
289182 @@ -0,0 +1,58 @@
289220 +} while (0)
289224 + pr_debug("HI_AHCI(REG) %s:%d: readl(0x%08X) = 0x%08X\n", \
289227 + } while (0)
289230 + pr_debug("HI_AHCI(REG) %s:%d: writel(0x%08X) = 0x%08X\n", \
289233 + } while (0)
289253 @@ -58,6 +59,33 @@ MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)
289255 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
289299 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
289320 + fbs_ctrl[port_num].fbs_enable_flag = 0;
289321 + fbs_ctrl[port_num].fbs_disable_flag = 0;
289322 + fbs_ctrl[port_num].fbs_cmd_issue_flag = 0;
289360 + cmd_timeout_count = 0;
289379 + ap->nr_active_links = 0;
289381 + fbs_ctrl[port_num].fbs_enable_flag = 0;
289382 + fbs_ctrl[ap->port_no].fbs_cmd_issue_flag = 0;
289386 + cmd_timeout_count = 0;
289401 + fbs_ctrl[port_num].fbs_enable_flag = 0;
289402 + fbs_ctrl[port_num].fbs_disable_flag = 0;
289493 + fbs_ctrl[port_num].fbs_disable_flag = 0;
289521 + fbs_ctrl[ap->port_no].fbs_enable_flag = 0;
289522 + fbs_ctrl[ap->port_no].fbs_disable_flag = 0;
289523 + fbs_ctrl[ap->port_no].fbs_cmd_issue_flag = 0;
289526 + timer_setup(&fbs_ctrl[ap->port_no].poll_timer, ahci_poll_timerout, 0);
289542 - for (unit = 0, cd = pcd; unit < PCD_UNITS; unit++, cd++)
289543 + for (unit = 0, cd = pcd; unit < PCD_UNITS; unit++, cd++) {
289557 for (unit = 0, cd = pcd; unit < PCD_UNITS; unit++, cd++) {
289569 pf_busy = 0;
289572 - for (pf = units, unit = 0; unit < PF_UNITS; pf++, unit++)
289573 + for (pf = units, unit = 0; unit < PF_UNITS; pf++, unit++) {
289854 @@ -0,0 +1,525 @@
289923 + { HI3516A_FIXED_3M, "3m", NULL, 0, 3000000, },
289924 + { HI3516A_FIXED_6M, "6m", NULL, 0, 6000000, },
289925 + { HI3516A_FIXED_13P5M, "13.5m", NULL, 0, 13500000, },
289926 + { HI3516A_FIXED_24M, "24m", NULL, 0, 24000000, },
289927 + { HI3516A_FIXED_25M, "25m", NULL, 0, 25000000, },
289928 + { HI3516A_FIXED_27M, "27m", NULL, 0, 27000000, },
289929 + { HI3516A_FIXED_37P125M, "37.125m", NULL, 0, 37125000, },
289930 + { HI3516A_FIXED_50M, "50m", NULL, 0, 50000000, },
289931 + { HI3516A_FIXED_74P25M, "74.25m", NULL, 0, 74250000, },
289932 + { HI3516A_FIXED_75M, "75m", NULL, 0, 75000000, },
289933 + { HI3516A_FIXED_99M, "99m", NULL, 0, 99000000, },
289934 + { HI3516A_FIXED_100M, "100m", NULL, 0, 100000000, },
289935 + { HI3516A_FIXED_125M, "125m", NULL, 0, 125000000, },
289936 + { HI3516A_FIXED_145M, "145m", NULL, 0, 145000000, },
289937 + { HI3516A_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
289938 + { HI3516A_FIXED_150M, "150m", NULL, 0, 150000000, },
289939 + { HI3516A_FIXED_194M, "194m", NULL, 0, 194000000, },
289940 + { HI3516A_FIXED_198M, "198m", NULL, 0, 198000000, },
289941 + { HI3516A_FIXED_200M, "200m", NULL, 0, 200000000, },
289942 + { HI3516A_FIXED_229M, "229m", NULL, 0, 229000000, },
289943 + { HI3516A_FIXED_237M, "237m", NULL, 0, 237000000, },
289944 + { HI3516A_FIXED_242M, "242m", NULL, 0, 242000000, },
289945 + { HI3516A_FIXED_250M, "250m", NULL, 0, 250000000, },
289946 + { HI3516A_FIXED_297M, "297m", NULL, 0, 297000000, },
289947 + { HI3516A_FIXED_300M, "300m", NULL, 0, 300000000, },
289948 + { HI3516A_FIXED_333M, "333m", NULL, 0, 333000000, },
289949 + { HI3516A_FIXED_400M, "400m", NULL, 0, 400000000, },
289950 + { HI3516A_FIXED_500M, "500m", NULL, 0, 500000000, },
289951 + { HI3516A_FIXED_594M, "594m", NULL, 0, 594000000, },
289952 + { HI3516A_FIXED_600M, "600m", NULL, 0, 600000000, },
289953 + { HI3516A_FIXED_726P25M, "725.25m", NULL, 0, 726250000, },
289954 + { HI3516A_FIXED_750M, "750m", NULL, 0, 750000000, },
289955 + { HI3516A_FIXED_900M, "900m", NULL, 0, 900000000, },
289956 + { HI3516A_FIXED_1000M, "1000m", NULL, 0, 1000000000UL, },
289957 + { HI3516A_FIXED_1188M, "1188m", NULL, 0, 1188000000UL, },
289969 +static u32 sysaxi_mux_table[] __initdata = {0, 1};
289970 +static u32 uart_mux_table[] __initdata = {0, 1};
289971 +static u32 snor_mux_table[] __initdata = {0, 1, 2};
289972 +static u32 snand_mux_table[] __initdata = {0, 1, 2};
289973 +static u32 nand_mux_table[] __initdata = {0, 1};
289974 +static u32 eth_phy_mux_table[] __initdata = {0, 1};
289975 +static u32 a7_mux_table[] __initdata = {2, 1, 0};
289976 +static u32 mmc_mux_table[] __initdata = {0, 1, 2, 3};
289982 + CLK_SET_RATE_PARENT, 0x30, 3, 1, 0, sysaxi_mux_table,
289986 + CLK_SET_RATE_PARENT, 0xc0, 2, 2, 0, snor_mux_table,
289990 + CLK_SET_RATE_PARENT, 0xc0, 6, 2, 0, snand_mux_table,
289994 + CLK_SET_RATE_PARENT, 0xd0, 2, 1, 0, nand_mux_table,
289998 + CLK_SET_RATE_PARENT, 0xc4, 2, 2, 0, mmc_mux_table,
290002 + CLK_SET_RATE_PARENT, 0xc4, 10, 2, 0, mmc_mux_table,
290007 + CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table,
290012 + 0xcc, 6, 1, 0, eth_phy_mux_table,
290016 + CLK_SET_RATE_PARENT, 0x30, 8, 2, 0, a7_mux_table,
290033 + CLK_SET_RATE_PARENT, 0xc0, 1, 0,
290038 + CLK_SET_RATE_PARENT, 0xc0, 5, 0,
290043 + CLK_SET_RATE_PARENT, 0xd8, 1, 0,
290048 + CLK_SET_RATE_PARENT, 0xc4, 1, 0,
290052 + CLK_SET_RATE_PARENT, 0xc4, 9, 0,
290058 + CLK_SET_RATE_PARENT, 0xb4, 5, 1,
290062 + CLK_SET_RATE_PARENT, 0xb4, 0, 1,
290068 + CLK_SET_RATE_PARENT, 0xe4, 15, 0,
290072 + CLK_SET_RATE_PARENT, 0xe4, 16, 0,
290076 + CLK_SET_RATE_PARENT, 0xe4, 17, 0,
290080 + CLK_SET_RATE_PARENT, 0xe4, 18, 0,
290085 + CLK_SET_RATE_PARENT, 0xcc, 1, 0,
290089 + CLK_SET_RATE_PARENT, 0xcc, 3, 0,
290094 + CLK_SET_RATE_PARENT, 0xe4, 13, 0,
290098 + CLK_SET_RATE_PARENT, 0xe4, 14, 0,
290103 + CLK_SET_RATE_PARENT, 0xd8, 5, 0,
290109 + HI3516A_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
290110 + 0x4, 0, 12, 12, 6
290121 + *frac_val = 0;
290138 + postdiv1_val = postdiv2_val = 0;
290161 + return 0;
290188 + rate = 0;
290214 + for (i = 0; i < nums; i++) {
290227 + init.num_parents = (clks[i].parent_name ? 1 : 0);
290256 + return 0;
290262 + unsigned int count = 0;
290328 +static u32 timer_mux_table[] __initdata = {0, 1};
290334 + 0x0, 16, 1, 0, timer_mux_table,
290340 + 0x0, 18, 1, 0, timer_mux_table,
290346 + 0x0, 20, 1, 0, timer_mux_table,
290352 + 0x0, 22, 1, 0, timer_mux_table,
290385 @@ -0,0 +1,261 @@
290414 + { HI3516CV500_FIXED_3M, "3m", NULL, 0, 3000000, },
290415 + { HI3516CV500_FIXED_6M, "6m", NULL, 0, 6000000, },
290416 + { HI3516CV500_FIXED_12M, "12m", NULL, 0, 12000000, },
290417 + { HI3516CV500_FIXED_24M, "24m", NULL, 0, 24000000, },
290418 + { HI3516CV500_FIXED_25M, "25m", NULL, 0, 25000000, },
290419 + { HI3516CV500_FIXED_50M, "50m", NULL, 0, 50000000, },
290420 + { HI3516CV500_FIXED_54M, "54m", NULL, 0, 54000000, },
290421 + { HI3516CV500_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
290422 + { HI3516CV500_FIXED_100M, "100m", NULL, 0, 100000000, },
290423 + { HI3516CV500_FIXED_125M, "125m", NULL, 0, 125000000, },
290424 + { HI3516CV500_FIXED_150M, "150m", NULL, 0, 150000000, },
290425 + { HI3516CV500_FIXED_163M, "163m", NULL, 0, 163000000, },
290426 + { HI3516CV500_FIXED_200M, "200m", NULL, 0, 200000000, },
290427 + { HI3516CV500_FIXED_250M, "250m", NULL, 0, 250000000, },
290428 + { HI3516CV500_FIXED_257M, "257m", NULL, 0, 257000000, },
290429 + { HI3516CV500_FIXED_300M, "300m", NULL, 0, 300000000, },
290430 + { HI3516CV500_FIXED_324M, "324m", NULL, 0, 324000000, },
290431 + { HI3516CV500_FIXED_342M, "342m", NULL, 0, 342000000, },
290432 + { HI3516CV500_FIXED_342M, "375m", NULL, 0, 375000000, },
290433 + { HI3516CV500_FIXED_396M, "396m", NULL, 0, 396000000, },
290434 + { HI3516CV500_FIXED_400M, "400m", NULL, 0, 400000000, },
290435 + { HI3516CV500_FIXED_448M, "448m", NULL, 0, 448000000, },
290436 + { HI3516CV500_FIXED_500M, "500m", NULL, 0, 500000000, },
290437 + { HI3516CV500_FIXED_540M, "540m", NULL, 0, 540000000, },
290438 + { HI3516CV500_FIXED_600M, "600m", NULL, 0, 600000000, },
290439 + { HI3516CV500_FIXED_750M, "750m", NULL, 0, 750000000, },
290440 + { HI3516CV500_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
290441 + { HI3516CV500_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
290453 +static u32 sysaxi_mux_table[] = {0, 1, 2};
290454 +static u32 sysapb_mux_table[] = {0, 1};
290455 +static u32 uart_mux_table[] = {0, 1};
290456 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
290457 +static u32 eth_mux_table[] = {0, 1};
290459 +static u32 pwm_mux_table[] = {0, 1, 2, 3};
290464 + CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table,
290469 + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
290473 + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
290477 + CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table,
290481 + CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table,
290485 + CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table,
290490 + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
290495 + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
290500 + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
290505 + CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table,
290510 + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
290515 + CLK_SET_RATE_PARENT, 0x1bc, 8, 2, 0, pwm_mux_table,
290530 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
290534 + CLK_SET_RATE_PARENT, 0x148, 1, 0,
290538 + CLK_SET_RATE_PARENT, 0x160, 1, 0,
290542 + CLK_SET_RATE_PARENT, 0x154, 1, 0,
290546 + CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
290550 + CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
290554 + CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
290558 + CLK_SET_RATE_PARENT, 0x1b8, 4, 0,
290562 + CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
290566 + CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
290570 + CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
290574 + CLK_SET_RATE_PARENT, 0x1b8, 14, 0,
290578 + CLK_SET_RATE_PARENT, 0x1b8, 15, 0,
290582 + CLK_SET_RATE_PARENT, 0x1b8, 16, 0,
290586 + CLK_SET_RATE_PARENT, 0x1b8, 17, 0,
290590 + CLK_SET_RATE_PARENT, 0x1b8, 18, 0,
290594 + CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
290598 + CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
290602 + CLK_SET_RATE_PARENT, 0x1bc, 14, 0,
290607 + CLK_SET_RATE_PARENT, 0x16c, 1, 0,
290611 + CLK_SET_RATE_PARENT, 0x194, 1, 0,
290615 + CLK_SET_RATE_PARENT, 0x194, 2, 0,
290619 + CLK_SET_RATE_PARENT, 0x1bc, 7, 0,
290652 @@ -0,0 +1,251 @@
290683 + { HI3516DV200_FIXED_100K, "100k", NULL, 0, 100000, },
290684 + { HI3516DV200_FIXED_400K, "400k", NULL, 0, 400000, },
290685 + { HI3516DV200_FIXED_3M, "3m", NULL, 0, 3000000, },
290686 + { HI3516DV200_FIXED_6M, "6m", NULL, 0, 6000000, },
290687 + { HI3516DV200_FIXED_12M, "12m", NULL, 0, 12000000, },
290688 + { HI3516DV200_FIXED_24M, "24m", NULL, 0, 24000000, },
290689 + { HI3516DV200_FIXED_25M, "25m", NULL, 0, 25000000, },
290690 + { HI3516DV200_FIXED_50M, "50m", NULL, 0, 50000000, },
290691 + { HI3516DV200_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
290692 + { HI3516DV200_FIXED_90M, "90m", NULL, 0, 90000000, },
290693 + { HI3516DV200_FIXED_100M, "100m", NULL, 0, 100000000, },
290694 + { HI3516DV200_FIXED_112M, "112m", NULL, 0, 112000000, },
290695 + { HI3516DV200_FIXED_125M, "125m", NULL, 0, 125000000, },
290696 + { HI3516DV200_FIXED_150M, "150m", NULL, 0, 150000000, },
290697 + { HI3516DV200_FIXED_200M, "200m", NULL, 0, 200000000, },
290698 + { HI3516DV200_FIXED_250M, "250m", NULL, 0, 250000000, },
290699 + { HI3516DV200_FIXED_300M, "300m", NULL, 0, 300000000, },
290700 + { HI3516DV200_FIXED_324M, "324m", NULL, 0, 324000000, },
290701 + { HI3516DV200_FIXED_342M, "342m", NULL, 0, 342000000, },
290702 + { HI3516DV200_FIXED_342M, "375m", NULL, 0, 375000000, },
290703 + { HI3516DV200_FIXED_400M, "400m", NULL, 0, 400000000, },
290704 + { HI3516DV200_FIXED_448M, "448m", NULL, 0, 448000000, },
290705 + { HI3516DV200_FIXED_500M, "500m", NULL, 0, 500000000, },
290706 + { HI3516DV200_FIXED_540M, "540m", NULL, 0, 540000000, },
290707 + { HI3516DV200_FIXED_600M, "600m", NULL, 0, 600000000, },
290708 + { HI3516DV200_FIXED_750M, "750m", NULL, 0, 750000000, },
290709 + { HI3516DV200_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
290710 + { HI3516DV200_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
290725 +static u32 sysaxi_mux_table[] = {0, 1};
290726 +static u32 sysapb_mux_table[] = {0, 1};
290727 +static u32 uart_mux_table[] = {0, 1};
290728 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
290729 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
290730 +static u32 eth_mux_table[] = {0, 1};
290731 +static u32 usb_mux_table[] = {0, 1};
290737 + CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table,
290742 + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
290746 + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
290750 + CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table,
290754 + CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table,
290759 + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
290764 + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
290769 + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
290773 + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
290777 + CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table
290793 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
290798 + CLK_SET_RATE_PARENT, 0x1f4, 28, 0,
290802 + CLK_SET_RATE_PARENT, 0x22c, 28, 0,
290807 + CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
290811 + CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
290815 + CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
290820 + CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
290824 + CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
290829 + CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
290833 + CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
290837 + CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
290842 + CLK_SET_RATE_PARENT, 0x16c, 1, 0,
290847 + CLK_SET_RATE_PARENT, 0x194, 2, 0,
290851 + CLK_SET_RATE_PARENT, 0x194, 1, 0,
290856 + CLK_SET_RATE_PARENT, 0x140, 8, 0,
290860 + CLK_SET_RATE_PARENT, 0x140, 9, 0,
290864 + CLK_SET_RATE_PARENT, 0x140, 12, 0,
290868 + CLK_SET_RATE_PARENT, 0x140, 11, 0,
290872 + CLK_SET_RATE_PARENT, 0x140, 4, 0,
290876 + CLK_SET_RATE_PARENT, 0x140, 2, 0,
290909 @@ -0,0 +1,271 @@
290938 + { HI3516DV300_FIXED_3M, "3m", NULL, 0, 3000000, },
290939 + { HI3516DV300_FIXED_6M, "6m", NULL, 0, 6000000, },
290940 + { HI3516DV300_FIXED_12M, "12m", NULL, 0, 12000000, },
290941 + { HI3516DV300_FIXED_24M, "24m", NULL, 0, 24000000, },
290942 + { HI3516DV300_FIXED_25M, "25m", NULL, 0, 25000000, },
290943 + { HI3516DV300_FIXED_50M, "50m", NULL, 0, 50000000, },
290944 + { HI3516DV300_FIXED_54M, "54m", NULL, 0, 54000000, },
290945 + { HI3516DV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
290946 + { HI3516DV300_FIXED_100M, "100m", NULL, 0, 100000000, },
290947 + { HI3516DV300_FIXED_125M, "125m", NULL, 0, 125000000, },
290948 + { HI3516DV300_FIXED_150M, "150m", NULL, 0, 150000000, },
290949 + { HI3516DV300_FIXED_163M, "163m", NULL, 0, 163000000, },
290950 + { HI3516DV300_FIXED_200M, "200m", NULL, 0, 200000000, },
290951 + { HI3516DV300_FIXED_250M, "250m", NULL, 0, 250000000, },
290952 + { HI3516DV300_FIXED_257M, "257m", NULL, 0, 257000000, },
290953 + { HI3516DV300_FIXED_300M, "300m", NULL, 0, 300000000, },
290954 + { HI3516DV300_FIXED_324M, "324m", NULL, 0, 324000000, },
290955 + { HI3516DV300_FIXED_342M, "342m", NULL, 0, 342000000, },
290956 + { HI3516DV300_FIXED_342M, "375m", NULL, 0, 375000000, },
290957 + { HI3516DV300_FIXED_396M, "396m", NULL, 0, 396000000, },
290958 + { HI3516DV300_FIXED_400M, "400m", NULL, 0, 400000000, },
290959 + { HI3516DV300_FIXED_448M, "448m", NULL, 0, 448000000, },
290960 + { HI3516DV300_FIXED_500M, "500m", NULL, 0, 500000000, },
290961 + { HI3516DV300_FIXED_540M, "540m", NULL, 0, 540000000, },
290962 + { HI3516DV300_FIXED_600M, "600m", NULL, 0, 600000000, },
290963 + { HI3516DV300_FIXED_750M, "750m", NULL, 0, 750000000, },
290964 + { HI3516DV300_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
290965 + { HI3516DV300_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
290978 +static u32 sysaxi_mux_table[] = {0, 1, 2};
290979 +static u32 sysapb_mux_table[] = {0, 1};
290980 +static u32 uart_mux_table[] = {0, 1};
290981 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
290982 +static u32 eth_mux_table[] = {0, 1};
290984 +static u32 pwm_mux_table[] = {0, 1, 2, 3};
290990 + CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table,
290995 + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
290999 + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
291003 + CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table,
291007 + CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table,
291011 + CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table,
291016 + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
291021 + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
291026 + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
291031 + CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table,
291036 + CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table,
291041 + CLK_SET_RATE_PARENT, 0x1bc, 8, 2, 0, pwm_mux_table,
291046 + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
291061 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
291065 + CLK_SET_RATE_PARENT, 0x148, 1, 0,
291069 + CLK_SET_RATE_PARENT, 0x160, 1, 0,
291073 + CLK_SET_RATE_PARENT, 0x154, 1, 0,
291077 + CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
291081 + CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
291085 + CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
291089 + CLK_SET_RATE_PARENT, 0x1b8, 3, 0,
291093 + CLK_SET_RATE_PARENT, 0x1b8, 4, 0,
291097 + CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
291101 + CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
291105 + CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
291109 + CLK_SET_RATE_PARENT, 0x1b8, 14, 0,
291113 + CLK_SET_RATE_PARENT, 0x1b8, 15, 0,
291117 + CLK_SET_RATE_PARENT, 0x1b8, 16, 0,
291121 + CLK_SET_RATE_PARENT, 0x1b8, 17, 0,
291125 + CLK_SET_RATE_PARENT, 0x1b8, 18, 0,
291129 + CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
291133 + CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
291137 + CLK_SET_RATE_PARENT, 0x1bc, 14, 0,
291141 + CLK_SET_RATE_PARENT, 0x16c, 1, 0,
291145 + CLK_SET_RATE_PARENT, 0x194, 1, 0,
291149 + CLK_SET_RATE_PARENT, 0x194, 2, 0,
291153 + CLK_SET_RATE_PARENT, 0x1bc, 7, 0,
291186 @@ -0,0 +1,244 @@
291217 + { HI3516EV200_FIXED_100K, "100k", NULL, 0, 100000, },
291218 + { HI3516EV200_FIXED_400K, "400k", NULL, 0, 400000, },
291219 + { HI3516EV200_FIXED_3M, "3m", NULL, 0, 3000000, },
291220 + { HI3516EV200_FIXED_6M, "6m", NULL, 0, 6000000, },
291221 + { HI3516EV200_FIXED_12M, "12m", NULL, 0, 12000000, },
291222 + { HI3516EV200_FIXED_24M, "24m", NULL, 0, 24000000, },
291223 + { HI3516EV200_FIXED_25M, "25m", NULL, 0, 25000000, },
291224 + { HI3516EV200_FIXED_50M, "50m", NULL, 0, 50000000, },
291225 + { HI3516EV200_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
291226 + { HI3516EV200_FIXED_90M, "90m", NULL, 0, 90000000, },
291227 + { HI3516EV200_FIXED_100M, "100m", NULL, 0, 100000000, },
291228 + { HI3516EV200_FIXED_112M, "112m", NULL, 0, 112000000, },
291229 + { HI3516EV200_FIXED_125M, "125m", NULL, 0, 125000000, },
291230 + { HI3516EV200_FIXED_150M, "150m", NULL, 0, 150000000, },
291231 + { HI3516EV200_FIXED_200M, "200m", NULL, 0, 200000000, },
291232 + { HI3516EV200_FIXED_250M, "250m", NULL, 0, 250000000, },
291233 + { HI3516EV200_FIXED_300M, "300m", NULL, 0, 300000000, },
291234 + { HI3516EV200_FIXED_324M, "324m", NULL, 0, 324000000, },
291235 + { HI3516EV200_FIXED_342M, "342m", NULL, 0, 342000000, },
291236 + { HI3516EV200_FIXED_342M, "375m", NULL, 0, 375000000, },
291237 + { HI3516EV200_FIXED_400M, "400m", NULL, 0, 400000000, },
291238 + { HI3516EV200_FIXED_448M, "448m", NULL, 0, 448000000, },
291239 + { HI3516EV200_FIXED_500M, "500m", NULL, 0, 500000000, },
291240 + { HI3516EV200_FIXED_540M, "540m", NULL, 0, 540000000, },
291241 + { HI3516EV200_FIXED_600M, "600m", NULL, 0, 600000000, },
291242 + { HI3516EV200_FIXED_750M, "750m", NULL, 0, 750000000, },
291243 + { HI3516EV200_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
291244 + { HI3516EV200_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
291259 +static u32 sysaxi_mux_table[] = {0, 1};
291260 +static u32 sysapb_mux_table[] = {0, 1};
291261 +static u32 uart_mux_table[] = {0, 1};
291262 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
291263 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
291264 +static u32 eth_mux_table[] = {0, 1};
291265 +static u32 usb_mux_table[] = {0, 1};
291271 + CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table,
291276 + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
291280 + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
291284 + CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table,
291288 + CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table,
291293 + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
291298 + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
291303 + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
291307 + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
291311 + CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table
291328 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
291332 + CLK_SET_RATE_PARENT, 0x1f4, 28, 0,
291336 + CLK_SET_RATE_PARENT, 0x22c, 28, 0,
291340 + CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
291344 + CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
291348 + CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
291352 + CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
291356 + CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
291360 + CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
291364 + CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
291368 + CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
291372 + CLK_SET_RATE_PARENT, 0x16c, 1, 0,
291376 + CLK_SET_RATE_PARENT, 0x194, 2, 0,
291380 + CLK_SET_RATE_PARENT, 0x194, 1, 0,
291384 + CLK_SET_RATE_PARENT, 0x140, 8, 0,
291388 + CLK_SET_RATE_PARENT, 0x140, 9, 0,
291392 + CLK_SET_RATE_PARENT, 0x140, 12, 0,
291396 + CLK_SET_RATE_PARENT, 0x140, 11, 0,
291400 + CLK_SET_RATE_PARENT, 0x140, 4, 0,
291404 + CLK_SET_RATE_PARENT, 0x140, 2, 0,
291436 @@ -0,0 +1,241 @@
291467 + { HI3516EV300_FIXED_100K, "100k", NULL, 0, 100000, },
291468 + { HI3516EV300_FIXED_400K, "400k", NULL, 0, 400000, },
291469 + { HI3516EV300_FIXED_3M, "3m", NULL, 0, 3000000, },
291470 + { HI3516EV300_FIXED_6M, "6m", NULL, 0, 6000000, },
291471 + { HI3516EV300_FIXED_12M, "12m", NULL, 0, 12000000, },
291472 + { HI3516EV300_FIXED_24M, "24m", NULL, 0, 24000000, },
291473 + { HI3516EV300_FIXED_25M, "25m", NULL, 0, 25000000, },
291474 + { HI3516EV300_FIXED_50M, "50m", NULL, 0, 50000000, },
291475 + { HI3516EV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
291476 + { HI3516EV300_FIXED_90M, "90m", NULL, 0, 90000000, },
291477 + { HI3516EV300_FIXED_100M, "100m", NULL, 0, 100000000, },
291478 + { HI3516EV300_FIXED_112M, "112m", NULL, 0, 112000000, },
291479 + { HI3516EV300_FIXED_125M, "125m", NULL, 0, 125000000, },
291480 + { HI3516EV300_FIXED_150M, "150m", NULL, 0, 150000000, },
291481 + { HI3516EV300_FIXED_200M, "200m", NULL, 0, 200000000, },
291482 + { HI3516EV300_FIXED_250M, "250m", NULL, 0, 250000000, },
291483 + { HI3516EV300_FIXED_300M, "300m", NULL, 0, 300000000, },
291484 + { HI3516EV300_FIXED_324M, "324m", NULL, 0, 324000000, },
291485 + { HI3516EV300_FIXED_342M, "342m", NULL, 0, 342000000, },
291486 + { HI3516EV300_FIXED_342M, "375m", NULL, 0, 375000000, },
291487 + { HI3516EV300_FIXED_400M, "400m", NULL, 0, 400000000, },
291488 + { HI3516EV300_FIXED_448M, "448m", NULL, 0, 448000000, },
291489 + { HI3516EV300_FIXED_500M, "500m", NULL, 0, 500000000, },
291490 + { HI3516EV300_FIXED_540M, "540m", NULL, 0, 540000000, },
291491 + { HI3516EV300_FIXED_600M, "600m", NULL, 0, 600000000, },
291492 + { HI3516EV300_FIXED_750M, "750m", NULL, 0, 750000000, },
291493 + { HI3516EV300_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
291494 + { HI3516EV300_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
291508 +static u32 sysaxi_mux_table[] = {0, 1};
291509 +static u32 sysapb_mux_table[] = {0, 1};
291510 +static u32 uart_mux_table[] = {0, 1};
291511 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
291512 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
291513 +static u32 eth_mux_table[] = {0, 1};
291514 +static u32 usb_mux_table[] = {0, 1};
291519 + CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table,
291524 + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
291528 + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
291532 + CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table,
291536 + CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table,
291541 + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
291546 + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
291551 + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
291555 + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
291559 + CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table
291574 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
291578 + CLK_SET_RATE_PARENT, 0x1f4, 28, 0,
291582 + CLK_SET_RATE_PARENT, 0x22c, 28, 0,
291586 + CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
291590 + CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
291594 + CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
291598 + CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
291602 + CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
291606 + CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
291610 + CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
291614 + CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
291618 + CLK_SET_RATE_PARENT, 0x16c, 1, 0,
291622 + CLK_SET_RATE_PARENT, 0x194, 2, 0,
291626 + CLK_SET_RATE_PARENT, 0x194, 1, 0,
291630 + CLK_SET_RATE_PARENT, 0x140, 8, 0,
291634 + CLK_SET_RATE_PARENT, 0x140, 9, 0,
291638 + CLK_SET_RATE_PARENT, 0x140, 12, 0,
291642 + CLK_SET_RATE_PARENT, 0x140, 11, 0,
291646 + CLK_SET_RATE_PARENT, 0x140, 4, 0,
291650 + CLK_SET_RATE_PARENT, 0x140, 2, 0,
291683 @@ -0,0 +1,291 @@
291717 + { HI3518EV20X_FIXED_3M, "3m", NULL, 0, 3000000, },
291718 + { HI3518EV20X_FIXED_6M, "6m", NULL, 0, 6000000, },
291719 + { HI3518EV20X_FIXED_24M, "24m", NULL, 0, 24000000, },
291720 + { HI3518EV20X_FIXED_25M, "25m", NULL, 0, 25000000, },
291721 + { HI3518EV20X_FIXED_27M, "27m", NULL, 0, 27000000, },
291722 + { HI3518EV20X_FIXED_37P125M, "37.125m", NULL, 0, 37125000, },
291723 + { HI3518EV20X_FIXED_49P5M, "49.5m", NULL, 0, 49500000, },
291724 + { HI3518EV20X_FIXED_50M, "50m", NULL, 0, 50000000, },
291725 + { HI3518EV20X_FIXED_54M, "54m", NULL, 0, 54000000, },
291726 + { HI3518EV20X_FIXED_74P25M, "74.25m", NULL, 0, 74250000, },
291727 + { HI3518EV20X_FIXED_99M, "99m", NULL, 0, 99000000, },
291728 + { HI3518EV20X_FIXED_125M, "125m", NULL, 0, 125000000, },
291729 + { HI3518EV20X_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
291730 + { HI3518EV20X_FIXED_198M, "198m", NULL, 0, 198000000, },
291731 + { HI3518EV20X_FIXED_200M, "200m", NULL, 0, 200000000, },
291732 + { HI3518EV20X_FIXED_250M, "250m", NULL, 0, 250000000, },
291733 + { HI3518EV20X_FIXED_297M, "297m", NULL, 0, 297000000, },
291734 + { HI3518EV20X_FIXED_300M, "300m", NULL, 0, 300000000, },
291735 + { HI3518EV20X_FIXED_396M, "396m", NULL, 0, 396000000, },
291736 + { HI3518EV20X_FIXED_540M, "540m", NULL, 0, 540000000, },
291737 + { HI3518EV20X_FIXED_594M, "594m", NULL, 0, 594000000, },
291738 + { HI3518EV20X_FIXED_600M, "600m", NULL, 0, 600000000, },
291739 + { HI3518EV20X_FIXED_650M, "660m", NULL, 0, 660000000, },
291740 + { HI3518EV20X_FIXED_750M, "750m", NULL, 0, 750000000, },
291741 + { HI3518EV20X_FIXED_1188M, "1188m", NULL, 0, 1188000000UL, },
291751 +static u32 sysapb_mux_table[] = {0, 1};
291752 +static u32 uart_mux_table[] = {0, 1, 2};
291753 +static u32 fmc_mux_table[] = {0, 1, 2, 3};
291754 +static u32 eth_mux_table[] = {0, 1};
291755 +static u32 mmc0_mux_table[] = {0, 1, 2, 3};
291756 +static u32 mmc1_mux_table[] = {0};
291762 + CLK_SET_RATE_PARENT, 0x30, 0, 1, 0, sysapb_mux_table,
291766 + CLK_SET_RATE_PARENT, 0xc0, 2, 2, 0, fmc_mux_table,
291771 + CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table,
291776 + CLK_SET_RATE_PARENT, 0xec, 7, 0, 0, eth_mux_table,
291781 + CLK_SET_RATE_PARENT, 0xc4, 10, 2, 0, mmc0_mux_table,
291786 + CLK_SET_RATE_PARENT, 0xc4, 2, 2, 0, mmc1_mux_table,
291803 + CLK_SET_RATE_PARENT, 0xc0, 1, 0,
291809 + CLK_SET_RATE_PARENT, 0xb4, 5, 1,
291813 + CLK_SET_RATE_PARENT, 0xb4, 0, 1,
291819 + CLK_SET_RATE_PARENT, 0xe4, 15, 0,
291823 + CLK_SET_RATE_PARENT, 0xe4, 16, 0,
291827 + CLK_SET_RATE_PARENT, 0xe4, 17, 0,
291832 + CLK_SET_RATE_PARENT, 0xec, 1, 0,
291837 + CLK_SET_RATE_PARENT, 0xc4, 9, 0,
291842 + CLK_SET_RATE_PARENT, 0xc4, 1, 0,
291847 + CLK_SET_RATE_PARENT, 0xe4, 13, 0,
291851 + CLK_SET_RATE_PARENT, 0xe4, 14, 0,
291856 + CLK_SET_RATE_PARENT, 0xd8, 5, 0,
291863 + unsigned int count = 0;
291924 +static u32 timer_mux_table[] __initdata = {0, 1};
291930 + 0x0, 16, 1, 0, timer_mux_table,
291936 + 0x0, 18, 1, 0, timer_mux_table,
291942 + 0x0, 20, 1, 0, timer_mux_table,
291948 + 0x0, 22, 1, 0, timer_mux_table,
291980 @@ -0,0 +1,240 @@
292011 + { HI3518EV300_FIXED_100K, "100k", NULL, 0, 100000, },
292012 + { HI3518EV300_FIXED_400K, "400k", NULL, 0, 400000, },
292013 + { HI3518EV300_FIXED_3M, "3m", NULL, 0, 3000000, },
292014 + { HI3518EV300_FIXED_6M, "6m", NULL, 0, 6000000, },
292015 + { HI3518EV300_FIXED_12M, "12m", NULL, 0, 12000000, },
292016 + { HI3518EV300_FIXED_24M, "24m", NULL, 0, 24000000, },
292017 + { HI3518EV300_FIXED_25M, "25m", NULL, 0, 25000000, },
292018 + { HI3518EV300_FIXED_50M, "50m", NULL, 0, 50000000, },
292019 + { HI3518EV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
292020 + { HI3518EV300_FIXED_90M, "90m", NULL, 0, 90000000, },
292021 + { HI3518EV300_FIXED_100M, "100m", NULL, 0, 100000000, },
292022 + { HI3518EV300_FIXED_112M, "112m", NULL, 0, 112000000, },
292023 + { HI3518EV300_FIXED_125M, "125m", NULL, 0, 125000000, },
292024 + { HI3518EV300_FIXED_150M, "150m", NULL, 0, 150000000, },
292025 + { HI3518EV300_FIXED_200M, "200m", NULL, 0, 200000000, },
292026 + { HI3518EV300_FIXED_250M, "250m", NULL, 0, 250000000, },
292027 + { HI3518EV300_FIXED_300M, "300m", NULL, 0, 300000000, },
292028 + { HI3518EV300_FIXED_324M, "324m", NULL, 0, 324000000, },
292029 + { HI3518EV300_FIXED_342M, "342m", NULL, 0, 342000000, },
292030 + { HI3518EV300_FIXED_342M, "375m", NULL, 0, 375000000, },
292031 + { HI3518EV300_FIXED_400M, "400m", NULL, 0, 400000000, },
292032 + { HI3518EV300_FIXED_448M, "448m", NULL, 0, 448000000, },
292033 + { HI3518EV300_FIXED_500M, "500m", NULL, 0, 500000000, },
292034 + { HI3518EV300_FIXED_540M, "540m", NULL, 0, 540000000, },
292035 + { HI3518EV300_FIXED_600M, "600m", NULL, 0, 600000000, },
292036 + { HI3518EV300_FIXED_750M, "750m", NULL, 0, 750000000, },
292037 + { HI3518EV300_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
292038 + { HI3518EV300_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
292052 +static u32 sysaxi_mux_table[] = {0, 1};
292053 +static u32 sysapb_mux_table[] = {0, 1};
292054 +static u32 uart_mux_table[] = {0, 1};
292055 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
292056 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
292057 +static u32 eth_mux_table[] = {0, 1};
292058 +static u32 usb_mux_table[] = {0, 1};
292063 + CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table,
292068 + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
292072 + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
292076 + CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table,
292080 + CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table,
292085 + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
292090 + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
292095 + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
292099 + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
292103 + CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table
292118 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
292122 + CLK_SET_RATE_PARENT, 0x1f4, 28, 0,
292126 + CLK_SET_RATE_PARENT, 0x22c, 28, 0,
292130 + CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
292134 + CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
292138 + CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
292142 + CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
292146 + CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
292150 + CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
292154 + CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
292158 + CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
292162 + CLK_SET_RATE_PARENT, 0x16c, 1, 0,
292166 + CLK_SET_RATE_PARENT, 0x194, 2, 0,
292170 + CLK_SET_RATE_PARENT, 0x194, 1, 0,
292174 + CLK_SET_RATE_PARENT, 0x140, 8, 0,
292178 + CLK_SET_RATE_PARENT, 0x140, 9, 0,
292182 + CLK_SET_RATE_PARENT, 0x140, 12, 0,
292186 + CLK_SET_RATE_PARENT, 0x140, 11, 0,
292190 + CLK_SET_RATE_PARENT, 0x140, 4, 0,
292194 + CLK_SET_RATE_PARENT, 0x140, 2, 0,
292226 @@ -0,0 +1,559 @@
292291 + HI3519AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
292292 + 0x4, 0, 12, 12, 6
292300 + { HI3519AV100_FIXED_2376M, "2376m", NULL, 0, 2376000000UL, },
292301 + { HI3519AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
292302 + { HI3519AV100_FIXED_594M, "594m", NULL, 0, 594000000, },
292303 + { HI3519AV100_FIXED_297M, "297m", NULL, 0, 297000000, },
292304 + { HI3519AV100_FIXED_148P5M, "148p5m", NULL, 0, 148500000, },
292305 + { HI3519AV100_FIXED_74P25M, "74p25m", NULL, 0, 74250000, },
292306 + { HI3519AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
292307 + { HI3519AV100_FIXED_475M, "475m", NULL, 0, 475000000, },
292308 + { HI3519AV100_FIXED_340M, "340m", NULL, 0, 340000000, },
292309 + { HI3519AV100_FIXED_72M, "72m", NULL, 0, 72000000, },
292310 + { HI3519AV100_FIXED_400M, "400m", NULL, 0, 400000000, },
292311 + { HI3519AV100_FIXED_200M, "200m", NULL, 0, 200000000, },
292312 + { HI3519AV100_FIXED_54M, "54m", NULL, 0, 54000000, },
292313 + { HI3519AV100_FIXED_27M, "27m", NULL, 0, 1188000000, },
292314 + { HI3519AV100_FIXED_37P125M, "37p125m", NULL, 0, 37125000, },
292315 + { HI3519AV100_FIXED_3000M, "3000m", NULL, 0, 3000000000UL, },
292316 + { HI3519AV100_FIXED_1500M, "1500m", NULL, 0, 1500000000, },
292317 + { HI3519AV100_FIXED_500M, "500m", NULL, 0, 500000000, },
292318 + { HI3519AV100_FIXED_250M, "250m", NULL, 0, 250000000, },
292319 + { HI3519AV100_FIXED_125M, "125m", NULL, 0, 125000000, },
292320 + { HI3519AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
292321 + { HI3519AV100_FIXED_600M, "600m", NULL, 0, 600000000, },
292322 + { HI3519AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
292323 + { HI3519AV100_FIXED_150M, "150m", NULL, 0, 150000000, },
292324 + { HI3519AV100_FIXED_75M, "75m", NULL, 0, 75000000, },
292325 + { HI3519AV100_FIXED_300M, "300m", NULL, 0, 300000000, },
292326 + { HI3519AV100_FIXED_60M, "60m", NULL, 0, 60000000, },
292327 + { HI3519AV100_FIXED_214M, "214m", NULL, 0, 214000000, },
292328 + { HI3519AV100_FIXED_107M, "107m", NULL, 0, 107000000, },
292329 + { HI3519AV100_FIXED_100M, "100m", NULL, 0, 100000000, },
292330 + { HI3519AV100_FIXED_50M, "50m", NULL, 0, 50000000, },
292331 + { HI3519AV100_FIXED_25M, "25m", NULL, 0, 25000000, },
292332 + { HI3519AV100_FIXED_24M, "24m", NULL, 0, 24000000, },
292333 + { HI3519AV100_FIXED_3M, "3m", NULL, 0, 3000000, },
292334 + { HI3519AV100_FIXED_100K, "100k", NULL, 0, 100000, },
292335 + { HI3519AV100_FIXED_400K, "400k", NULL, 0, 400000, },
292336 + { HI3519AV100_FIXED_49P5M, "49p5m", NULL, 0, 49500000, },
292337 + { HI3519AV100_FIXED_99M, "99m", NULL, 0, 99000000, },
292338 + { HI3519AV100_FIXED_187P5M, "187p5m", NULL, 0, 187500000, },
292339 + { HI3519AV100_FIXED_198M, "198m", NULL, 0, 198000000, },
292346 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
292351 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
292356 +static u32 sysapb_mux_table[] = {0, 1};
292361 +static u32 sysbus_mux_table[] = {0, 1};
292364 +static u32 uart_mux_table[] = {0, 1, 2};
292369 +static u32 a53_1_clksel_mux_table[] = {0, 1, 2, 3};
292374 + CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
292379 + CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
292384 + CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
292389 + CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
292394 + CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
292399 + CLK_SET_RATE_PARENT, 0xe8, 0, 1, 1, sysbus_mux_table
292404 + CLK_SET_RATE_PARENT, 0x1a4, 0, 2, 1, uart_mux_table
292409 + CLK_SET_RATE_PARENT, 0x1a4, 2, 2, 1, uart_mux_table
292414 + CLK_SET_RATE_PARENT, 0x1a4, 4, 2, 1, uart_mux_table
292419 + CLK_SET_RATE_PARENT, 0x1a4, 6, 2, 1, uart_mux_table
292424 + CLK_SET_RATE_PARENT, 0x1a4, 8, 2, 1, uart_mux_table
292429 + CLK_SET_RATE_PARENT, 0x1a4, 10, 2, 1, uart_mux_table
292434 + CLK_SET_RATE_PARENT, 0x1a4, 12, 2, 1, uart_mux_table
292439 + CLK_SET_RATE_PARENT, 0x1a4, 14, 2, 1, uart_mux_table
292444 + CLK_SET_RATE_PARENT, 0x1a4, 28, 2, 1, uart_mux_table
292449 + CLK_SET_RATE_PARENT, 0xe4, 10, 2, 3, a53_1_clksel_mux_table
292462 + CLK_SET_RATE_PARENT, 0x170, 1, 0,
292466 + CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
292470 + CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
292474 + CLK_SET_RATE_PARENT, 0x214, 28, 0,
292478 + CLK_SET_RATE_PARENT, 0x198, 16, 0,
292482 + CLK_SET_RATE_PARENT, 0x198, 17, 0,
292486 + CLK_SET_RATE_PARENT, 0x198, 18, 0,
292490 + CLK_SET_RATE_PARENT, 0x198, 19, 0,
292494 + CLK_SET_RATE_PARENT, 0x198, 20, 0,
292498 + CLK_SET_RATE_PARENT, 0x198, 21, 0,
292502 + CLK_SET_RATE_PARENT, 0x198, 22, 0,
292506 + CLK_SET_RATE_PARENT, 0x198, 23, 0,
292510 + CLK_SET_RATE_PARENT, 0x198, 29, 0,
292514 + CLK_SET_RATE_PARENT, 0x0174, 1, 0,
292518 + CLK_SET_RATE_PARENT, 0x0174, 5, 0,
292523 + CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
292527 + CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
292531 + CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
292535 + CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
292539 + CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
292543 + CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
292547 + CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
292551 + CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
292555 + CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
292559 + CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
292563 + CLK_SET_RATE_PARENT, 0x0198, 24, 0,
292567 + CLK_SET_RATE_PARENT, 0x0198, 25, 0,
292571 + CLK_SET_RATE_PARENT, 0x0198, 26, 0,
292575 + CLK_SET_RATE_PARENT, 0x0198, 27, 0,
292579 + CLK_SET_RATE_PARENT, 0x0198, 28, 0,
292583 + CLK_SET_RATE_PARENT, 0x16c, 6, 0,
292587 + CLK_SET_RATE_PARENT, 0x16c, 5, 0,
292591 + CLK_SET_RATE_PARENT, 0x16c, 9, 0,
292595 + CLK_SET_RATE_PARENT, 0x16c, 8, 0,
292599 + CLK_SET_RATE_PARENT, 0x14c, 5, 0,
292611 + *frac_val = 0;
292632 + postdiv1_val = postdiv2_val = 0;
292655 + return 0;
292683 + rate = 0;
292686 + return 0;
292717 + for (i = 0; i < nums; i++) {
292730 + init.num_parents = (clks[i].parent_name ? 1 : 0);
292791 @@ -0,0 +1,288 @@
292825 + { HI3521A_FIXED_2M, "2m", NULL, 0, 2000000, },
292826 + { HI3521A_FIXED_2P2M, "2.2m", NULL, 0, 2200000, },
292827 + { HI3521A_FIXED_2P5M, "2.5m", NULL, 0, 2500000, },
292828 + { HI3521A_FIXED_2P5M, "3m", NULL, 0, 3000000, },
292829 + { HI3521A_FIXED_24M, "24m", NULL, 0, 24000000, },
292830 + { HI3521A_FIXED_25M, "25m", NULL, 0, 25000000, },
292831 + { HI3521A_FIXED_27M, "27m", NULL, 0, 27000000, },
292832 + { HI3521A_FIXED_50M, "50m", NULL, 0, 50000000, },
292833 + { HI3521A_FIXED_54M, "54m", NULL, 0, 54000000, },
292834 + { HI3521A_FIXED_60M, "60m", NULL, 0, 60000000, },
292835 + { HI3521A_FIXED_62P5M, "62.5m", NULL, 0, 62500000, },
292836 + { HI3521A_FIXED_75M, "75m", NULL, 0, 75000000, },
292837 + { HI3521A_FIXED_83M, "83m", NULL, 0, 83000000, },
292838 + { HI3521A_FIXED_100M, "100m", NULL, 0, 100000000, },
292839 + { HI3521A_FIXED_125M, "125m", NULL, 0, 125000000, },
292840 + { HI3521A_FIXED_150M, "150m", NULL, 0, 150000000, },
292841 + { HI3521A_FIXED_162M, "162m", NULL, 0, 162000000, },
292842 + { HI3521A_FIXED_187M, "187m", NULL, 0, 187000000, },
292843 + { HI3521A_FIXED_187P5M, "187.5m", NULL, 0, 187500000, },
292844 + { HI3521A_FIXED_202P5M, "202.5m", NULL, 0, 202500000, },
292845 + { HI3521A_FIXED_250M, "250m", NULL, 0, 250000000, },
292846 + { HI3521A_FIXED_270M, "270m", NULL, 0, 270000000, },
292847 + { HI3521A_FIXED_300M, "300m", NULL, 0, 300000000, },
292848 + { HI3521A_FIXED_324M, "324m", NULL, 0, 324000000, },
292849 + { HI3521A_FIXED_375M, "375m", NULL, 0, 375000000, },
292850 + { HI3521A_FIXED_400M, "400m", NULL, 0, 400000000, },
292851 + { HI3521A_FIXED_405M, "405m", NULL, 0, 405000000, },
292852 + { HI3521A_FIXED_500M, "500m", NULL, 0, 500000000, },
292853 + { HI3521A_FIXED_750M, "750m", NULL, 0, 750000000, },
292854 + { HI3521A_FIXED_800M, "800m", NULL, 0, 800000000, },
292855 + { HI3521A_FIXED_810M, "810m", NULL, 0, 810000000, },
292856 + { HI3521A_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
292857 + { HI3521A_FIXED_1620M, "1620m", NULL, 0, 1620000000UL, },
292865 +static u32 sysaxi_mux_table[] __initdata = {0, 1, 2};
292866 +static u32 uart_mux_table[] __initdata = {0, 1, 2};
292867 +static u32 fmc_mux_table[] __initdata = {0, 1, 2};
292868 +static u32 eth_phy_mux_table[] __initdata = {0, 1};
292874 + CLK_SET_RATE_PARENT, 0x34, 12, 2, 0, sysaxi_mux_table,
292878 + CLK_SET_RATE_PARENT, 0x74, 2, 2, 0, fmc_mux_table,
292882 + CLK_SET_RATE_PARENT, 0x84, 18, 2, 0, uart_mux_table,
292887 + CLK_SET_RATE_PARENT, 0x78, 6, 1, 0, eth_phy_mux_table,
292904 + CLK_SET_RATE_PARENT, 0x74, 1, 0,
292910 + CLK_SET_RATE_PARENT, 0x84, 15, 0,
292914 + CLK_SET_RATE_PARENT, 0x84, 16, 0,
292918 + CLK_SET_RATE_PARENT, 0x84, 17, 0,
292923 + CLK_SET_RATE_PARENT, 0x78, 1, 0,
292927 + CLK_SET_RATE_PARENT, 0x78, 3, 0,
292932 + CLK_SET_RATE_PARENT, 0x84, 13, 0,
292937 + CLK_SET_RATE_PARENT, 0x80, 5, 0,
292944 + unsigned int count = 0;
293005 +static u32 timer_mux_table[] __initdata = {0, 1};
293011 + 0x0, 16, 1, 0, timer_mux_table,
293017 + 0x0, 18, 1, 0, timer_mux_table,
293023 + 0x0, 20, 1, 0, timer_mux_table,
293029 + 0x0, 22, 1, 0, timer_mux_table,
293035 + 0x0, 25, 1, 0, timer_mux_table,
293041 + 0x0, 27, 1, 0, timer_mux_table,
293047 + 0x0, 29, 1, 0, timer_mux_table,
293053 + 0x0, 31, 1, 0, timer_mux_table,
293085 @@ -0,0 +1,255 @@
293116 + { HI3521DV200_FIXED_100K, "100k", NULL, 0, 100000, },
293117 + { HI3521DV200_FIXED_400K, "400k", NULL, 0, 400000, },
293118 + { HI3521DV200_FIXED_3M, "3m", NULL, 0, 3000000, },
293119 + { HI3521DV200_FIXED_6M, "6m", NULL, 0, 6000000, },
293120 + { HI3521DV200_FIXED_24M, "24m", NULL, 0, 24000000, },
293121 + { HI3521DV200_FIXED_24P75M, "24p75m", NULL, 0, 24750000, },
293122 + { HI3521DV200_FIXED_49P5M, "49p5m", NULL, 0, 49500000, },
293123 + { HI3521DV200_FIXED_50M, "50m", NULL, 0, 50000000, },
293124 + { HI3521DV200_FIXED_54M, "54m", NULL, 0, 54000000, },
293125 + { HI3521DV200_FIXED_90M, "90m", NULL, 0, 90000000, },
293126 + { HI3521DV200_FIXED_99M, "99m", NULL, 0, 99000000, },
293127 + { HI3521DV200_FIXED_112M, "112m", NULL, 0, 112000000, },
293128 + { HI3521DV200_FIXED_125M, "125m", NULL, 0, 125000000, },
293129 + { HI3521DV200_FIXED_148P5M, "148p5m", NULL, 0, 148500000, },
293130 + { HI3521DV200_FIXED_198M, "198m", NULL, 0, 198000000, },
293131 + { HI3521DV200_FIXED_250M, "250m", NULL, 0, 250000000, },
293132 + { HI3521DV200_FIXED_297M, "297m", NULL, 0, 297000000, },
293133 + { HI3521DV200_FIXED_324M, "324m", NULL, 0, 324000000, },
293134 + { HI3521DV200_FIXED_342M, "342m", NULL, 0, 342000000, },
293135 + { HI3521DV200_FIXED_342M, "375m", NULL, 0, 375000000, },
293136 + { HI3521DV200_FIXED_396M, "396m", NULL, 0, 396000000, },
293137 + { HI3521DV200_FIXED_448M, "448m", NULL, 0, 448000000, },
293138 + { HI3521DV200_FIXED_500M, "500m", NULL, 0, 500000000, },
293139 + { HI3521DV200_FIXED_540M, "540m", NULL, 0, 540000000, },
293140 + { HI3521DV200_FIXED_600M, "600m", NULL, 0, 600000000, },
293141 + { HI3521DV200_FIXED_750M, "750m", NULL, 0, 750000000, },
293142 + { HI3521DV200_FIXED_900M, "900m", NULL, 0, 900000000, },
293143 + { HI3521DV200_FIXED_1200M, "1200m", NULL, 0, 1200000000UL, },
293148 +static u32 sysaxi_mux_table[] = {0, 1, 2, 3};
293151 +static u32 syscfg_mux_table[] = {0, 1, 2};
293156 +static u32 fmc_mux_table[] = {0, 1, 3, 4, 5, 6, 7};
293161 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
293164 +static u32 eth_mux_table[] = {0, 1};
293167 +static u32 uart_mux_table[] = {0, 1, 2};
293170 +static u32 i2c_mux_table[] = {0, 1};
293176 + CLK_SET_RATE_PARENT, 0x2000, 0, 2, 0, sysaxi_mux_table,
293181 + CLK_SET_RATE_PARENT, 0x2000, 4, 2, 0, syscfg_mux_table,
293186 + CLK_SET_RATE_PARENT, 0x3f40, 12, 3, 0, fmc_mux_table,
293191 + CLK_SET_RATE_PARENT, 0x34c0, 24, 3, 0, mmc_mux_table,
293196 + CLK_SET_RATE_PARENT, 0x37c8, 12, 1, 0, eth_mux_table,
293202 + CLK_SET_RATE_PARENT, 0x4180, 12, 2, 0, uart_mux_table,
293207 + CLK_SET_RATE_PARENT, 0x4188, 12, 2, 0, uart_mux_table,
293212 + CLK_SET_RATE_PARENT, 0x4190, 12, 2, 0, uart_mux_table,
293217 + CLK_SET_RATE_PARENT, 0x4198, 12, 2, 0, uart_mux_table,
293222 + CLK_SET_RATE_PARENT, 0x41a0, 12, 2, 0, uart_mux_table,
293227 + CLK_SET_RATE_PARENT, 0x4280, 12, 1, 0, i2c_mux_table,
293232 + CLK_SET_RATE_PARENT, 0x4288, 12, 1, 0, i2c_mux_table,
293247 + CLK_SET_RATE_PARENT, 0x3f40, 4, 0,
293251 + CLK_SET_RATE_PARENT, 0x34c0, 0, 0,
293255 + CLK_SET_RATE_PARENT, 0x4180, 4, 0,
293259 + CLK_SET_RATE_PARENT, 0x4188, 4, 0,
293263 + CLK_SET_RATE_PARENT, 0x4190, 4, 0,
293267 + CLK_SET_RATE_PARENT, 0x4198, 4, 0,
293271 + CLK_SET_RATE_PARENT, 0x41a0, 4, 0,
293275 + CLK_SET_RATE_PARENT, 0x4280, 4, 0,
293279 + CLK_SET_RATE_PARENT, 0x4288, 4, 0,
293283 + CLK_SET_RATE_PARENT, 0x4480, 4, 0,
293287 + CLK_SET_RATE_PARENT, 0x4488, 4, 0,
293291 + CLK_SET_RATE_PARENT, 0x37c4, 4, 0,
293295 + CLK_SET_RATE_PARENT, 0x37c0, 4, 0,
293299 + CLK_SET_RATE_PARENT, 0x37c8, 4, 0,
293303 + CLK_SET_RATE_PARENT, 0x37d0, 4, 0,
293307 + CLK_SET_RATE_PARENT, 0x2a80, 5, 0,
293311 + CLK_SET_RATE_PARENT, 0x2a80, 4, 0,
293346 @@ -0,0 +1,323 @@
293380 + { HI3531A_FIXED_2M, "2m", NULL, 0, 2000000, },
293381 + { HI3531A_FIXED_2P02M, "2.02m", NULL, 0, 2020000, },
293382 + { HI3531A_FIXED_2P5M, "2.5m", NULL, 0, 2500000, },
293383 + { HI3531A_FIXED_3M, "3m", NULL, 0, 3000000, },
293384 + { HI3531A_FIXED_24M, "24m", NULL, 0, 24000000, },
293385 + { HI3531A_FIXED_25M, "25m", NULL, 0, 25000000, },
293386 + { HI3531A_FIXED_27M, "27m", NULL, 0, 27000000, },
293387 + { HI3531A_FIXED_37P125M, "37.125m", NULL, 0, 37125000, },
293388 + { HI3531A_FIXED_37P5M, "37.5m", NULL, 0, 37500000, },
293389 + { HI3531A_FIXED_40P5M, "40.5m", NULL, 0, 40500000, },
293390 + { HI3531A_FIXED_48M, "48m", NULL, 0, 48000000, },
293391 + { HI3531A_FIXED_50M, "50m", NULL, 0, 50000000, },
293392 + { HI3531A_FIXED_54M, "54m", NULL, 0, 54000000, },
293393 + { HI3531A_FIXED_59P2M, "59.2m", NULL, 0, 59200000, },
293394 + { HI3531A_FIXED_60M, "60m", NULL, 0, 60000000, },
293395 + { HI3531A_FIXED_62P5M, "62.5m", NULL, 0, 62500000, },
293396 + { HI3531A_FIXED_74P25M, "75.25m", NULL, 0, 74250000, },
293397 + { HI3531A_FIXED_75M, "75m", NULL, 0, 75000000, },
293398 + { HI3531A_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
293399 + { HI3531A_FIXED_100M, "100m", NULL, 0, 100000000, },
293400 + { HI3531A_FIXED_125M, "125m", NULL, 0, 125000000, },
293401 + { HI3531A_FIXED_150M, "150m", NULL, 0, 150000000, },
293402 + { HI3531A_FIXED_187P5M, "187.5m", NULL, 0, 187500000, },
293403 + { HI3531A_FIXED_200M, "200m", NULL, 0, 200000000, },
293404 + { HI3531A_FIXED_250M, "250m", NULL, 0, 250000000, },
293405 + { HI3531A_FIXED_300M, "300m", NULL, 0, 300000000, },
293406 + { HI3531A_FIXED_324M, "324m", NULL, 0, 324000000, },
293407 + { HI3531A_FIXED_355M, "355m", NULL, 0, 355000000, },
293408 + { HI3531A_FIXED_400M, "400m", NULL, 0, 400000000, },
293409 + { HI3531A_FIXED_433M, "433m", NULL, 0, 433000000, },
293410 + { HI3531A_FIXED_500M, "500m", NULL, 0, 500000000, },
293411 + { HI3531A_FIXED_750M, "750m", NULL, 0, 750000000, },
293412 + { HI3531A_FIXED_800M, "800m", NULL, 0, 800000000, },
293413 + { HI3531A_FIXED_1000M, "1000m", NULL, 0, 1000000000UL, },
293414 + { HI3531A_FIXED_1420M, "1420m", NULL, 0, 1420000000UL, },
293415 + { HI3531A_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
293425 +static u32 sysaxi_mux_table[] __initdata = {0, 1, 2};
293426 +static u32 periaxi_mux_table[] __initdata = {0, 1, 2};
293427 +static u32 uart_mux_table[] __initdata = {0, 1, 2};
293428 +static u32 fmc_mux_table[] __initdata = {0, 1, 2};
293429 +static u32 nfc_mux_table[] __initdata = {0, 1};
293430 +static u32 eth_phy_mux_table[] __initdata = {0, 1};
293437 + CLK_SET_RATE_PARENT, 0x50, 0, 2, 0, periaxi_mux_table,
293442 + CLK_SET_RATE_PARENT, 0x50, 2, 2, 0, sysaxi_mux_table,
293447 + CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, fmc_mux_table,
293452 + CLK_SET_RATE_PARENT, 0x13c, 2, 1, 0, nfc_mux_table,
293457 + CLK_SET_RATE_PARENT, 0x154, 19, 2, 0, uart_mux_table,
293463 + CLK_SET_RATE_PARENT, 0x14c, 6, 1, 0, eth_phy_mux_table,
293484 + CLK_SET_RATE_PARENT, 0x148, 1, 0,
293490 + CLK_SET_RATE_PARENT, 0x13c, 1, 0,
293496 + CLK_SET_RATE_PARENT, 0x154, 15, 0,
293500 + CLK_SET_RATE_PARENT, 0x154, 16, 0,
293504 + CLK_SET_RATE_PARENT, 0x154, 17, 0,
293508 + CLK_SET_RATE_PARENT, 0x154, 18, 0,
293513 + CLK_SET_RATE_PARENT, 0x14c, 1, 0,
293517 + CLK_SET_RATE_PARENT, 0x14c, 3, 0,
293522 + CLK_SET_RATE_PARENT, 0x154, 13, 0,
293527 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
293534 + unsigned int count = 0;
293595 +static u32 timer_mux_table[] __initdata = {0, 1};
293601 + 0x0, 16, 1, 0, timer_mux_table,
293607 + 0x0, 18, 1, 0, timer_mux_table,
293613 + 0x0, 20, 1, 0, timer_mux_table,
293619 + 0x0, 22, 1, 0, timer_mux_table,
293625 + 0x0, 25, 1, 0, timer_mux_table,
293631 + 0x0, 27, 1, 0, timer_mux_table,
293637 + 0x0, 29, 1, 0, timer_mux_table,
293643 + 0x0, 31, 1, 0, timer_mux_table,
293672 index 000000000..0b5b4dfeb
293675 @@ -0,0 +1,578 @@
293744 + { HI3531DV200_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
293745 + { HI3531DV200_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
293746 + { HI3531DV200_FIXED_842M, "842m", NULL, 0, 842000000, },
293747 + { HI3531DV200_FIXED_792M, "792m", NULL, 0, 792000000, },
293748 + { HI3531DV200_FIXED_750M, "750m", NULL, 0, 750000000, },
293749 + { HI3531DV200_FIXED_710M, "710m", NULL, 0, 710000000, },
293750 + { HI3531DV200_FIXED_680M, "680m", NULL, 0, 680000000, },
293751 + { HI3531DV200_FIXED_667M, "667m", NULL, 0, 667000000, },
293752 + { HI3531DV200_FIXED_631M, "631m", NULL, 0, 631000000, },
293753 + { HI3531DV200_FIXED_600M, "600m", NULL, 0, 600000000, },
293754 + { HI3531DV200_FIXED_568M, "568m", NULL, 0, 568000000, },
293755 + { HI3531DV200_FIXED_500M, "500m", NULL, 0, 500000000, },
293756 + { HI3531DV200_FIXED_475M, "475m", NULL, 0, 475000000, },
293757 + { HI3531DV200_FIXED_428M, "428m", NULL, 0, 428000000, },
293758 + { HI3531DV200_FIXED_400M, "400m", NULL, 0, 400000000, },
293759 + { HI3531DV200_FIXED_396M, "396m", NULL, 0, 396000000, },
293760 + { HI3531DV200_FIXED_300M, "300m", NULL, 0, 300000000, },
293761 + { HI3531DV200_FIXED_297M, "297m", NULL, 0, 297000000, },
293762 + { HI3531DV200_FIXED_257M, "257m", NULL, 0, 257000000, },
293763 + { HI3531DV200_FIXED_250M, "250m", NULL, 0, 250000000, },
293764 + { HI3531DV200_FIXED_200M, "200m", NULL, 0, 200000000, },
293765 + { HI3531DV200_FIXED_198M, "198m", NULL, 0, 198000000, },
293766 + { HI3531DV200_FIXED_196p5M, "196p5m", NULL, 0, 196500000, },
293767 + { HI3531DV200_FIXED_187p5M, "187p5m", NULL, 0, 187500000, },
293768 + { HI3531DV200_FIXED_175M, "175m", NULL, 0, 175000000, },
293769 + { HI3531DV200_FIXED_163M, "163m", NULL, 0, 163000000, },
293770 + { HI3531DV200_FIXED_150M, "150m", NULL, 0, 150000000, },
293771 + { HI3531DV200_FIXED_148p5M, "148p5m", NULL, 0, 148500000, },
293772 + { HI3531DV200_FIXED_125M, "125m", NULL, 0, 125000000, },
293773 + { HI3531DV200_FIXED_107M, "107m", NULL, 0, 107000000, },
293774 + { HI3531DV200_FIXED_100M, "100m", NULL, 0, 100000000, },
293775 + { HI3531DV200_FIXED_99M, "99m", NULL, 0, 99000000, },
293776 + { HI3531DV200_FIXED_75M, "75m", NULL, 0, 75000000, },
293777 + { HI3531DV200_FIXED_74p25M, "74p25m", NULL, 0, 74250000, },
293778 + { HI3531DV200_FIXED_72M, "72m", NULL, 0, 72000000, },
293779 + { HI3531DV200_FIXED_60M, "60m", NULL, 0, 60000000, },
293780 + { HI3531DV200_FIXED_54M, "54m", NULL, 0, 54000000, },
293781 + { HI3531DV200_FIXED_50M, "50m", NULL, 0, 50000000, },
293782 + { HI3531DV200_FIXED_49p5M, "49p5m", NULL, 0, 49500000, },
293783 + { HI3531DV200_FIXED_37p125M, "37p125m", NULL, 0, 37125000, },
293784 + { HI3531DV200_FIXED_36M, "36m", NULL, 0, 36000000, },
293785 + { HI3531DV200_FIXED_32p4M, "32p4m", NULL, 0, 32400000, },
293786 + { HI3531DV200_FIXED_27M, "27m", NULL, 0, 27000000, },
293787 + { HI3531DV200_FIXED_25M, "25m", NULL, 0, 25000000, },
293788 + { HI3531DV200_FIXED_24M, "24m", NULL, 0, 24000000, },
293789 + { HI3531DV200_FIXED_12M, "12m", NULL, 0, 12000000, },
293790 + { HI3531DV200_FIXED_3M, "3m", NULL, 0, 3000000, },
293791 + { HI3531DV200_FIXED_1p6M, "1p6m", NULL, 0, 1600000, },
293792 + { HI3531DV200_FIXED_400K, "400k", NULL, 0, 400000, },
293793 + { HI3531DV200_FIXED_100K, "100k", NULL, 0, 100000, },
293800 +static u32 fmc_mux_table[] = {0, 1, 3, 4, 5, 6, 7};
293805 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
293810 +static u32 sysapb_mux_table[] = {0, 1};
293815 +static u32 sysaxi_mux_table[] = {0, 1};
293818 +static u32 uart_mux_table[] = {0, 1, 2};
293823 +static u32 i2c_mux_table[] = {0, 1};
293829 + CLK_SET_RATE_PARENT, 0x3f40, 12, 3, 0, fmc_mux_table,
293834 + CLK_SET_RATE_PARENT, 0x34c0, 24, 3, 0, mmc_mux_table,
293839 + CLK_SET_RATE_PARENT, 0x2000, 8, 1, 0, sysapb_mux_table
293844 + CLK_SET_RATE_PARENT, 0x2000, 0, 1, 0, sysaxi_mux_table
293849 + CLK_SET_RATE_PARENT, 0x4180, 12, 2, 0, uart_mux_table
293854 + CLK_SET_RATE_PARENT, 0x4188, 12, 2, 0, uart_mux_table
293859 + CLK_SET_RATE_PARENT, 0x4190, 12, 2, 0, uart_mux_table
293864 + CLK_SET_RATE_PARENT, 0x4198, 12, 2, 0, uart_mux_table
293869 + CLK_SET_RATE_PARENT, 0x41a0, 12, 2, 0, uart_mux_table
293874 + CLK_SET_RATE_PARENT, 0x4280, 12, 1, 0, i2c_mux_table
293879 + CLK_SET_RATE_PARENT, 0x4288, 12, 1, 0, i2c_mux_table
293890 + CLK_SET_RATE_PARENT, 0x3f40, 4, 0,
293894 + CLK_SET_RATE_PARENT, 0x34c0, 0, 0,
293898 + CLK_SET_RATE_PARENT, 0x4180, 4, 0,
293902 + CLK_SET_RATE_PARENT, 0x4188, 4, 0,
293906 + CLK_SET_RATE_PARENT, 0x4190, 4, 0,
293910 + CLK_SET_RATE_PARENT, 0x4198, 4, 0,
293914 + CLK_SET_RATE_PARENT, 0x41A0, 4, 0,
293918 + CLK_SET_RATE_PARENT, 0x37c4, 4, 0,
293922 + CLK_SET_RATE_PARENT, 0x37c0, 4, 0,
293926 + CLK_SET_RATE_PARENT, 0x3804, 4, 0,
293930 + CLK_SET_RATE_PARENT, 0x3800, 4, 0,
293934 + CLK_SET_RATE_PARENT, 0x4280, 4, 0,
293938 + CLK_SET_RATE_PARENT, 0x4288, 4, 0,
293942 + CLK_SET_RATE_PARENT, 0x4480, 4, 0,
293946 + CLK_SET_RATE_PARENT, 0x2a80, 5, 0,
293950 + CLK_SET_RATE_PARENT, 0x2a80, 4, 0,
293956 + HI3531DV200_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
293957 + 0x4, 0, 12, 12, 6
293960 + HI3531DV200_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3,
293961 + 0x24, 0, 12, 12, 6
293971 + *frac_val = 0;
293988 + postdiv1_val = postdiv2_val = 0;
294011 + return 0;
294038 + rate = 0;
294064 + for (i = 0; i < nums; i++) {
294077 + init.num_parents = (clks[i].parent_name ? 1 : 0);
294219 + return 0;
294228 + return 0;
294259 @@ -0,0 +1,570 @@
294328 + { HI3535AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
294329 + { HI3535AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
294330 + { HI3535AV100_FIXED_842M, "842m", NULL, 0, 842000000, },
294331 + { HI3535AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
294332 + { HI3535AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
294333 + { HI3535AV100_FIXED_710M, "710m", NULL, 0, 710000000, },
294334 + { HI3535AV100_FIXED_680M, "680m", NULL, 0, 680000000, },
294335 + { HI3535AV100_FIXED_667M, "667m", NULL, 0, 667000000, },
294336 + { HI3535AV100_FIXED_631M, "631m", NULL, 0, 631000000, },
294337 + { HI3535AV100_FIXED_600M, "600m", NULL, 0, 600000000, },
294338 + { HI3535AV100_FIXED_568M, "568m", NULL, 0, 568000000, },
294339 + { HI3535AV100_FIXED_500M, "500m", NULL, 0, 500000000, },
294340 + { HI3535AV100_FIXED_475M, "475m", NULL, 0, 475000000, },
294341 + { HI3535AV100_FIXED_428M, "428m", NULL, 0, 428000000, },
294342 + { HI3535AV100_FIXED_400M, "400m", NULL, 0, 400000000, },
294343 + { HI3535AV100_FIXED_396M, "396m", NULL, 0, 396000000, },
294344 + { HI3535AV100_FIXED_300M, "300m", NULL, 0, 300000000, },
294345 + { HI3535AV100_FIXED_297M, "297m", NULL, 0, 297000000, },
294346 + { HI3535AV100_FIXED_257M, "257m", NULL, 0, 257000000, },
294347 + { HI3535AV100_FIXED_250M, "250m", NULL, 0, 250000000, },
294348 + { HI3535AV100_FIXED_200M, "200m", NULL, 0, 200000000, },
294349 + { HI3535AV100_FIXED_198M, "198m", NULL, 0, 198000000, },
294350 + { HI3535AV100_FIXED_196p5M, "196p5m", NULL, 0, 196500000, },
294351 + { HI3535AV100_FIXED_187p5M, "187p5m", NULL, 0, 187500000, },
294352 + { HI3535AV100_FIXED_175M, "175m", NULL, 0, 175000000, },
294353 + { HI3535AV100_FIXED_163M, "163m", NULL, 0, 163000000, },
294354 + { HI3535AV100_FIXED_150M, "150m", NULL, 0, 150000000, },
294355 + { HI3535AV100_FIXED_148p5M, "148p5m", NULL, 0, 148500000, },
294356 + { HI3535AV100_FIXED_125M, "125m", NULL, 0, 125000000, },
294357 + { HI3535AV100_FIXED_107M, "107m", NULL, 0, 107000000, },
294358 + { HI3535AV100_FIXED_100M, "100m", NULL, 0, 100000000, },
294359 + { HI3535AV100_FIXED_99M, "99m", NULL, 0, 99000000, },
294360 + { HI3535AV100_FIXED_75M, "75m", NULL, 0, 75000000, },
294361 + { HI3535AV100_FIXED_74p25M, "74p25m", NULL, 0, 74250000, },
294362 + { HI3535AV100_FIXED_72M, "72m", NULL, 0, 72000000, },
294363 + { HI3535AV100_FIXED_60M, "60m", NULL, 0, 60000000, },
294364 + { HI3535AV100_FIXED_54M, "54m", NULL, 0, 54000000, },
294365 + { HI3535AV100_FIXED_50M, "50m", NULL, 0, 50000000, },
294366 + { HI3535AV100_FIXED_49p5M, "49p5m", NULL, 0, 49500000, },
294367 + { HI3535AV100_FIXED_37p125M, "37p125m", NULL, 0, 37125000, },
294368 + { HI3535AV100_FIXED_36M, "36m", NULL, 0, 36000000, },
294369 + { HI3535AV100_FIXED_32p4M, "32p4m", NULL, 0, 32400000, },
294370 + { HI3535AV100_FIXED_27M, "27m", NULL, 0, 27000000, },
294371 + { HI3535AV100_FIXED_25M, "25m", NULL, 0, 25000000, },
294372 + { HI3535AV100_FIXED_24M, "24m", NULL, 0, 24000000, },
294373 + { HI3535AV100_FIXED_12M, "12m", NULL, 0, 12000000, },
294374 + { HI3535AV100_FIXED_3M, "3m", NULL, 0, 3000000, },
294375 + { HI3535AV100_FIXED_1p6M, "1p6m", NULL, 0, 1600000, },
294376 + { HI3535AV100_FIXED_400K, "400k", NULL, 0, 400000, },
294377 + { HI3535AV100_FIXED_100K, "100k", NULL, 0, 100000, },
294384 +static u32 fmc_mux_table[] = {0, 1, 3, 4, 5, 6, 7};
294389 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
294394 +static u32 sysapb_mux_table[] = {0, 1};
294399 +static u32 sysaxi_mux_table[] = {0, 1};
294402 +static u32 uart_mux_table[] = {0, 1, 2};
294407 +static u32 i2c_mux_table[] = {0, 1};
294413 + CLK_SET_RATE_PARENT, 0x3f40, 12, 3, 0, fmc_mux_table,
294418 + CLK_SET_RATE_PARENT, 0x34c0, 24, 3, 0, mmc_mux_table,
294423 + CLK_SET_RATE_PARENT, 0x2000, 8, 1, 0, sysapb_mux_table
294428 + CLK_SET_RATE_PARENT, 0x2000, 0, 1, 0, sysaxi_mux_table
294433 + CLK_SET_RATE_PARENT, 0x4180, 12, 2, 0, uart_mux_table
294437 + CLK_SET_RATE_PARENT, 0x4188, 12, 2, 0, uart_mux_table
294441 + CLK_SET_RATE_PARENT, 0x4190, 12, 2, 0, uart_mux_table
294445 + CLK_SET_RATE_PARENT, 0x4198, 12, 2, 0, uart_mux_table
294449 + CLK_SET_RATE_PARENT, 0x41a0, 12, 2, 0, uart_mux_table
294453 + CLK_SET_RATE_PARENT, 0x4280, 12, 1, 0, i2c_mux_table
294457 + CLK_SET_RATE_PARENT, 0x4288, 12, 1, 0, i2c_mux_table
294468 + CLK_SET_RATE_PARENT, 0x3f40, 4, 0,
294472 + CLK_SET_RATE_PARENT, 0x34c0, 0, 0,
294476 + CLK_SET_RATE_PARENT, 0x4180, 4, 0,
294480 + CLK_SET_RATE_PARENT, 0x4188, 4, 0,
294484 + CLK_SET_RATE_PARENT, 0x4190, 4, 0,
294488 + CLK_SET_RATE_PARENT, 0x4198, 4, 0,
294492 + CLK_SET_RATE_PARENT, 0x41A0, 4, 0,
294496 + CLK_SET_RATE_PARENT, 0x37c4, 4, 0,
294500 + CLK_SET_RATE_PARENT, 0x37c0, 4, 0,
294504 + CLK_SET_RATE_PARENT, 0x3804, 4, 0,
294508 + CLK_SET_RATE_PARENT, 0x3800, 4, 0,
294512 + CLK_SET_RATE_PARENT, 0x4280, 4, 0,
294516 + CLK_SET_RATE_PARENT, 0x4288, 4, 0,
294520 + CLK_SET_RATE_PARENT, 0x4480, 4, 0,
294524 + CLK_SET_RATE_PARENT, 0x2a80, 5, 0,
294528 + CLK_SET_RATE_PARENT, 0x2a80, 4, 0,
294534 + HI3535AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
294535 + 0x4, 0, 12, 12, 6
294538 + HI3535AV100_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3,
294539 + 0x24, 0, 12, 12, 6
294549 + *frac_val = 0;
294566 + postdiv1_val = postdiv2_val = 0;
294589 + return 0;
294616 + rate = 0;
294642 + for (i = 0; i < nums; i++) {
294655 + init.num_parents = (clks[i].parent_name ? 1 : 0);
294794 + return 0;
294803 + return 0;
294835 @@ -0,0 +1,270 @@
294867 + { HI3536DV100_FIXED_3M, "3m", NULL, 0, 3000000, },
294868 + { HI3536DV100_FIXED_6M, "6m", NULL, 0, 6000000, },
294869 + { HI3536DV100_FIXED_12M, "12m", NULL, 0, 12000000, },
294870 + { HI3536DV100_FIXED_24M, "24m", NULL, 0, 24000000, },
294871 + { HI3536DV100_FIXED_50M, "50m", NULL, 0, 50000000, },
294872 + { HI3536DV100_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
294873 + { HI3536DV100_FIXED_100M, "100m", NULL, 0, 100000000, },
294874 + { HI3536DV100_FIXED_125M, "125m", NULL, 0, 125000000, },
294875 + { HI3536DV100_FIXED_150M, "150m", NULL, 0, 150000000, },
294876 + { HI3536DV100_FIXED_200M, "200m", NULL, 0, 200000000, },
294877 + { HI3536DV100_FIXED_250M, "250m", NULL, 0, 250000000, },
294878 + { HI3536DV100_FIXED_300M, "300m", NULL, 0, 300000000, },
294879 + { HI3536DV100_FIXED_324M, "324m", NULL, 0, 324000000, },
294880 + { HI3536DV100_FIXED_342M, "342m", NULL, 0, 342000000, },
294881 + { HI3536DV100_FIXED_342M, "375m", NULL, 0, 375000000, },
294882 + { HI3536DV100_FIXED_400M, "400m", NULL, 0, 400000000, },
294883 + { HI3536DV100_FIXED_448M, "448m", NULL, 0, 448000000, },
294884 + { HI3536DV100_FIXED_500M, "500m", NULL, 0, 500000000, },
294885 + { HI3536DV100_FIXED_540M, "540m", NULL, 0, 540000000, },
294886 + { HI3536DV100_FIXED_600M, "600m", NULL, 0, 600000000, },
294887 + { HI3536DV100_FIXED_750M, "750m", NULL, 0, 750000000, },
294888 + { HI3536DV100_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
294898 +static u32 sysaxi_mux_table[] __initdata = {0, 1, 2, 3};
294899 +static u32 sysapb_mux_table[] __initdata = {0, 1};
294900 +static u32 uart_mux_table[] __initdata = {0, 1, 2};
294901 +static u32 fmc_mux_table[] __initdata = {0, 1, 2};
294907 + CLK_SET_RATE_PARENT, 0x50, 2, 2, 0, sysaxi_mux_table,
294912 + CLK_SET_RATE_PARENT, 0x50, 0, 1, 0, sysapb_mux_table,
294916 + CLK_SET_RATE_PARENT, 0xc0, 2, 2, 0, fmc_mux_table,
294921 + CLK_SET_RATE_PARENT, 0xcc, 18, 2, 0, uart_mux_table,
294937 + CLK_SET_RATE_PARENT, 0xc0, 1, 0,
294942 + CLK_SET_RATE_PARENT, 0xcc, 15, 0,
294946 + CLK_SET_RATE_PARENT, 0xcc, 16, 0,
294950 + CLK_SET_RATE_PARENT, 0xcc, 17, 0,
294955 + CLK_SET_RATE_PARENT, 0xc4, 1, 0,
294959 + CLK_SET_RATE_PARENT, 0xc4, 10, 0,
294963 + CLK_SET_RATE_PARENT, 0xc8, 5, 0,
294970 + unsigned int count = 0;
295031 +static u32 timer_mux_table[] __initdata = {0, 1};
295037 + 0x0, 16, 1, 0, timer_mux_table,
295043 + 0x0, 18, 1, 0, timer_mux_table,
295049 + 0x0, 20, 1, 0, timer_mux_table,
295055 + 0x0, 22, 1, 0, timer_mux_table,
295061 + 0x0, 25, 1, 0, timer_mux_table,
295067 + 0x0, 27, 1, 0, timer_mux_table,
295073 + 0x0, 29, 1, 0, timer_mux_table,
295079 + 0x0, 31, 1, 0, timer_mux_table,
295111 @@ -0,0 +1,566 @@
295176 + HI3556AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
295177 + 0x4, 0, 12, 12, 6
295185 + { HI3556AV100_FIXED_2376M, "2376m", NULL, 0, 2376000000UL, },
295186 + { HI3556AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
295187 + { HI3556AV100_FIXED_594M, "594m", NULL, 0, 594000000, },
295188 + { HI3556AV100_FIXED_297M, "297m", NULL, 0, 297000000, },
295189 + { HI3556AV100_FIXED_148P5M, "148p5m", NULL, 0, 148500000, },
295190 + { HI3556AV100_FIXED_74P25M, "74p25m", NULL, 0, 74250000, },
295191 + { HI3556AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
295192 + { HI3556AV100_FIXED_475M, "475m", NULL, 0, 475000000, },
295193 + { HI3556AV100_FIXED_340M, "340m", NULL, 0, 340000000, },
295194 + { HI3556AV100_FIXED_72M, "72m", NULL, 0, 72000000, },
295195 + { HI3556AV100_FIXED_400M, "400m", NULL, 0, 400000000, },
295196 + { HI3556AV100_FIXED_200M, "200m", NULL, 0, 200000000, },
295197 + { HI3556AV100_FIXED_54M, "54m", NULL, 0, 54000000, },
295198 + { HI3556AV100_FIXED_27M, "27m", NULL, 0, 1188000000, },
295199 + { HI3556AV100_FIXED_37P125M, "37p125m", NULL, 0, 37125000, },
295200 + { HI3556AV100_FIXED_3000M, "3000m", NULL, 0, 3000000000UL, },
295201 + { HI3556AV100_FIXED_1500M, "1500m", NULL, 0, 1500000000, },
295202 + { HI3556AV100_FIXED_500M, "500m", NULL, 0, 500000000, },
295203 + { HI3556AV100_FIXED_250M, "250m", NULL, 0, 250000000, },
295204 + { HI3556AV100_FIXED_125M, "125m", NULL, 0, 125000000, },
295205 + { HI3556AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
295206 + { HI3556AV100_FIXED_600M, "600m", NULL, 0, 600000000, },
295207 + { HI3556AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
295208 + { HI3556AV100_FIXED_150M, "150m", NULL, 0, 150000000, },
295209 + { HI3556AV100_FIXED_75M, "75m", NULL, 0, 75000000, },
295210 + { HI3556AV100_FIXED_300M, "300m", NULL, 0, 300000000, },
295211 + { HI3556AV100_FIXED_60M, "60m", NULL, 0, 60000000, },
295212 + { HI3556AV100_FIXED_214M, "214m", NULL, 0, 214000000, },
295213 + { HI3556AV100_FIXED_107M, "107m", NULL, 0, 107000000, },
295214 + { HI3556AV100_FIXED_100M, "100m", NULL, 0, 100000000, },
295215 + { HI3556AV100_FIXED_50M, "50m", NULL, 0, 50000000, },
295216 + { HI3556AV100_FIXED_25M, "25m", NULL, 0, 25000000, },
295217 + { HI3556AV100_FIXED_24M, "24m", NULL, 0, 24000000, },
295218 + { HI3556AV100_FIXED_3M, "3m", NULL, 0, 3000000, },
295219 + { HI3556AV100_FIXED_100K, "100k", NULL, 0, 100000, },
295220 + { HI3556AV100_FIXED_400K, "400k", NULL, 0, 400000, },
295221 + { HI3556AV100_FIXED_49P5M, "49p5m", NULL, 0, 49500000, },
295222 + { HI3556AV100_FIXED_99M, "99m", NULL, 0, 99000000, },
295223 + { HI3556AV100_FIXED_187P5M, "187p5m", NULL, 0, 187500000, },
295224 + { HI3556AV100_FIXED_198M, "198m", NULL, 0, 198000000, },
295231 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
295236 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
295241 +static u32 sysapb_mux_table[] = {0, 1};
295246 +static u32 sysbus_mux_table[] = {0, 1};
295249 +static u32 uart_mux_table[] = {0, 1, 2};
295254 +static u32 a53_1_clksel_mux_table[] = {0, 1, 2, 3};
295259 + CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
295264 + CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
295269 + CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
295274 + CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
295279 + CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
295284 + CLK_SET_RATE_PARENT, 0xe8, 0, 1, 1, sysbus_mux_table
295289 + CLK_SET_RATE_PARENT, 0x1a4, 0, 2, 1, uart_mux_table
295294 + CLK_SET_RATE_PARENT, 0x1a4, 2, 2, 1, uart_mux_table
295299 + CLK_SET_RATE_PARENT, 0x1a4, 4, 2, 1, uart_mux_table
295304 + CLK_SET_RATE_PARENT, 0x1a4, 6, 2, 1, uart_mux_table
295309 + CLK_SET_RATE_PARENT, 0x1a4, 8, 2, 1, uart_mux_table
295314 + CLK_SET_RATE_PARENT, 0x1a4, 10, 2, 1, uart_mux_table
295319 + CLK_SET_RATE_PARENT, 0x1a4, 12, 2, 1, uart_mux_table
295324 + CLK_SET_RATE_PARENT, 0x1a4, 14, 2, 1, uart_mux_table
295329 + CLK_SET_RATE_PARENT, 0x1a4, 28, 2, 1, uart_mux_table
295334 + CLK_SET_RATE_PARENT, 0xe4, 10, 2, 3, a53_1_clksel_mux_table
295348 + CLK_SET_RATE_PARENT, 0x170, 1, 0,
295353 + CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
295357 + CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
295361 + CLK_SET_RATE_PARENT, 0x214, 28, 0,
295366 + CLK_SET_RATE_PARENT, 0x198, 16, 0,
295370 + CLK_SET_RATE_PARENT, 0x198, 17, 0,
295374 + CLK_SET_RATE_PARENT, 0x198, 18, 0,
295378 + CLK_SET_RATE_PARENT, 0x198, 19, 0,
295382 + CLK_SET_RATE_PARENT, 0x198, 20, 0,
295386 + CLK_SET_RATE_PARENT, 0x198, 21, 0,
295390 + CLK_SET_RATE_PARENT, 0x198, 22, 0,
295394 + CLK_SET_RATE_PARENT, 0x198, 23, 0,
295398 + CLK_SET_RATE_PARENT, 0x198, 29, 0,
295403 + CLK_SET_RATE_PARENT, 0x0174, 1, 0,
295407 + CLK_SET_RATE_PARENT, 0x0174, 5, 0,
295412 + CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
295416 + CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
295420 + CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
295424 + CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
295428 + CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
295432 + CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
295436 + CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
295440 + CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
295444 + CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
295448 + CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
295453 + CLK_SET_RATE_PARENT, 0x0198, 24, 0,
295457 + CLK_SET_RATE_PARENT, 0x0198, 25, 0,
295461 + CLK_SET_RATE_PARENT, 0x0198, 26, 0,
295465 + CLK_SET_RATE_PARENT, 0x0198, 27, 0,
295469 + CLK_SET_RATE_PARENT, 0x0198, 28, 0,
295474 + CLK_SET_RATE_PARENT, 0x14c, 5, 0,
295479 + CLK_SET_RATE_PARENT, 0x16c, 5, 0,
295483 + CLK_SET_RATE_PARENT, 0x16c, 6, 0,
295487 + CLK_SET_RATE_PARENT, 0x16c, 8, 0,
295491 + CLK_SET_RATE_PARENT, 0x16c, 9, 0,
295503 + *frac_val = 0;
295524 + postdiv1_val = postdiv2_val = 0;
295547 + return 0;
295575 + rate = 0;
295578 + return 0;
295609 + for (i = 0; i < nums; i++) {
295622 + init.num_parents = (clks[i].parent_name ? 1 : 0);
295683 @@ -0,0 +1,274 @@
295712 + { HI3556V200_FIXED_3M, "3m", NULL, 0, 3000000, },
295713 + { HI3556V200_FIXED_6M, "6m", NULL, 0, 6000000, },
295714 + { HI3556V200_FIXED_12M, "12m", NULL, 0, 12000000, },
295715 + { HI3556V200_FIXED_24M, "24m", NULL, 0, 24000000, },
295716 + { HI3556V200_FIXED_25M, "25m", NULL, 0, 25000000, },
295717 + { HI3556V200_FIXED_50M, "50m", NULL, 0, 50000000, },
295718 + { HI3556V200_FIXED_54M, "54m", NULL, 0, 54000000, },
295719 + { HI3556V200_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
295720 + { HI3556V200_FIXED_100M, "100m", NULL, 0, 100000000, },
295721 + { HI3556V200_FIXED_125M, "125m", NULL, 0, 125000000, },
295722 + { HI3556V200_FIXED_150M, "150m", NULL, 0, 150000000, },
295723 + { HI3556V200_FIXED_163M, "163m", NULL, 0, 163000000, },
295724 + { HI3556V200_FIXED_200M, "200m", NULL, 0, 200000000, },
295725 + { HI3556V200_FIXED_250M, "250m", NULL, 0, 250000000, },
295726 + { HI3556V200_FIXED_257M, "257m", NULL, 0, 257000000, },
295727 + { HI3556V200_FIXED_300M, "300m", NULL, 0, 300000000, },
295728 + { HI3556V200_FIXED_324M, "324m", NULL, 0, 324000000, },
295729 + { HI3556V200_FIXED_342M, "342m", NULL, 0, 342000000, },
295730 + { HI3556V200_FIXED_342M, "375m", NULL, 0, 375000000, },
295731 + { HI3556V200_FIXED_396M, "396m", NULL, 0, 396000000, },
295732 + { HI3556V200_FIXED_400M, "400m", NULL, 0, 400000000, },
295733 + { HI3556V200_FIXED_448M, "448m", NULL, 0, 448000000, },
295734 + { HI3556V200_FIXED_500M, "500m", NULL, 0, 500000000, },
295735 + { HI3556V200_FIXED_540M, "540m", NULL, 0, 540000000, },
295736 + { HI3556V200_FIXED_600M, "600m", NULL, 0, 600000000, },
295737 + { HI3556V200_FIXED_750M, "750m", NULL, 0, 750000000, },
295738 + { HI3556V200_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
295739 + { HI3556V200_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
295752 +static u32 sysaxi_mux_table[] = {0, 1, 2};
295753 +static u32 sysapb_mux_table[] = {0, 1};
295754 +static u32 uart_mux_table[] = {0, 1};
295755 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
295757 +static u32 eth_mux_table[] = {0, 1};
295759 +static u32 mmc_mux_table[] = {0, 1, 2, 3};
295765 + CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table,
295770 + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
295774 + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
295778 + CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table,
295782 + CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table,
295786 + CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table,
295791 + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
295797 + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
295803 + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
295808 + CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table,
295813 + CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table,
295819 + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
295835 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
295839 + CLK_SET_RATE_PARENT, 0x148, 1, 0,
295843 + CLK_SET_RATE_PARENT, 0x160, 1, 0,
295847 + CLK_SET_RATE_PARENT, 0x154, 1, 0,
295851 + CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
295855 + CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
295859 + CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
295863 + CLK_SET_RATE_PARENT, 0x1b8, 3, 0,
295867 + CLK_SET_RATE_PARENT, 0x1b8, 4, 0,
295871 + CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
295875 + CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
295879 + CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
295883 + CLK_SET_RATE_PARENT, 0x1b8, 14, 0,
295887 + CLK_SET_RATE_PARENT, 0x1b8, 15, 0,
295891 + CLK_SET_RATE_PARENT, 0x1b8, 16, 0,
295895 + CLK_SET_RATE_PARENT, 0x1b8, 17, 0,
295899 + CLK_SET_RATE_PARENT, 0x1b8, 18, 0,
295903 + CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
295907 + CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
295911 + CLK_SET_RATE_PARENT, 0x1bc, 14, 0,
295916 + CLK_SET_RATE_PARENT, 0x16c, 1, 0,
295921 + CLK_SET_RATE_PARENT, 0x194, 1, 0,
295925 + CLK_SET_RATE_PARENT, 0x194, 2, 0,
295930 + CLK_SET_RATE_PARENT, 0x1bc, 7, 0,
295963 @@ -0,0 +1,882 @@
296032 + { HI3559AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
296033 + { HI3559AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
296034 + { HI3559AV100_FIXED_842M, "842m", NULL, 0, 842000000, },
296035 + { HI3559AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
296036 + { HI3559AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
296037 + { HI3559AV100_FIXED_710M, "710m", NULL, 0, 710000000, },
296038 + { HI3559AV100_FIXED_680M, "680m", NULL, 0, 680000000, },
296039 + { HI3559AV100_FIXED_667M, "667m", NULL, 0, 667000000, },
296040 + { HI3559AV100_FIXED_631M, "631m", NULL, 0, 631000000, },
296041 + { HI3559AV100_FIXED_600M, "600m", NULL, 0, 600000000, },
296042 + { HI3559AV100_FIXED_568M, "568m", NULL, 0, 568000000, },
296043 + { HI3559AV100_FIXED_500M, "500m", NULL, 0, 500000000, },
296044 + { HI3559AV100_FIXED_475M, "475m", NULL, 0, 475000000, },
296045 + { HI3559AV100_FIXED_428M, "428m", NULL, 0, 428000000, },
296046 + { HI3559AV100_FIXED_400M, "400m", NULL, 0, 400000000, },
296047 + { HI3559AV100_FIXED_396M, "396m", NULL, 0, 396000000, },
296048 + { HI3559AV100_FIXED_300M, "300m", NULL, 0, 300000000, },
296049 + { HI3559AV100_FIXED_250M, "250m", NULL, 0, 250000000, },
296050 + { HI3559AV100_FIXED_200M, "200m", NULL, 0, 200000000, },
296051 + { HI3559AV100_FIXED_198M, "198m", NULL, 0, 198000000, },
296052 + { HI3559AV100_FIXED_187p5M, "187p5m", NULL, 0, 187500000, },
296053 + { HI3559AV100_FIXED_150M, "150m", NULL, 0, 150000000, },
296054 + { HI3559AV100_FIXED_148p5M, "148p5m", NULL, 0, 1485000000, },
296055 + { HI3559AV100_FIXED_125M, "125m", NULL, 0, 125000000, },
296056 + { HI3559AV100_FIXED_107M, "107m", NULL, 0, 107000000, },
296057 + { HI3559AV100_FIXED_100M, "100m", NULL, 0, 100000000, },
296058 + { HI3559AV100_FIXED_99M, "99m", NULL, 0, 99000000, },
296059 + { HI3559AV100_FIXED_75M, "75m", NULL, 0, 75000000, },
296060 + { HI3559AV100_FIXED_74p25M, "74p25m", NULL, 0, 74250000, },
296061 + { HI3559AV100_FIXED_72M, "72m", NULL, 0, 72000000, },
296062 + { HI3559AV100_FIXED_60M, "60m", NULL, 0, 60000000, },
296063 + { HI3559AV100_FIXED_54M, "54m", NULL, 0, 54000000, },
296064 + { HI3559AV100_FIXED_50M, "50m", NULL, 0, 50000000, },
296065 + { HI3559AV100_FIXED_49p5M, "49p5m", NULL, 0, 49500000, },
296066 + { HI3559AV100_FIXED_37p125M, "37p125m", NULL, 0, 37125000, },
296067 + { HI3559AV100_FIXED_36M, "36m", NULL, 0, 36000000, },
296068 + { HI3559AV100_FIXED_32p4M, "32p4m", NULL, 0, 32400000, },
296069 + { HI3559AV100_FIXED_27M, "27m", NULL, 0, 27000000, },
296070 + { HI3559AV100_FIXED_25M, "25m", NULL, 0, 25000000, },
296071 + { HI3559AV100_FIXED_24M, "24m", NULL, 0, 24000000, },
296072 + { HI3559AV100_FIXED_12M, "12m", NULL, 0, 12000000, },
296073 + { HI3559AV100_FIXED_3M, "3m", NULL, 0, 3000000, },
296074 + { HI3559AV100_FIXED_1p6M, "1p6m", NULL, 0, 1600000, },
296075 + { HI3559AV100_FIXED_400K, "400k", NULL, 0, 400000, },
296076 + { HI3559AV100_FIXED_100K, "100k", NULL, 0, 100000, },
296083 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
296088 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
296093 +static u32 sysapb_mux_table[] = {0, 1};
296098 +static u32 sysbus_mux_table[] = {0, 1};
296101 +static u32 uart_mux_table[] = {0, 1, 2};
296106 +static u32 a73_clksel_mux_table[] = {0, 1, 2};
296111 + CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
296116 + CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
296121 + CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
296126 + CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
296131 + CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table,
296136 + CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
296141 + CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table
296146 + CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table
296151 + CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table
296162 + CLK_SET_RATE_PARENT, 0x170, 1, 0,
296166 + CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
296170 + CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
296174 + CLK_SET_RATE_PARENT, 0x214, 28, 0,
296178 + CLK_SET_RATE_PARENT, 0x23c, 28, 0,
296182 + CLK_SET_RATE_PARENT, 0x198, 23, 0,
296186 + CLK_SET_RATE_PARENT, 0x198, 24, 0,
296190 + CLK_SET_RATE_PARENT, 0x198, 25, 0,
296194 + CLK_SET_RATE_PARENT, 0x198, 26, 0,
296198 + CLK_SET_RATE_PARENT, 0x198, 27, 0,
296202 + CLK_SET_RATE_PARENT, 0x0174, 1, 0,
296206 + CLK_SET_RATE_PARENT, 0x0174, 5, 0,
296210 + CLK_SET_RATE_PARENT, 0x0174, 3, 0,
296214 + CLK_SET_RATE_PARENT, 0x0174, 7, 0,
296218 + CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
296222 + CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
296226 + CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
296230 + CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
296234 + CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
296238 + CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
296242 + CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
296246 + CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
296250 + CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
296254 + CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
296258 + CLK_SET_RATE_PARENT, 0x01a0, 26, 0,
296262 + CLK_SET_RATE_PARENT, 0x01a0, 27, 0,
296266 + CLK_SET_RATE_PARENT, 0x0198, 16, 0,
296270 + CLK_SET_RATE_PARENT, 0x0198, 17, 0,
296274 + CLK_SET_RATE_PARENT, 0x0198, 18, 0,
296278 + CLK_SET_RATE_PARENT, 0x0198, 19, 0,
296282 + CLK_SET_RATE_PARENT, 0x0198, 20, 0,
296286 + CLK_SET_RATE_PARENT, 0x0198, 21, 0,
296290 + CLK_SET_RATE_PARENT, 0x0198, 22, 0,
296294 + CLK_SET_RATE_PARENT, 0x16c, 6, 0,
296298 + CLK_SET_RATE_PARENT, 0x16c, 5, 0,
296302 + CLK_SET_RATE_PARENT, 0x16c, 9, 0,
296306 + CLK_SET_RATE_PARENT, 0x16c, 8, 0,
296310 + CLK_SET_RATE_PARENT, 0x14c, 5, 0,
296316 + HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
296317 + 0x4, 0, 12, 12, 6
296320 + HI3559AV100_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3,
296321 + 0x24, 0, 12, 12, 6
296337 + *frac_val = 0;
296355 + postdiv1_val = postdiv2_val = 0;
296378 + return 0;
296416 + rate = 0;
296422 + return 0;
296450 + for (i = 0; i < nums; i++) {
296463 + init.num_parents = (clks[i].parent_name ? 1 : 0);
296572 + { HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, },
296573 + { HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, },
296574 + { HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, },
296575 + { HI3559AV100_SHUB_SOURCE_PLL, "clk_source_PLL", NULL, 0, 192000000UL, },
296576 + { HI3559AV100_SHUB_I2C0_CLK, "clk_shub_i2c0", NULL, 0, 48000000UL, },
296577 + { HI3559AV100_SHUB_I2C1_CLK, "clk_shub_i2c1", NULL, 0, 48000000UL, },
296578 + { HI3559AV100_SHUB_I2C2_CLK, "clk_shub_i2c2", NULL, 0, 48000000UL, },
296579 + { HI3559AV100_SHUB_I2C3_CLK, "clk_shub_i2c3", NULL, 0, 48000000UL, },
296580 + { HI3559AV100_SHUB_I2C4_CLK, "clk_shub_i2c4", NULL, 0, 48000000UL, },
296581 + { HI3559AV100_SHUB_I2C5_CLK, "clk_shub_i2c5", NULL, 0, 48000000UL, },
296582 + { HI3559AV100_SHUB_I2C6_CLK, "clk_shub_i2c6", NULL, 0, 48000000UL, },
296583 + { HI3559AV100_SHUB_I2C7_CLK, "clk_shub_i2c7", NULL, 0, 48000000UL, },
296584 + { HI3559AV100_SHUB_UART_CLK_32K, "clk_uart_32K", NULL, 0, 32000UL, },
296588 +static u32 shub_source_clk_mux_table[] = {0, 1, 2, 3};
296593 +static u32 shub_uart_source_clk_mux_table[] = {0, 1, 2, 3};
296601 + 0, 0x0, 0, 2, 0, shub_source_clk_mux_table,
296606 + 0, 0x1c, 28, 2, 0, shub_uart_source_clk_mux_table,
296612 +struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}};
296613 +struct clk_div_table shub_spi4_clk_table[] = {{0, 8}, {1, 4}, {2, 2}, {3, 1}};
296617 + { HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2, CLK_DIVIDER_ALLOW_Z…
296618 + { HI3559AV100_SHUB_UART_DIV_CLK, "clk_uart_div_clk", "shub_clk", 0, 0x1c, 28, 2, CLK_DIVIDER_ALLO…
296626 + 0, 0x20, 1, 0,
296630 + 0, 0x20, 5, 0,
296634 + 0, 0x20, 9, 0,
296639 + 0, 0x1c, 1, 0,
296643 + 0, 0x1c, 5, 0,
296647 + 0, 0x1c, 9, 0,
296651 + 0, 0x1c, 13, 0,
296655 + 0, 0x1c, 17, 0,
296659 + 0, 0x1c, 21, 0,
296663 + 0, 0x1c, 25, 0,
296668 + 0, 0x24, 4, 0,
296677 + crg_base = ioremap_nocache(0x18020000, 0x1000);
296680 + val = readl_relaxed(crg_base + 0x20);
296681 + val |= (0x2 << 24);
296682 + writel_relaxed(val, crg_base + 0x20);
296685 + val = readl_relaxed(crg_base + 0x1C);
296686 + val |= (0x1 << 28);
296687 + writel_relaxed(val, crg_base + 0x1C);
296692 + return 0;
296810 + return 0;
296819 + return 0;
296851 @@ -0,0 +1,271 @@
296880 + { HI3559V200_FIXED_3M, "3m", NULL, 0, 3000000, },
296881 + { HI3559V200_FIXED_6M, "6m", NULL, 0, 6000000, },
296882 + { HI3559V200_FIXED_12M, "12m", NULL, 0, 12000000, },
296883 + { HI3559V200_FIXED_24M, "24m", NULL, 0, 24000000, },
296884 + { HI3559V200_FIXED_25M, "25m", NULL, 0, 25000000, },
296885 + { HI3559V200_FIXED_50M, "50m", NULL, 0, 50000000, },
296886 + { HI3559V200_FIXED_54M, "54m", NULL, 0, 54000000, },
296887 + { HI3559V200_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
296888 + { HI3559V200_FIXED_100M, "100m", NULL, 0, 100000000, },
296889 + { HI3559V200_FIXED_125M, "125m", NULL, 0, 125000000, },
296890 + { HI3559V200_FIXED_150M, "150m", NULL, 0, 150000000, },
296891 + { HI3559V200_FIXED_163M, "163m", NULL, 0, 163000000, },
296892 + { HI3559V200_FIXED_200M, "200m", NULL, 0, 200000000, },
296893 + { HI3559V200_FIXED_250M, "250m", NULL, 0, 250000000, },
296894 + { HI3559V200_FIXED_257M, "257m", NULL, 0, 257000000, },
296895 + { HI3559V200_FIXED_300M, "300m", NULL, 0, 300000000, },
296896 + { HI3559V200_FIXED_324M, "324m", NULL, 0, 324000000, },
296897 + { HI3559V200_FIXED_342M, "342m", NULL, 0, 342000000, },
296898 + { HI3559V200_FIXED_342M, "375m", NULL, 0, 375000000, },
296899 + { HI3559V200_FIXED_396M, "396m", NULL, 0, 396000000, },
296900 + { HI3559V200_FIXED_400M, "400m", NULL, 0, 400000000, },
296901 + { HI3559V200_FIXED_448M, "448m", NULL, 0, 448000000, },
296902 + { HI3559V200_FIXED_500M, "500m", NULL, 0, 500000000, },
296903 + { HI3559V200_FIXED_540M, "540m", NULL, 0, 540000000, },
296904 + { HI3559V200_FIXED_600M, "600m", NULL, 0, 600000000, },
296905 + { HI3559V200_FIXED_750M, "750m", NULL, 0, 750000000, },
296906 + { HI3559V200_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
296907 + { HI3559V200_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
296921 +static u32 sysaxi_mux_table[] = {0, 1, 2};
296922 +static u32 sysapb_mux_table[] = {0, 1};
296923 +static u32 uart_mux_table[] = {0, 1};
296924 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
296926 +static u32 eth_mux_table[] = {0, 1};
296928 +static u32 mmc_mux_table[] = {0, 1, 2, 3};
296934 + CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table,
296939 + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
296943 + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
296947 + CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table,
296951 + CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table,
296955 + CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table,
296960 + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
296966 + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
296972 + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
296977 + CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table,
296982 + CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table,
296988 + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
297004 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
297008 + CLK_SET_RATE_PARENT, 0x148, 1, 0,
297012 + CLK_SET_RATE_PARENT, 0x160, 1, 0,
297016 + CLK_SET_RATE_PARENT, 0x154, 1, 0,
297020 + CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
297024 + CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
297028 + CLK_SET_RATE_PARENT, 0x1b8, 3, 0,
297032 + CLK_SET_RATE_PARENT, 0x1b8, 4, 0,
297036 + CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
297040 + CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
297044 + CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
297048 + CLK_SET_RATE_PARENT, 0x1b8, 14, 0,
297052 + CLK_SET_RATE_PARENT, 0x1b8, 15, 0,
297056 + CLK_SET_RATE_PARENT, 0x1b8, 16, 0,
297060 + CLK_SET_RATE_PARENT, 0x1b8, 17, 0,
297064 + CLK_SET_RATE_PARENT, 0x1b8, 18, 0,
297068 + CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
297072 + CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
297076 + CLK_SET_RATE_PARENT, 0x1bc, 14, 0,
297081 + CLK_SET_RATE_PARENT, 0x16c, 1, 0,
297086 + CLK_SET_RATE_PARENT, 0x194, 1, 0,
297090 + CLK_SET_RATE_PARENT, 0x194, 2, 0,
297095 + CLK_SET_RATE_PARENT, 0x1bc, 7, 0,
297182 + rstc->membase = of_iomap(np, 0);
297268 #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;})
297269 #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;})
297282 @@ -0,0 +1,356 @@
297318 +#define TIMER_LOAD 0x00 /* ACVR rw */
297319 +#define TIMER_VALUE 0x04 /* ACVR ro */
297320 +#define TIMER_CTRL 0x08 /* ACVR rw */
297321 +#define TIMER_CTRL_ONESHOT (1 << 0) /* CVR */
297323 +#define TIMER_CTRL_DIV1 (0 << 2) /* ACVR */
297330 +#define TIMER_INTCLR 0x0c /* ACVR wo */
297331 +#define TIMER_RIS 0x10 /* CVR ro */
297332 +#define TIMER_MIS 0x14 /* CVR ro */
297333 +#define TIMER_BGLOAD 0x18 /* CVR rw */
297335 +#define CPU_TASKS_FROZEN 0x0010
297365 + writel(0, base + TIMER_CTRL);
297366 + writel(0xffffffff, base + TIMER_LOAD);
297367 + writel(0xffffffff, base + TIMER_VALUE);
297410 + writel(0, hiclkevt->base + TIMER_CTRL);
297412 + return 0;
297432 + return 0;
297451 + return 0;
297471 + writel(0, hiclkevt->base + TIMER_CTRL);
297477 + clockevents_config_and_register(clkevt, hiclkevt->rate, 0xf,
297478 + 0x7fffffff);
297480 + return 0;
297568 + clk1 = of_clk_get(node, 0);
297598 + for (ix = 0; ix < nr_cpus; ix++) {
297603 + while (--ix >= 0)
297612 + base = of_iomap(node, 0);
297614 + pr_err("can't iomap timer %d\n", 0);
297626 + return 0;
297631 + for (ix = 0; ix < nr_irqs; ix++)
297691 @@ -0,0 +1,1443 @@
297826 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "lli num = 0%d\n", num);
297827 + for (i = 0; i < num; i++) {
297828 + printk("lli%d:lli_L: 0x%llx\n", i, plli[i].next_lli & 0xffffffff);
297829 + printk("lli%d:lli_H: 0x%llx\n", i, (plli[i].next_lli >> BITS_PER_HALF_WORD) & 0xffffffff);
297830 + printk("lli%d:count: 0x%x\n", i, plli[i].count);
297831 + printk("lli%d:src_addr_L: 0x%llx\n", i, plli[i].src_addr & 0xffffffff);
297832 + printk("lli%d:src_addr_H: 0x%llx\n", i, (plli[i].src_addr >> BITS_PER_HALF_WORD) & 0xffffffff);
297833 + printk("lli%d:dst_addr_L: 0x%llx\n", i, plli[i].dest_addr & 0xffffffff);
297834 + printk("lli%d:dst_addr_H: 0x%llx\n", i, (plli[i].dest_addr >> BITS_PER_HALF_WORD) & 0xffffffff);
297835 + printk("lli%d:CONFIG: 0x%x\n", i, plli[i].config);
297878 + unsigned int reg = 0;
297879 + unsigned int offset = 0;
297891 + request_num = dma_spec->args[0];
297900 + reg = 0xc0;
297903 + offset = hiedmac->misc_ctrl_base + (request_num & (~0x3));
297906 + reg &= ~(0x3f << ((request_num & 0x3) << 3));
297907 + reg |= signal << ((request_num & 0x3) << 3);
297912 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "offset = 0x%x, reg = 0x%x\n", offset, reg);
297940 + hiedmac->irq = platform_get_irq(platdev, 0);
297941 + if (unlikely(hiedmac->irq < 0))
297948 + res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
297957 + return 0;
297968 + hiedmac->misc_regmap = 0;
297997 + return 0;
298038 + phychan->id)) & 0xffffffff) << BITS_PER_HALF_WORD);
298041 + if (next_lli != 0) {
298046 + for (i = 0; i < index; i++)
298102 + for (i = 0; i < hiedmac->channels; i++) {
298128 + if (plli->next_lli != 0x0)
298129 + hiedmacv310_writel((plli->next_lli & 0xffffffff) | HIEDMAC_LLI_ENABLE,
298132 + hiedmacv310_writel((plli->next_lli & 0xffffffff),
298135 + hiedmacv310_writel(((plli->next_lli >> 32) & 0xffffffff),
298138 + hiedmacv310_writel(plli->src_addr & 0xffffffff,
298140 + hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff,
298142 + hiedmacv310_writel(plli->dest_addr & 0xffffffff,
298144 + hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff,
298161 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, " HIEDMAC_Cx_CONFIG = 0x%x\n", val);
298209 + return 0;
298223 + for (timeout = 2000; timeout > 0; timeout--) {
298224 + if (!((0x1 << phychan->id) & hiedmacv310_readl(hiedmac->base + HIEDMAC_CH_STAT)))
298229 + if (timeout == 0)
298242 + return 0;
298247 + return 0;
298269 + return 0;
298276 + return 0;
298289 + return 0;
298303 + return 0;
298319 + return ~0;
298335 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "addr_width = 0x%x\n", addr_width);
298337 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "width = 0x%x\n", width);
298340 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, "tsf_desc->ccfg = 0x%x\n", config);
298341 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "burst = 0x%x\n", burst);
298344 + if (signal >= 0) {
298358 + unsigned int burst = 0;
298359 + unsigned int addr_width = 0;
298360 + unsigned int maxburst = 0;
298380 + else if (maxburst == 0)
298387 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, "tsf_desc->ccfg = 0x%x\n", tsf_desc->ccfg);
298403 + memset(&plli[num], 0x0, sizeof(*plli));
298411 + if (num > 0) {
298416 + return 0;
298436 + if (len == 0) {
298437 + hiedmacv310_error("Transfer length is 0. \n");
298452 + return 0;
298460 + dma_addr_t src = 0;
298461 + dma_addr_t dst = 0;
298513 + size_t count_in_sg = 0;
298523 + return 0;
298540 + while (dsg->len != 0) {
298555 + return 0;
298563 + unsigned int lli_count = 0;
298579 + last_plli->next_lli = 0;
298582 + return 0;
298593 + dma_addr_t slave_addr = 0;
298636 + u32 config = 0;
298657 + /* max burst width is 16 ,but reg value set 0xf */
298688 + dma_addr_t slave_addr = 0;
298736 + val = 0x1 << phychan->id;
298788 + return 0;
298793 + channel_tc_status = (channel_tc_status >> chan_id) & 0x01;
298798 + channel_tc_status = (channel_tc_status >> chan_id) & 0x01;
298801 + channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
298804 + if ((channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) & (1 << chan_id)) {
298805 + hiedmacv310_error("Error in hiedmac %d!,ERR1 = 0x%x,ERR2 = 0x%x,ERR3 = 0x%x\n",
298806 + chan_id, channel_err_status[0],
298835 + u32 mask = 0;
298840 + hiedmacv310_error("channel_status = 0x%x\n", channel_status);
298844 + for (i = 0; i < hiedmac->channels; i++) {
298845 + temp = (channel_status >> i) & 0x1;
298874 + for (i = 0; i < channels; i++) {
298892 + return 0;
298949 + for (i = 0; i < hiedmac->channels; i++) {
298970 + return 0;
299038 + trasfer_size, EDMACV300_POOL_ALIGN, 0);
299074 + ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
299091 + return 0;
299104 + int err = 0;
299140 @@ -0,0 +1,153 @@
299167 +#define HIEDMACV310_TRACE_LEVEL 0
299178 +} while (0)
299188 +} while (0)
299194 +} while (0)
299207 +} while (0)
299210 +#define MAX_TRANSFER_BYTES 0xffff
299213 +#define HIEDMAC_INT_STAT 0x0
299214 +#define HIEDMAC_INT_TC1 0x4
299215 +#define HIEDMAC_INT_TC2 0x8
299216 +#define HIEDMAC_INT_ERR1 0xc
299217 +#define HIEDMAC_INT_ERR2 0x10
299218 +#define HIEDMAC_INT_ERR3 0x14
299220 +#define HIEDMAC_INT_TC1_MASK 0x18
299221 +#define HIEDMAC_INT_TC2_MASK 0x1c
299222 +#define HIEDMAC_INT_ERR1_MASK 0x20
299223 +#define HIEDMAC_INT_ERR2_MASK 0x24
299224 +#define HIEDMAC_INT_ERR3_MASK 0x28
299226 +#define HIEDMAC_INT_TC1_RAW 0x600
299227 +#define HIEDMAC_INT_TC2_RAW 0x608
299228 +#define HIEDMAC_INT_ERR1_RAW 0x610
299229 +#define HIEDMAC_INT_ERR2_RAW 0x618
299230 +#define HIEDMAC_INT_ERR3_RAW 0x620
299232 +#define hiedmac_cx_curr_cnt0(cn) (0x404 + (cn) * 0x20)
299233 +#define hiedmac_cx_curr_src_addr_l(cn) (0x408 + (cn) * 0x20)
299234 +#define hiedmac_cx_curr_src_addr_h(cn) (0x40c + (cn) * 0x20)
299235 +#define hiedmac_cx_curr_dest_addr_l(cn) (0x410 + (cn) * 0x20)
299236 +#define hiedmac_cx_curr_dest_addr_h(cn) (0x414 + (cn) * 0x20)
299238 +#define HIEDMAC_CH_PRI 0x688
299239 +#define HIEDMAC_CH_STAT 0x690
299240 +#define HIEDMAC_DMA_CTRL 0x698
299242 +#define hiedmac_cx_base(cn) (0x800 + (cn) * 0x40)
299243 +#define hiedmac_cx_lli_l(cn) (0x800 + (cn) * 0x40)
299244 +#define hiedmac_cx_lli_h(cn) (0x804 + (cn) * 0x40)
299245 +#define hiedmac_cx_cnt0(cn) (0x81c + (cn) * 0x40)
299246 +#define hiedmac_cx_src_addr_l(cn) (0x820 + (cn) * 0x40)
299247 +#define hiedmac_cx_src_addr_h(cn) (0x824 + (cn) * 0x40)
299248 +#define hiedmac_cx_dest_addr_l(cn) (0x828 + (cn) * 0x40)
299249 +#define hiedmac_cx_dest_addr_h(cn) (0x82c + (cn) * 0x40)
299250 +#define hiedmac_cx_config(cn) (0x830 + (cn) * 0x40)
299252 +#define HIEDMAC_ALL_CHAN_CLR 0xff
299253 +#define HIEDMAC_INT_ENABLE_ALL_CHAN 0xff
299261 +#define HIEDMAC_WIDTH_8BIT 0b0
299262 +#define HIEDMAC_WIDTH_16BIT 0b1
299263 +#define HIEDMAC_WIDTH_32BIT 0b10
299264 +#define HIEDMAC_WIDTH_64BIT 0b11
299276 +#define HIEDMAC_LLI_ALIGN 0x40
299277 +#define HIEDMAC_LLI_DISABLE 0x0
299278 +#define HIEDMAC_LLI_ENABLE 0x2
299280 +#define HIEDMAC_CXCONFIG_SIGNAL_SHIFT 0x4
299281 +#define HIEDMAC_CXCONFIG_MEM_TYPE 0x0
299282 +#define HIEDMAC_CXCONFIG_DEV_MEM_TYPE 0x1
299283 +#define HIEDMAC_CXCONFIG_TSF_TYPE_SHIFT 0x2
299284 +#define HIEDMAC_CXCONFIG_LLI_START 0x1
299286 +#define HIEDMAC_CXCONFIG_ITC_EN 0x1
299287 +#define HIEDMAC_CXCONFIG_ITC_EN_SHIFT 0x1
299289 +#define CCFG_EN 0x1
299323 return 0;
299373 + if (gpio_idx < 0)
299378 + if (pl061->gc.base < 0)
299400 + for (gpio_idx = 0; gpio_idx < pl061->gc.ngpio; gpio_idx++)
299432 @@ -0,0 +1,8 @@
299446 @@ -0,0 +1,27 @@
299479 @@ -0,0 +1,91 @@
299492 + OUTPUT_USER = 0, /* User timing */
299576 @@ -0,0 +1,775 @@
299609 + unsigned int status; /* 0: closed, 1: opened */
299620 + unsigned int status; /* 0: closed, 1: opened */
299674 + cap->layer_cap[DRM_HAL_GFX_G0].formats[0] = DRM_HAL_FMT_ARGB8888;
299677 + cap->layer_cap[DRM_HAL_GFX_G1].available = 0;
299679 + cap->layer_cap[DRM_HAL_GFX_G2].available = 0;
299686 + cap->layer_cap[DRM_HAL_GFX_G3].formats[0] = DRM_HAL_FMT_ARGB8888;
299695 + int matched = 0;
299714 + for (i = 0; i < DRM_HAL_GFX_MAX; i++) {
299715 + if (cap.layer_cap[i].available != 0 &&
299725 + return 0;
299731 + hi_vo_csc csc = {0};
299739 + if (ret != 0) {
299746 + if (ret != 0) {
299750 + return 0;
299755 + int ret = 0;
299758 + enum drm_connector_status mipi_status = 0;
299759 + enum drm_connector_status hdmi_status = 0;
299790 + return 0;
299794 + if (ret != 0) {
299799 + if (ret != 0) {
299804 + if (ret != 0) {
299809 + return 0;
299830 + if (hi_plane->status == 0) {
299831 + return 0;
299835 + if (ret != 0) {
299840 + if (ret != 0) {
299843 + hi_plane->status = 0;
299844 + return 0;
299894 + hi_plane->root_hi_crtc->status == 0) {
299899 + gem = drm_gem_fb_get_obj(fb, 0);
299907 + hal_rect.x = 0;
299908 + hal_rect.y = 0;
299912 + if (ret != 0) {
299919 + if (ret != 0) {
299924 + ret = gfx_dev->set_attr(hi_plane->id, DRM_HAL_GFX_ATTR_STRIDE, &fb->pitches[0]);
299925 + if (ret != 0) {
299931 + if (ret != 0) {
299937 + if (ret != 0) {
299952 + return 0;
299992 + case 0:
300001 + return 0;
300018 + return 0;
300024 + if (ret != 0) {
300030 + if (ret != 0) {
300038 + return 0;
300057 + if (hi_crtc->status == 0) {
300059 + return 0;
300063 + if (ret != 0) {
300068 + for (i = 0; i < HI_DRM_MAX_PRIMARY_NUM; i++) {
300079 + if (ret != 0) {
300082 + hi_crtc->status = 0;
300112 + if (ret != 0) {
300116 + return 0;
300124 + hi_vo_user_intfsync_info intf_sync_attr = {0};
300142 + ret = disp_dev->attach_user_intf_sync(hi_crtc->id, &intf_sync_attr, 0);
300143 + if (ret != 0) {
300147 + return 0;
300161 + if (ret != 0) {
300165 + return 0;
300179 + if (ret != 0) {
300183 + return 0;
300197 + if (ret != 0) {
300201 + return 0;
300208 + struct drm_hal_gfx_capability cap = {0};
300216 + if (cap.layer_cap[layer].available == 0) {
300220 + for (i = 0; i < HI_DRM_MAX_CRTC_NUM; i++) {
300234 + if (type == DRM_HAL_GFX_CB_INTR_100 && hi_crtc->adp_crtc_cb != NULL && hi_crtc->status != 0) {
300237 + return 0;
300255 + return 0;
300262 + if (ret != 0) {
300267 + return 0;
300283 + {DRM_HAL_TIMING_FMT_1080P_60, {148500, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0}},
300284 + {DRM_HAL_TIMING_FMT_1080P_50, {148500, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0}},
300285 + {DRM_HAL_TIMING_FMT_1080P_59_94, {148352, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0…
300286 + {DRM_HAL_TIMING_FMT_1080P_30, {74250, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0}},
300287 + {DRM_HAL_TIMING_FMT_1080P_25, {74250, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0}},
300288 + {DRM_HAL_TIMING_FMT_1080P_24, {74250, 1920, 2558, 2602, 2750, 0, 1080, 1084, 1089, 1125, 0}},
300289 + {DRM_HAL_TIMING_FMT_1080I_60, {74250, 1920, 2008, 2052, 2200, 0, 540, 542, 547, 562, 0}},
300290 + {DRM_HAL_TIMING_FMT_1080I_50, {74250, 1920, 2448, 2492, 2640, 0, 540, 542, 547, 562, 0}},
300291 + {DRM_HAL_TIMING_FMT_720P_60, {74250, 1280, 1390, 1430, 1650, 0, 720, 725, 730, 750, 0}},
300292 + {DRM_HAL_TIMING_FMT_720P_50, {74250, 1280, 1720, 1760, 1980, 0, 720, 725, 730, 750, 0}},
300293 + {DRM_HAL_TIMING_FMT_576P_50, {27000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0}},
300294 + {DRM_HAL_TIMING_FMT_480P_60, {27000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0}},
300295 + {DRM_HAL_TIMING_FMT_PAL, {13500, 720, 732, 795, 864, 0, 288, 290, 293, 312, 0}},
300296 + {DRM_HAL_TIMING_FMT_NTSC, {13500, 720, 739, 801, 858, 0, 240, 244, 247, 262, 0}},
300297 + {DRM_HAL_TIMING_FMT_VESA_800X600_60, {40000, 800, 840, 968, 1056, 0, 600, 601, 605, 628, 0}},
300298 + {DRM_HAL_TIMING_FMT_VESA_1024X768_60, {48400, 1024, 1048, 1184, 1344, 0, 768, 771, 777, 806, 0…
300299 + {DRM_HAL_TIMING_FMT_VESA_1280X800_60, {83500, 1280, 1352, 1480, 1680, 0, 800, 803, 809, 831, 0…
300300 …_HAL_TIMING_FMT_VESA_1280X1024_60, {108000, 1280, 1328, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0}},
300301 + {DRM_HAL_TIMING_FMT_VESA_1366X768_60, {85500, 1366, 1436, 1579, 1792, 0, 768, 771, 774, 798, 0…
300302 … {DRM_HAL_TIMING_FMT_VESA_1440X900_60, {106500, 1440, 1488, 1520, 1600, 0, 900, 903, 909, 926, 0}},
300303 …_HAL_TIMING_FMT_VESA_1600X1200_60, {162000, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0}},
300304 …_HAL_TIMING_FMT_VESA_1680X1050_60, {146250, 1680, 1784, 1960, 2240, 0, 1050, 1053, 1059, 1089, 0}},
300305 …_HAL_TIMING_FMT_VESA_1920X1200_60, {193250, 1920, 1968, 2000, 2080, 0, 1200, 1203, 1209, 1235, 0}},
300306 … {DRM_HAL_TIMING_FMT_2560X1440_60, {238750, 2560, 2608, 2640, 2720, 0, 1440, 1442, 1447, 1481, 0}},
300307 … {DRM_HAL_TIMING_FMT_2560X1600_60, {268500, 2560, 2608, 2640, 2720, 0, 1600, 1603, 1609, 1646, 0}},
300308 …{DRM_HAL_TIMING_FMT_3840X2160P_24, {297000, 3840, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0}},
300309 …{DRM_HAL_TIMING_FMT_3840X2160P_25, {297000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0}},
300310 …{DRM_HAL_TIMING_FMT_3840X2160P_30, {297000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0}},
300311 …{DRM_HAL_TIMING_FMT_3840X2160P_50, {594000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0}},
300312 …{DRM_HAL_TIMING_FMT_3840X2160P_60, {594000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0}},
300313 …{DRM_HAL_TIMING_FMT_4096X2160P_24, {297000, 4096, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0}},
300314 …{DRM_HAL_TIMING_FMT_4096X2160P_25, {297000, 4096, 5064, 5152, 5280, 0, 2160, 2168, 2178, 2250, 0}},
300315 …{DRM_HAL_TIMING_FMT_4096X2160P_30, {297000, 4096, 4184, 4272, 4400, 0, 2160, 2168, 2178, 2250, 0}},
300316 …{DRM_HAL_TIMING_FMT_4096X2160P_50, {594000, 4096, 5064, 5152, 5280, 0, 2160, 2168, 2178, 2250, 0}},
300317 …{DRM_HAL_TIMING_FMT_4096X2160P_60, {594000, 4096, 4184, 4272, 4400, 0, 2160, 2168, 2178, 2250, 0}},
300318 + {DRM_HAL_TIMING_FMT_USER, {155493, 480, 528, 560, 620, 0, 960, 963, 968, 974, 0}},
300325 + for (i = 0; i < sizeof(g_adp_crtc_timing_map) / sizeof(struct adp_crtc_timing_map); i++) {
300357 @@ -0,0 +1,69 @@
300432 @@ -0,0 +1,345 @@
300470 + unsigned int open; /* 0: close, 1: open */
300471 + unsigned int enable; /* 0: disable, 1: enable */
300510 + return 0;
300514 + if (ret != 0) {
300519 + return 0;
300531 + if (hdmitx->open == 0) {
300532 + return 0;
300536 + if (ret != 0) {
300540 + hdmitx->open = 0;
300541 + return 0;
300554 + return 0;
300558 + if (ret != 0) {
300563 + return 0;
300575 + if (hdmitx->enable == 0) {
300576 + return 0;
300580 + if (ret != 0) {
300584 + hdmitx->enable = 0;
300585 + return 0;
300600 + if (ret != 0) {
300605 + if (ret <= 0) {
300608 + return 0;
300623 + if (ret != 0) {
300628 + if (ret != 0) {
300655 + if (ret != 0) {
300660 + if (ret != 0) {
300663 + return 0;
300677 + if (ret != 0) {
300682 + if (ret != 0) {
300685 + return 0;
300692 + struct drm_hal_hdmitx_attr hdmi_attr = {0};
300703 + if (ret != 0) {
300708 + return 0;
300713 + if (ret != 0) {
300719 + if (ret != 0) {
300724 + if (ret != 0) {
300741 + if (ret != 0) {
300744 + return 0;
300756 + g_hi_hdmitx->hdmitx[0].drm_hdmi_id = drm_hdmi_id;
300757 + g_hi_hdmitx->hdmitx[0].hi_hdmi_id = DRM_HAL_HDMITX_0;
300758 + *conn = &g_hi_hdmitx->hdmitx[0].conn;
300759 + *encoder = &g_hi_hdmitx->hdmitx[0].encoder;
300760 + return 0;
300770 + return 0;
300783 @@ -0,0 +1,28 @@
300817 @@ -0,0 +1,300 @@
300859 + unsigned int enable; /* 0: disable, 1: enable */
300882 + .flags = 0, /* 0 alg data */
300902 + if (ret != 0) {
300935 + return 0;
300939 + if (ret != 0) {
300944 + if (ret != 0) {
300950 + if (ret != 0) {
300954 + return 0;
300967 + return 0;
300971 + if (ret != 0) {
300977 + return 0;
300990 + if (hi_mipitx->enable == 0) {
300991 + return 0;
300995 + if (ret != 0) {
301000 + hi_mipitx->enable = 0;
301001 + return 0;
301015 + return 0;
301030 + return 0;
301043 + return 0;
301045 + if (brightness < 0 || brightness >255) {
301046 + HI_DRM_INFO("brightness value out of range[0~255]!");
301047 + return 0;
301050 + if (ret != 0) {
301054 + return 0;
301061 + hi_mipitx->private.tv_brightness_property = drm_property_create_range(dev, 0, "brightness", 0,…
301067 + return 0;
301093 + return 0;
301105 + return 0;
301123 @@ -0,0 +1,32 @@
301161 @@ -0,0 +1,388 @@
301199 + if (ret != 0) {
301210 + if (ret != 0) {
301216 + return 0;
301236 + if (ret != 0) {
301258 + if (ret != 0) {
301264 + return 0;
301272 + if (ret != 0) {
301285 + if (ret != 0) {
301303 + if (drm_crtc_vblank_get(crtc) == 0) {
301344 + if (ret != 0) {
301375 + return 0;
301384 + if (ret != 0) {
301392 + return 0;
301413 + if (ret != 0) {
301440 + if (ret != 0) {
301445 + /* get the primary 0 plane on this crtc */
301446 + ret = hi_adp_plane_get_by_index(crtc, &primary, DRM_PLANE_TYPE_PRIMARY, 0);
301447 + if (ret != 0) {
301453 + if (ret != 0) {
301459 + if (ret != 0) {
301475 + if (ret != 0) {
301491 + if (ret != 0) {
301498 + for (i = 0; i < cap.crtc_num; i++) {
301502 + return 0;
301512 + for (i = 0; i < cap.crtc_num; i++) {
301531 + for (i = 0; i < cap.crtc_num; i++) {
301533 + if (ret != 0) {
301539 + for (j = 0; j < HI_DRM_MAX_PRIMARY_NUM; j++) {
301541 + if (ret != 0) {
301555 @@ -0,0 +1,17 @@
301578 @@ -0,0 +1,393 @@
301612 +#define DRIVER_MINOR 0
301651 + uint32_t handle = 0;
301659 + HI_DRM_ERR("gem object not finde fd %d, handle 0x%x", arg->fd, handle);
301674 + return 0;
301691 + return 0;
301694 + HI_DRM_ERR("drm_check_dumb_phy_addr, addr_start-addr_end [0x%llx-0x%llx]\n", addr_start, addr_…
301708 + if (ret != 0) {
301715 + return 0;
301717 + (void)memset(node, 0, sizeof(struct hi_drm_phys));
301722 + HI_DRM_ERR("gem object not finde handle 0x%x", args->handle);
301741 + return 0;
301829 + dev->mode_config.min_width = 0;
301830 + dev->mode_config.min_height = 0;
301843 + if (ret != 0) {
301848 + if (ret != 0) {
301853 + if (ret != 0) {
301858 + if (ret != 0) {
301866 + return 0;
301914 + if (ret != 0) {
301919 + ret = drm_dev_register(drm_dev, 0);
301920 + if (ret != 0) {
301927 + return 0;
301950 + return 0;
301974 index 000000000..0fcfdaecc
301977 @@ -0,0 +1,29 @@
302000 +} while (0)
302012 @@ -0,0 +1,43 @@
302048 + return 0;
302062 @@ -0,0 +1,27 @@
302095 @@ -0,0 +1,232 @@
302136 + if (ret != 0) {
302143 + if (ret != 0) {
302195 + return 0;
302203 + if (ret != 0) {
302215 + if (ret != 0) {
302249 + if (ret != 0) {
302267 + if (ret != 0) {
302293 + if (ret != 0) {
302299 + if (ret != 0) {
302313 + if (ret != 0) {
302318 + return 0;
302333 @@ -0,0 +1,16 @@
302355 @@ -0,0 +1,188 @@
302417 + return 0;
302433 + if (ret != 0) {
302445 + if (ret != 0) {
302470 + if (ret != 0) {
302488 + if (ret != 0) {
302504 + if (ret != 0) {
302511 + if (ret != 0) {
302526 + if (ret != 0) {
302532 + return 0;
302549 @@ -0,0 +1,17 @@
302572 @@ -0,0 +1,31 @@
302587 +#define DRM_HISILICON_GEM_FD_TO_PHYADDR 0x1
302609 @@ -0,0 +1,26 @@
302641 @@ -0,0 +1,2 @@
302649 @@ -0,0 +1,41 @@
302679 +#define VDMA_DATA_CMD 0x6
302696 @@ -0,0 +1,534 @@
302753 + && ((uintptr_t)ptr > 0))
302755 +int vdma_flag = 0;
302784 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
302785 + if (((dma_intr_status >> i) & 0x1) == 1) {
302838 + return 0;
302841 + for (i = 0; i < CHANNEL_NUM; i++) {
302847 + if (((tmp & 0x01) == 0x00) && (channel_intr == 0x00)) {
302866 + return 0;
302899 + reg[channel] &= 0xfffffc00;
302927 + return 0;
302931 + return 0;
302941 + unsigned int tmp_reg = 0;
302944 + return 0;
302949 + /* set rd dust address is ram 0 */
302950 + dmac_writew(hi_reg_vdma_base_va + DMAC_RD_DUSTB_ADDR, 0x04c11000);
302952 + /* set wr dust address is ram 0x1000 */
302953 + dmac_writew(hi_reg_vdma_base_va + DMAC_WR_DUSTB_ADDR, 0x04c11000);
302965 + for (i = 0; i < CHANNEL_NUM; i++) {
302973 + return 0;
302986 + return 0;
302997 + return 0;
303035 + int ret = 0;
303045 + wake_channel_flag[ulchnn] = 0;
303054 + if (hi_vdma_channelstart(ulchnn, psource, pdest) != 0) {
303075 + if (((uintptr_t)dst & 0xff) || ((uintptr_t)src & 0xff)) {
303092 + if (ret < 0) {
303095 + return 0;
303111 + res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
303134 + dma->irq = platform_get_irq(platdev, 0);
303135 + if (unlikely(dma->irq < 0)) {
303149 + for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
303165 + for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
303169 + vdma_flag = 0;
303172 + return 0;
303183 + for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
303189 + vdma_flag = 0;
303191 + return 0;
303201 + for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
303207 + return 0;
303236 @@ -0,0 +1,122 @@
303262 +#define DMAC_GLOBLE_CTRL 0x000
303263 +#define WFE_EN (0x1 << 23)
303264 +#define EVENT_BROADCAST_EN (0x1 << 21)
303265 +#define AUTO_CLK_GT_EN (0x1 << 17)
303266 +#define AUTO_PRI_EN (0x1 << 16)
303267 +#define WR_CMD_NUM_PER_ARB (0x4 << 12)
303268 +#define RD_CMD_NUM_PER_ARB (0x4 << 8)
303269 +#define WR_OTD_NUM (0xF << 4)
303270 +#define RD_OTD_NUM (0xF)
303272 +#define DMAC_PRI_THRESHOLD 0x004
303274 +#define DMAC_MMU_NMRR 0x008
303275 +#define DMAC_MMU_PRRR 0x00C
303277 +#define DMAC_RD_DUSTB_ADDR 0x010
303278 +#define DMAC_WR_DUSTB_ADDR 0x014
303280 +#define DMAC_CHANNEL_STATUS 0x01c
303281 +#define DMAC_WORK_DURATION 0x020
303282 +#define DMAC_INT_STATUS 0x02c
303284 +#define DMAC_CHANNEL_BASE 0x100
303285 +#define DMAC_CxSRCADDR(i) (DMAC_CHANNEL_BASE + 0x00 + 0x20 * i)
303286 +#define DMAC_CxDESTADDR(i) (DMAC_CHANNEL_BASE + 0x04 + 0x20 * i)
303287 +#define DMAC_CxLENGTH(i) (DMAC_CHANNEL_BASE + 0x08 + 0x20 * i)
303288 +#define DMAC_CxTTBR(i) (DMAC_CHANNEL_BASE + 0x0C + 0x20 * i)
303289 +#define DMAC_CxMISC(i) (DMAC_CHANNEL_BASE + 0x10 + 0x20 * i)
303290 +#define DMAC_CxINTR_RAW(i) (DMAC_CHANNEL_BASE + 0x14 + 0x20 * i)
303291 +#define CX_INT_STAT (0x1 << 4)
303292 +#define CX_INT_TC_RAW (0x1 << 3)
303293 +#define CX_INT_TE_RAW (0x1 << 2)
303294 +#define CX_INT_TM_RAW (0x1 << 1)
303295 +#define CX_INT_AP_RAW (0x1 << 0)
303297 +#define DMAC_INTR_ENABLE (0x1 << 8)
303300 +#define DMAC_CHANNEL_ENABLE (0x1 << 9)
303303 +#define AFE (0x1 << 6)
303306 +#define DEST_IS_KERNEL (0x1 << 2)
303307 +#define SRC_IS_KERNEL (0x1 << 1)
303310 +#define TTB_RGN (0x1 << 3) /* outer cache write back allocate */
303315 +#define TRE 0x001
303317 +#define PRRR 0xff0a81a8
303318 +#define NMRR 0x40e040e0
303320 +#define DMAC_SYNC_VAL 0x0
303334 +#define DMAC_SWIDTH_ERROR (DMAC_ERROR_BASE + 0xa)
303335 +#define DMAC_LLI_ADDRESS_INVALID (DMAC_ERROR_BASE + 0xb)
303336 +#define DMAC_TRANS_CONTROL_INVALID (DMAC_ERROR_BASE + 0xc)
303337 +#define DMAC_MEMORY_ALLOCATE_ERROR (DMAC_ERROR_BASE + 0xd)
303338 +#define DMAC_NOT_FINISHED (DMAC_ERROR_BASE + 0xe)
303340 +#define DMAC_TIMEOUT (DMAC_ERROR_BASE + 0xf)
303341 +#define DMAC_CHN_SUCCESS (DMAC_ERROR_BASE + 0x10)
303342 +#define DMAC_CHN_CONFIG_ERROR (DMAC_ERROR_BASE + 0x11)
303343 +#define DMAC_CHN_DATA_ERROR (DMAC_ERROR_BASE + 0x12)
303344 +#define DMAC_CHN_TIMEOUT (DMAC_ERROR_BASE + 0x13)
303345 +#define DMAC_CHN_ALLOCAT (DMAC_ERROR_BASE + 0x14)
303346 +#define DMAC_CHN_VACANCY (DMAC_ERROR_BASE + 0x15)
303352 +#define DMA_TRANS_OK 0x1
303353 +#define DMA_PAGE_FAULT 0x2
303354 +#define DMA_TRANS_FAULT 0x3
303364 @@ -0,0 +1,109 @@
303407 +} while (0)
303413 + long ret = 0;
303435 + return 0;
303440 + return 0;
303479 @@ -0,0 +1,21 @@
303506 @@ -0,0 +1,6 @@
303518 @@ -0,0 +1,1303 @@
303580 +#define RX 0
303582 +static int dmac_channel[CHANNEL_NUM] = {0, 1, 2, 3};
303591 +#define dma_err(fmt, ...) do {} while (0)
303616 +#define CLR_INT(i) ((*(unsigned int *)(dma_regbase+0x008)) = (1 << i))
303632 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
303633 + if ((((channel_status >> i) & 0x1) == 0x01)) {
303640 + if ((0x01 == ((channel_tc_status >> i) & 0x01)))
303642 + (0x01 << i));
303643 + else if ((0x01 == ((channel_err_status
303644 + >> i) & 0x01)))
303646 + (0x01 << i));
303652 + if ((0x01 == ((channel_tc_status >> i) & 0x01))) {
303654 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR, (0x01 << i));
303655 + } else if ((0x01 == ((channel_err_status >> i) & 0x01))) {
303657 + dmac_writew(dma->regbase + DMAC_INTERRCLR, (0x01 << i));
303682 + unsigned int time = 0;
303686 + for (j = 0; j < 3; j++) {
303688 + channel_tc_status[j] = (channel_status >> i) & 0x01;
303690 + channel_err_status[j] = (channel_status >> i) & 0x01;
303693 + if ((channel_tc_status[0] == 0x1) &&
303694 + (channel_tc_status[1] == 0x1) &&
303695 + (channel_tc_status[2] == 0x1)) {
303697 + dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x01 << i));
303699 + } else if ((channel_err_status[0] == 0x1) &&
303700 + (channel_err_status[1] == 0x1) &&
303701 + (channel_err_status[2] == 0x1)) {
303704 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x01 << i));
303723 + int status = 0;
303760 + for (i = 0; i < CHANNEL_NUM; i++) {
303765 + g_channelinfo = g_channelinfo & 0x00ff;
303767 + for (i = 0; i < CHANNEL_NUM; i++) {
303770 + if (0x00 == (channelinfo & 0x01)) {
303773 + (0x01 << dmac_channel[i]));
303775 + (0x01 << dmac_channel[i]));
303802 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x01 << channel));
303803 + dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x01 << channel));
303808 + return 0;
303823 + return 0;
303857 + if (tempvalue == 0) {
303860 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
303861 + dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
303862 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
303872 + if (ret < 0) {
303876 + if (request_irq(dma->irq, dmac_isr, 0, "hi_dma", dma)) {
303882 + return 0;
303888 + * ppheadlli[0]: memory physics address
303904 + ppheadlli[0] = (unsigned int)(dma_phys);
303907 + return 0;
303919 + dma_phys = (dma_addr_t)(ppheadlli[0]);
303925 + ppheadlli[0] = 0;
303926 + ppheadlli[1] = 0;
303927 + return 0;
303956 + dmac_writew(dma_regbase + DMAC_CxLLI(uwchannel_num), 0);
303957 + tmp_trasnsfer = (uwnumtransfers >> 2) & 0xfff;
303958 + tmp_trasnsfer = tmp_trasnsfer | (DMAC_CxCONTROL_M2M & (~0xfff));
303962 + return 0;
303984 + return 0;
303994 + int ret = 0;
303996 + if (channel < 0) {
304039 + phy_address = (unsigned int)(ppheadlli[0]);
304040 + dma_debug("phy_address: 0x%X\n", phy_address);
304042 + dma_debug("address: 0x%X\n", address);
304043 + for (j = 0; j < lli_num; j++) {
304044 + dma_debug("psource[%d]: 0x%X\n", j, psource[j]);
304048 + dma_debug("pdest[%d]: 0x%X\n", j, pdest[j]);
304053 + /* if the last node, next_lli_addr = 0 */
304055 + dmac_writew(address, 0);
304058 + (((phy_address + 8) & (~0x03)) |
304067 + (~0xfff)) | (length[j]) |
304068 + 0x80000000));
304071 + (((DMAC_CxCONTROL_LLIM2M_ISP & (~0xfff)) |
304072 + (length[j])) & 0x7fffffff));
304080 + return 0;
304091 + unsigned int lli_num = 0;
304092 + unsigned int last_lli = 0;
304098 + if ((totaltransfersize % uwnumtransfers) != 0) {
304103 + phy_address = (unsigned int)(ppheadlli[0]);
304105 + for (j = 0; j < lli_num; j++) {
304115 + dmac_writew(address, 0);
304118 + (((phy_address + 8) & (~0x03)) |
304124 + if ((j == (lli_num - 1)) && (last_lli == 0))
304126 + (~0xfff)) |
304128 + 0x80000000));
304132 + (~0xfff)) |
304135 + 0x80000000));
304138 + (((DMAC_CxCONTROL_LLIM2M & (~0xfff)) |
304139 + (uwnumtransfers >> 2)) & 0x7fffffff));
304146 + return 0;
304167 + reg_value &= 0xFFFFFFFE;
304179 + reg_value &= 0xFFFFFFFE;
304184 + reg_value = reg_value & 0x00ff;
304185 + count = 0;
304186 + while (((reg_value >> channel) & 0x1) == 1) {
304188 + reg_value = reg_value & 0x00ff;
304195 + return 0;
304221 + memset(&plli, 0, sizeof(plli));
304229 + dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << uwchannel_num));
304230 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << uwchannel_num));
304231 + dmac_writew(dma_regbase + DMAC_SYNC, 0x0);
304246 + return 0;
304259 + unsigned int temp = 0;
304273 + memset(&plli, 0, sizeof(plli));
304281 + dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << uwchannel_num));
304282 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << uwchannel_num));
304283 + dmac_writew(dma_regbase + DMAC_SYNC, 0x0);
304297 + return 0;
304310 + unsigned int uwtrans_control = 0;
304312 + unsigned int uwdst_addr = 0;
304313 + unsigned int uwsrc_addr = 0;
304326 + (uwchannel_num > CHANNEL_NUM) || (uwchannel_num < 0)) {
304340 + if (tmp & (~0x0fff)) {
304345 + tmp = tmp & 0xfff;
304347 + (g_peripheral[uwperipheralid].transfer_ctrl & (~0xfff));
304349 + (0x1 << (unsigned int)uwchannel_num));
304350 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << (unsigned int)uwchannel_num));
304360 + return 0;
304372 + unsigned int uwtrans_control = 0;
304374 + unsigned int uwdst_addr = 0;
304375 + unsigned int uwsrc_addr = 0;
304388 + (uwchannel_num > 3) || (uwchannel_num < 0)) {
304402 + if (tmp & (~0x0fff)) {
304407 + tmp = tmp & 0xfff;
304409 + (g_peripheral[uwperipheralid].transfer_ctrl & (~0xfff));
304411 + (0x1 << (unsigned int)uwchannel_num));
304412 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << (unsigned int)uwchannel_num));
304422 + return 0;
304432 + unsigned int dma_size = 0;
304436 + dma_count = 0;
304443 + while ((left_size >> 2) >= 0xffc) {
304444 + dma_size = 0xffc;
304455 + if (dmac_channelstart(ulchnn) != 0) {
304471 + if (dmac_channelstart(ulchnn) != 0) {
304479 + return 0;
304489 + unsigned int dma_size = 0;
304493 + dma_count = 0;
304502 + while ((left_size >> uwwidth) >= 0xffc) {
304503 + dma_size = 0xffc;
304508 + uwperipheralid, (dma_size << uwwidth), 0) < 0) {
304512 + if (dmac_channelstart(ulchnn) != 0) {
304524 + pr_debug("memaddr=0x%x\n", (unsigned int)(memaddr +
304529 + uwperipheralid, left_size, 0) < 0) {
304533 + if (dmac_channelstart(ulchnn) != 0) {
304546 + unsigned int dma_size = 0;
304551 + dma_count = 0;
304560 + while ((left_size >> uwwidth) >= 0xffc) {
304561 + dma_size = 0xffc;
304566 + uwperipheralid, (dma_size << uwwidth), 0) < 0) {
304570 + if (dmac_channelstart(ulchnn) != 0) {
304582 + pr_debug("memaddr=0x%x\n", (unsigned int)(memaddr +
304587 + uwperipheralid, left_size, 0) < 0) {
304591 + if (dmac_channelstart(ulchnn) != 0) {
304628 + if (dmac_channelstart(chnn) != 0) {
304640 + int ret = 0;
304644 + if (uwperipheralid < 0) {
304665 + if (uwperipheralid < 0) {
304695 + res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
304716 + dma->irq = platform_get_irq(platdev, 0);
304717 + if (unlikely(dma->irq < 0)) {
304730 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
304745 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
304751 + return 0;
304762 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
304768 + return 0;
304781 + if (tempvalue == 0) {
304784 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
304785 + dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
304786 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
304793 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
304797 + return 0;
304827 @@ -0,0 +1,90 @@
304857 +#define dma_debug(fmt, ...) do {} while (0);
304860 +#define DMAC_CONFIGURATIONx_HALT_DMA_ENABLE (0x01L<<18)
304861 +#define DMAC_CONFIGURATIONx_ACTIVE (0x01L<<17)
304863 +#define DMAC_CONFIGURATIONx_CHANNEL_DISABLE 0
304877 +#define DMAC_SWIDTH_ERROR (DMAC_ERROR_BASE+0xa)
304878 +#define DMAC_LLI_ADDRESS_INVALID (DMAC_ERROR_BASE+0xb)
304879 +#define DMAC_TRANS_CONTROL_INVALID (DMAC_ERROR_BASE+0xc)
304880 +#define DMAC_MEMORY_ALLOCATE_ERROR (DMAC_ERROR_BASE+0xd)
304881 +#define DMAC_NOT_FINISHED (DMAC_ERROR_BASE+0xe)
304883 +#define DMAC_TIMEOUT (DMAC_ERROR_BASE+0xf)
304884 +#define DMAC_CHN_SUCCESS (DMAC_ERROR_BASE+0x10)
304885 +#define DMAC_CHN_ERROR (DMAC_ERROR_BASE+0x11)
304886 +#define DMAC_CHN_TIMEOUT (DMAC_ERROR_BASE+0x12)
304887 +#define DMAC_CHN_ALLOCAT (DMAC_ERROR_BASE+0x13)
304888 +#define DMAC_CHN_VACANCY (DMAC_ERROR_BASE+0x14)
304890 +#define DMAC_CONFIGURATIONx_ACTIVE_NOT 0
304893 +#define DMAC_TRANS_SIZE 0xff0
304915 +/* #define PAGE_SIZE 0x1000 */
304923 @@ -0,0 +1,176 @@
304944 +#define DDRAM_ADRS 0x80000000 /* fixed */
304945 +#define DDRAM_SIZE 0x1FFFFFFF /* 512M DDR. */
304947 +#define FLASH_BASE 0x10000000
304948 +#define FLASH_SIZE 0x04000000 /* (32MB) */
304950 +#define DMAC_INTSTATUS 0X00
304951 +#define DMAC_INTTCSTATUS 0X04
304952 +#define DMAC_INTTCCLEAR 0X08
304953 +#define DMAC_INTERRORSTATUS 0X0C
304955 +#define DMAC_INTERRCLR 0X10
304956 +#define DMAC_RAWINTTCSTATUS 0X14
304957 +#define DMAC_RAWINTERRORSTATUS 0X18
304958 +#define DMAC_ENBLDCHNS 0X1C
304959 +#define DMAC_CONFIG 0X30
304960 +#define DMAC_SYNC 0X34
304962 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
304964 +#define DMAC_CxDISABLE 0x00
304965 +#define DMAC_CxENABLE 0x01
304968 +#define DMAC_CxBASE(i) (0x100 + i * 0x20)
304970 +#define DMAC_CxDESTADDR(i) (DMAC_CxBASE(i) + 0x04)
304971 +#define DMAC_CxLLI(i) (DMAC_CxBASE(i) + 0x08)
304972 +#define DMAC_CxCONTROL(i) (DMAC_CxBASE(i) + 0x0C)
304973 +#define DMAC_CxCONFIG(i) (DMAC_CxBASE(i) + 0x10)
304976 +#define DMAC_CxCONTROL_M2M 0x9d480000 /* Dwidth=32,burst size=4 */
304977 +#define DMAC_CxCONTROL_LLIM2M 0x0f480000 /* Dwidth=32,burst size=1 */
304978 +#define DMAC_CxCONTROL_LLIM2M_ISP 0x0b489000 /* Dwidth=32,burst size=1 */
304979 +#define DMAC_CxCONTROL_LLIP2M 0x0a000000
304980 +#define DMAC_CxCONTROL_LLIM2P 0x86089000
304981 +#define DMAC_CxLLI_LM 0x01
304985 +#define DMAC_CxCONFIG_M2M 0xc000
304986 +#define DMAC_CxCONFIG_LLIM2M 0xc000
304988 +/* #define DMAC_CxCONFIG_M2M 0x4001 */
304990 +#define DMAC_CHANNEL_DISABLE 0xfffffffe
304992 +#define DMAC_CxCONTROL_P2M 0x89409000
304993 +#define DMAC_CxCONFIG_P2M 0xd000
304995 +#define DMAC_CxCONTROL_M2P 0x86089000
304996 +#define DMAC_CxCONFIG_M2P 0xc800
304998 +#define DMAC_CxCONFIG_SIO_P2M 0x0000d000
304999 +#define DMAC_CxCONFIG_SIO_M2P 0x0000c800
305003 +#define DMAC_CONFIG_VAL 0x01
305005 +#define DMAC_SYNC_VAL 0x0
305012 +#define MMC_REG_BASE 0x10030000
305013 +#define MMC_RX_REG (MMC_REG_BASE + 0x100)
305014 +#define MMC_TX_REG (MMC_REG_BASE + 0x100)
305016 +#define UART0_REG_BASE 0x20080000
305017 +#define UART0_DATA_REG (UART0_REG_BASE + 0x0)
305019 +#define UART1_REG_BASE 0x20090000
305020 +#define UART1_DATA_REG (UART1_REG_BASE + 0x0)
305022 +#define UART2_REG_BASE 0x200A0000
305023 +#define UART2_DATA_REG (UART2_REG_BASE + 0x0)
305025 +#define UART3_REG_BASE 0x200B0000
305026 +#define UART3_DATA_REG (UART3_REG_BASE + 0x0)
305028 +#define SPI0_REG_BASE 0x200c0000
305029 +#define SPI0_DATA_REG (SPI0_REG_BASE + 0x08)
305031 +#define SPI1_REG_BASE 0x200e0000
305032 +#define SPI1_DATA_REG (SPI1_REG_BASE + 0x08)
305034 +#define I2C0_REG_BASE 0x200d0000
305035 +#define I2C0_DATA_REG (I2C0_REG_BASE + 0x10)
305037 +#define I2C1_REG_BASE 0x20240000
305038 +#define I2C1_DATA_REG (I2C1_REG_BASE + 0x10)
305040 +#define PERI_8BIT_MODE 0
305053 + /* periphal 0: I2C0/I2C1 RX */
305054 + { 0, I2C0_DATA_REG, 0x99000000, 0x1000, PERI_8BIT_MODE },
305056 + { 1, I2C0_DATA_REG, 0x96000000, 0x0840, PERI_8BIT_MODE },
305058 + { 2, I2C1_DATA_REG, 0x99000000, 0x1004, PERI_8BIT_MODE },
305060 + { 3, I2C1_DATA_REG, 0x96000000, 0x08c0, PERI_8BIT_MODE },
305087 + { 12, 0, 0, 0, 0 },
305090 + { 13, 0, 0, 0, 0 },
305093 + { 14, 0, 0, 0, 0 },
305096 + { 15, 0, 0, 0, 0 },
305105 @@ -0,0 +1,168 @@
305126 +#define DDRAM_ADRS 0x80000000 /* fixed */
305127 +#define DDRAM_SIZE 0x3FFFFFFF /* 1GB DDR. */
305129 +#define FLASH_BASE 0x10000000
305130 +#define FLASH_SIZE 0x04000000 /* (32MB) */
305133 +#define DMAC_INTSTATUS 0X00
305134 +#define DMAC_INTTCSTATUS 0X04
305135 +#define DMAC_INTTCCLEAR 0X08
305136 +#define DMAC_INTERRORSTATUS 0X0C
305138 +#define DMAC_INTERRCLR 0X10
305139 +#define DMAC_RAWINTTCSTATUS 0X14
305140 +#define DMAC_RAWINTERRORSTATUS 0X18
305141 +#define DMAC_ENBLDCHNS 0X1C
305142 +#define DMAC_CONFIG 0X30
305143 +#define DMAC_SYNC 0X34
305145 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
305147 +#define DMAC_CxDISABLE 0x00
305148 +#define DMAC_CxENABLE 0x01
305151 +#define DMAC_CxBASE(i) (0x100 + i * 0x20)
305153 +#define DMAC_CxDESTADDR(i) (DMAC_CxBASE(i) + 0x04)
305154 +#define DMAC_CxLLI(i) (DMAC_CxBASE(i) + 0x08)
305155 +#define DMAC_CxCONTROL(i) (DMAC_CxBASE(i) + 0x0C)
305156 +#define DMAC_CxCONFIG(i) (DMAC_CxBASE(i) + 0x10)
305159 +#define DMAC_CxCONTROL_M2M 0x9d480000 /* Dwidth=32,burst size=4 */
305160 +#define DMAC_CxCONTROL_LLIM2M 0x0f480000 /* Dwidth=32,burst size=1 */
305161 +#define DMAC_CxCONTROL_LLIM2M_ISP 0x0b489000 /* Dwidth=32,burst size=1 */
305162 +#define DMAC_CxLLI_LM 0x01
305164 +#define DMAC_CxCONFIG_M2M 0xc000
305165 +#define DMAC_CxCONFIG_LLIM2M 0xc000
305167 +/* #define DMAC_CxCONFIG_M2M 0x4001 */
305169 +#define DMAC_CHANNEL_DISABLE 0xfffffffe
305171 +#define DMAC_CxCONTROL_P2M 0x89409000
305172 +#define DMAC_CxCONFIG_P2M 0xd000
305174 +#define DMAC_CxCONTROL_M2P 0x86089000
305175 +#define DMAC_CxCONFIG_M2P 0xc800
305177 +#define DMAC_CxCONFIG_SIO_P2M 0x0000d000
305178 +#define DMAC_CxCONFIG_SIO_M2P 0x0000c800
305182 +#define DMAC_CONFIG_VAL 0x01
305184 +#define DMAC_SYNC_VAL 0x0
305191 +#define REG_BASE_UART0 0x20080000
305192 +#define UART0_DATA_REG (REG_BASE_UART0 + 0x0)
305194 +#define REG_BASE_UART1 0x20090000
305195 +#define UART1_DATA_REG (REG_BASE_UART1 + 0x0)
305197 +#define REG_BASE_UART2 0x200a0000
305198 +#define UART2_DATA_REG (REG_BASE_UART2 + 0x0)
305200 +#define REG_BASE_SPI0 0x200c0000
305201 +#define SPI0_DATA_REG (REG_BASE_SPI0 + 0x08)
305203 +#define REG_BASE_SPI1 0x200e0000
305204 +#define SPI1_DATA_REG (REG_BASE_SPI1 + 0x08)
305206 +#define REG_BASE_I2C0 0x200d0000
305207 +#define I2C0_DATA_REG (REG_BASE_I2C0 + 0x10)
305209 +#define REG_BASE_I2C1 0x20240000
305210 +#define I2C1_DATA_REG (REG_BASE_I2C1 + 0x10)
305212 +#define REG_BASE_I2C2 0x20250000
305213 +#define I2C2_DATA_REG (REG_BASE_I2C2 + 0x10)
305225 + /* periphal 0: I2C0 RX, 8bit width */
305226 + {0, I2C0_DATA_REG, 0x99000000, 0x1000, 0},
305229 + {1, I2C0_DATA_REG, 0x96000000, 0x0840, 0},
305232 + {2, I2C1_DATA_REG, 0x99000000, 0x1004, 0},
305235 + {3, I2C1_DATA_REG, 0x96000000, 0x08c0, 0},
305238 + {4, UART0_DATA_REG, 0x99000000, 0xd008, 0},
305241 + {5, UART0_DATA_REG, 0x96000000, 0xc940, 0},
305244 + {6, UART1_DATA_REG, 0x99000000, 0xd00c, 0},
305247 + {7, UART1_DATA_REG, 0x96000000, 0xc9c0, 0},
305250 + {8, UART2_DATA_REG, 0x99000000, 0xd010, 0},
305253 + {9, UART2_DATA_REG, 0x96000000, 0xca40, 0},
305256 + {10, I2C2_DATA_REG, 0x99000000, 0x1014, 0},
305259 + {11, I2C2_DATA_REG, 0x96000000, 0x0ac0, 0},
305262 + {12, 0, 0x99000000, 0xd018, 0},
305265 + {13, 0, 0x96000000, 0xcb40, 0},
305268 + {14, 0, 0x99000000, 0xd01c, 0},
305271 + {15, 0, 0x96000000, 0xcbc0, 0},
305279 @@ -0,0 +1,151 @@
305300 +#define DDR_MEM_BASE 0x80000000
305302 +#define DDRAM_SIZE 0x7FFFFFFF /* 2GB DDR. */
305304 +#define FLASH_BASE 0x10000000
305305 +#define FLASH_SIZE 0x04000000 /* (32MB) */
305307 +#define DMAC_INTSTATUS 0X00
305308 +#define DMAC_INTTCSTATUS 0X04
305309 +#define DMAC_INTTCCLEAR 0X08
305310 +#define DMAC_INTERRORSTATUS 0X0C
305312 +#define DMAC_INTERRCLR 0X10
305313 +#define DMAC_RAWINTTCSTATUS 0X14
305314 +#define DMAC_RAWINTERRORSTATUS 0X18
305315 +#define DMAC_ENBLDCHNS 0X1C
305316 +#define DMAC_CONFIG 0X30
305317 +#define DMAC_SYNC 0X34
305319 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
305321 +#define DMAC_CxDISABLE 0x00
305322 +#define DMAC_CxENABLE 0x01
305325 +#define DMAC_CxBASE(i) (0x100 + i * 0x20)
305327 +#define DMAC_CxDESTADDR(i) (DMAC_CxBASE(i) + 0x04)
305328 +#define DMAC_CxLLI(i) (DMAC_CxBASE(i) + 0x08)
305329 +#define DMAC_CxCONTROL(i) (DMAC_CxBASE(i) + 0x0C)
305330 +#define DMAC_CxCONFIG(i) (DMAC_CxBASE(i) + 0x10)
305333 +#define DMAC_CxCONTROL_M2M 0x9d480000 /* Dwidth=32,burst size=4 */
305334 +#define DMAC_CxCONTROL_LLIM2M 0x0f480000 /* Dwidth=32,burst size=1 */
305335 +#define DMAC_CxCONTROL_LLIM2M_ISP 0x0b489000 /* Dwidth=32,burst size=1 */
305336 +#define DMAC_CxCONTROL_LLIP2M 0x0a000000
305337 +#define DMAC_CxCONTROL_LLIM2P 0x86089000
305338 +#define DMAC_CxLLI_LM 0x01
305340 +#define DMAC_CxCONFIG_M2M 0xc000
305341 +#define DMAC_CxCONFIG_LLIM2M 0xc000
305343 +/* #define DMAC_CxCONFIG_M2M 0x4001 */
305345 +#define DMAC_CHANNEL_DISABLE 0xfffffffe
305347 +#define DMAC_CxCONTROL_P2M 0x89409000
305348 +#define DMAC_CxCONFIG_P2M 0xd000
305350 +#define DMAC_CxCONTROL_M2P 0x86089000
305351 +#define DMAC_CxCONFIG_M2P 0xc800
305353 +#define DMAC_CxCONFIG_SIO_P2M 0x0000d000
305354 +#define DMAC_CxCONFIG_SIO_M2P 0x0000c800
305358 +#define DMAC_CONFIG_VAL 0x01
305360 +#define DMAC_SYNC_VAL 0x0
305368 +#define REG_BASE_UART0 0x12080000
305369 +#define REG_BASE_UART1 0x12090000
305370 +#define REG_BASE_UART2 0x120a0000
305372 +#define REG_UART_DATA 0x0000
305379 +#define SSP_REG_BASE 0x120d0000
305380 +#define REG_SSP_DATA 0x0008
305385 +#define I2C_REG_BASE 0x120c0000
305386 +#define REG_I2C_DATA 0x0010
305400 + /* Request 0: UART0 Rx 8bit width */
305401 + { 0, UART0_DATA_REG, 0x99000000, 0xd000, 0 },
305404 + { 1, UART0_DATA_REG, 0x96000000, 0xc840, 0 },
305407 + { 2, UART1_DATA_REG, 0x99000000, 0xd004, 0 },
305410 + { 3, UART1_DATA_REG, 0x96000000, 0xc8c0, 0 },
305413 + { 4, UART2_DATA_REG, 0x99000000, 0xd008, 0 },
305416 + { 5, UART2_DATA_REG, 0x96000000, 0xc940, 0 },
305419 + { 6, SSP_DATA_REG, 0x99000000, 0xd00c, 0 },
305422 + { 7, SSP_DATA_REG, 0x96000000, 0xc9c0, 0 },
305425 + { 8, I2C_DATA_REG, 0x99000000, 0x1010, 0 },
305428 + { 9, I2C_DATA_REG, 0x96000000, 0x0a40, 0 },
305436 @@ -0,0 +1,166 @@
305457 +#define DDR_MEM_BASE 0x40000000
305459 +#define DDRAM_SIZE 0xbFFFFFFF /* 3GB DDR. */
305461 +#define FLASH_BASE 0x10000000
305462 +#define FLASH_SIZE 0x04000000 /* (32MB) */
305464 +#define DMAC_INTSTATUS 0X00
305465 +#define DMAC_INTTCSTATUS 0X04
305466 +#define DMAC_INTTCCLEAR 0X08
305467 +#define DMAC_INTERRORSTATUS 0X0C
305469 +#define DMAC_INTERRCLR 0X10
305470 +#define DMAC_RAWINTTCSTATUS 0X14
305471 +#define DMAC_RAWINTERRORSTATUS 0X18
305472 +#define DMAC_ENBLDCHNS 0X1C
305473 +#define DMAC_CONFIG 0X30
305474 +#define DMAC_SYNC 0X34
305476 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
305478 +#define DMAC_CxDISABLE 0x00
305479 +#define DMAC_CxENABLE 0x01
305482 +#define DMAC_CxBASE(i) (0x100 + i * 0x20)
305484 +#define DMAC_CxDESTADDR(i) (DMAC_CxBASE(i) + 0x04)
305485 +#define DMAC_CxLLI(i) (DMAC_CxBASE(i) + 0x08)
305486 +#define DMAC_CxCONTROL(i) (DMAC_CxBASE(i) + 0x0C)
305487 +#define DMAC_CxCONFIG(i) (DMAC_CxBASE(i) + 0x10)
305490 +#define DMAC_CxCONTROL_M2M 0x9d480000 /* Dwidth=32,burst size=4 */
305491 +#define DMAC_CxCONTROL_LLIM2M 0x0f480000 /* Dwidth=32,burst size=1 */
305492 +#define DMAC_CxCONTROL_LLIM2M_ISP 0x0b489000 /* Dwidth=32,burst size=1 */
305493 +#define DMAC_CxCONTROL_LLIP2M 0x0a000000
305494 +#define DMAC_CxCONTROL_LLIM2P 0x86089000
305495 +#define DMAC_CxLLI_LM 0x01
305497 +#define DMAC_CxCONFIG_M2M 0xc000
305498 +#define DMAC_CxCONFIG_LLIM2M 0xc000
305500 +/* #define DMAC_CxCONFIG_M2M 0x4001 */
305502 +#define DMAC_CHANNEL_DISABLE 0xfffffffe
305504 +#define DMAC_CxCONTROL_P2M 0x89409000
305505 +#define DMAC_CxCONFIG_P2M 0xd000
305507 +#define DMAC_CxCONTROL_M2P 0x86089000
305508 +#define DMAC_CxCONFIG_M2P 0xc800
305510 +#define DMAC_CxCONFIG_SIO_P2M 0x0000d000
305511 +#define DMAC_CxCONFIG_SIO_M2P 0x0000c800
305515 +#define DMAC_CONFIG_VAL 0x01
305517 +#define DMAC_SYNC_VAL 0x0
305525 +#define UART0_REG_BASE 0x12080000
305526 +#define UART1_REG_BASE 0x12090000
305527 +#define UART2_REG_BASE 0x120A0000
305528 +#define UART3_REG_BASE 0x12130000
305530 +#define REG_UART_DATA 0x0000
305538 +#define SSP_REG_BASE 0x120d0000
305539 +#define REG_SSP_DATA 0x0008
305543 +#define I2C0_REG_BASE 0x120c0000
305544 +#define I2C1_REG_BASE 0x122e0000
305546 +#define REG_I2C_DATA 0x0010
305560 + /* Request 0: UART0 Rx 8bit width */
305561 + { 0, UART0_DATA_REG, 0x99000000, 0xd000, 0 },
305564 + { 1, UART0_DATA_REG, 0x96000000, 0xc840, 0 },
305567 + { 2, UART1_DATA_REG, 0x99000000, 0xd004, 0 },
305570 + { 3, UART1_DATA_REG, 0x96000000, 0xc8c0, 0 },
305573 + { 4, UART2_DATA_REG, 0x99000000, 0xd008, 0 },
305576 + { 5, UART2_DATA_REG, 0x96000000, 0xc940, 0 },
305579 + { 6, SSP_DATA_REG, 0x99000000, 0xd00c, 0 },
305582 + { 7, SSP_DATA_REG, 0x96000000, 0xc9c0, 0 },
305585 + { 8, I2C0_DATA_REG, 0x99000000, 0x1010, 0 },
305588 + { 9, I2C0_DATA_REG, 0x96000000, 0x0a40, 0 },
305591 + { 10, UART3_DATA_REG, 0x99000000, 0xd014, 0 },
305594 + { 11, UART3_DATA_REG, 0x96000000, 0xcac0, 0 },
305597 + { 12, I2C1_DATA_REG, 0x99000000, 0x1018, 0 },
305600 + { 13, I2C1_DATA_REG, 0x96000000, 0x0b40, 0 },
305608 @@ -0,0 +1,131 @@
305629 +#define DDRAM_ADRS 0x80000000 /* fixed */
305630 +#define DDRAM_SIZE 0x1FFFFFFF /* 512M DDR. */
305632 +#define FLASH_BASE 0x10000000
305633 +#define FLASH_SIZE 0x04000000 /* (32MB) */
305635 +#define DMAC_INTSTATUS 0X00
305636 +#define DMAC_INTTCSTATUS 0X04
305637 +#define DMAC_INTTCCLEAR 0X08
305638 +#define DMAC_INTERRORSTATUS 0X0C
305640 +#define DMAC_INTERRCLR 0X10
305641 +#define DMAC_RAWINTTCSTATUS 0X14
305642 +#define DMAC_RAWINTERRORSTATUS 0X18
305643 +#define DMAC_ENBLDCHNS 0X1C
305644 +#define DMAC_CONFIG 0X30
305645 +#define DMAC_SYNC 0X34
305647 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
305649 +#define DMAC_CxDISABLE 0x00
305650 +#define DMAC_CxENABLE 0x01
305653 +#define DMAC_CxBASE(i) (0x100 + i * 0x20)
305655 +#define DMAC_CxDESTADDR(i) (DMAC_CxBASE(i) + 0x04)
305656 +#define DMAC_CxLLI(i) (DMAC_CxBASE(i) + 0x08)
305657 +#define DMAC_CxCONTROL(i) (DMAC_CxBASE(i) + 0x0C)
305658 +#define DMAC_CxCONFIG(i) (DMAC_CxBASE(i) + 0x10)
305661 +#define DMAC_CxCONTROL_M2M 0x9d480000 /* Dwidth=32,burst size=4 */
305662 +#define DMAC_CxCONTROL_LLIM2M 0x0f480000 /* Dwidth=32,burst size=1 */
305663 +#define DMAC_CxCONTROL_LLIM2M_ISP 0x0b489000 /* Dwidth=32,burst size=1 */
305664 +#define DMAC_CxLLI_LM 0x01
305668 +#define DMAC_CxCONFIG_M2M 0xc000
305669 +#define DMAC_CxCONFIG_LLIM2M 0xc000
305671 +/* #define DMAC_CxCONFIG_M2M 0x4001 */
305673 +#define DMAC_CHANNEL_DISABLE 0xfffffffe
305675 +#define DMAC_CxCONTROL_P2M 0x89409000
305676 +#define DMAC_CxCONFIG_P2M 0xd000
305678 +#define DMAC_CxCONTROL_M2P 0x86089000
305679 +#define DMAC_CxCONFIG_M2P 0xc800
305681 +#define DMAC_CxCONFIG_SIO_P2M 0x0000d000
305682 +#define DMAC_CxCONFIG_SIO_M2P 0x0000c800
305686 +#define DMAC_CONFIG_VAL 0x01
305688 +#define DMAC_SYNC_VAL 0x0
305695 +#define REG_BASE_I2C0 0x120c0000
305696 +#define I2C0_DATA_RXF (REG_BASE_I2C0 + 0x24)
305697 +#define I2C0_DATA_TXF (REG_BASE_I2C0 + 0x20)
305700 +#define REG_BASE_UART0 0x12080000
305701 +#define UART0_DATA_REG (REG_BASE_UART0 + 0x0)
305703 +#define REG_BASE_UART1 0x12090000
305704 +#define UART1_DATA_REG (REG_BASE_UART1 + 0x0)
305706 +#define REG_BASE_UART2 0x120a0000
305707 +#define UART2_DATA_REG (REG_BASE_UART2 + 0x0)
305714 + /* periphal 0: UART0 RX, 8bit width */
305715 + {0, UART0_DATA_REG, 0x99000000, 0xd000, 0},
305718 + {1, UART0_DATA_REG, 0x96000000, 0xc840, 0},
305721 + {2, UART1_DATA_REG, 0x99000000, 0xd004, 0},
305724 + {3, UART1_DATA_REG, 0x96000000, 0xc8c0, 0},
305727 + {4, UART2_DATA_REG, 0x99000000, 0xd008, 0},
305730 + {5, UART2_DATA_REG, 0x96000000, 0xc940, 0},
305733 + {6, I2C0_DATA_RXF, 0x99000000, 0x100c, 0},
305736 + {7, I2C0_DATA_TXF, 0x96000000, 0x9c0, 0},
305745 @@ -0,0 +1,29 @@
305780 @@ -0,0 +1,4 @@
305790 @@ -0,0 +1,107 @@
305815 +#define UART4_REG_BASE 0x120A4000
305816 +#define UART3_REG_BASE 0x120A3000
305817 +#define UART2_REG_BASE 0x120A2000
305818 +#define UART1_REG_BASE 0x120A1000
305819 +#define UART0_REG_BASE 0x120A0000
305821 +#define UART0_DR (UART0_REG_BASE + 0x0)
305822 +#define UART1_DR (UART1_REG_BASE + 0x0)
305823 +#define UART2_DR (UART2_REG_BASE + 0x0)
305824 +#define UART3_DR (UART3_REG_BASE + 0x0)
305825 +#define UART4_DR (UART4_REG_BASE + 0x0)
305827 +#define I2C7_REG_BASE 0x120B7000
305828 +#define I2C6_REG_BASE 0x120B6000
305829 +#define I2C5_REG_BASE 0x120B5000
305830 +#define I2C4_REG_BASE 0x120B4000
305831 +#define I2C3_REG_BASE 0x120B3000
305832 +#define I2C2_REG_BASE 0x120B2000
305833 +#define I2C1_REG_BASE 0x120B1000
305834 +#define I2C0_REG_BASE 0x120B0000
305836 +#define I2C0_TX_FIFO (I2C0_REG_BASE + 0x20)
305837 +#define I2C0_RX_FIFO (I2C0_REG_BASE + 0x24)
305839 +#define I2C1_TX_FIFO (I2C1_REG_BASE + 0x20)
305840 +#define I2C1_RX_FIFO (I2C1_REG_BASE + 0x24)
305842 +#define I2C2_TX_FIFO (I2C2_REG_BASE + 0x20)
305843 +#define I2C2_RX_FIFO (I2C2_REG_BASE + 0x24)
305845 +#define I2C3_TX_FIFO (I2C3_REG_BASE + 0x20)
305846 +#define I2C3_RX_FIFO (I2C3_REG_BASE + 0x24)
305848 +#define I2C4_TX_FIFO (I2C4_REG_BASE + 0x20)
305849 +#define I2C4_RX_FIFO (I2C4_REG_BASE + 0x24)
305851 +#define I2C5_TX_FIFO (I2C5_REG_BASE + 0x20)
305852 +#define I2C5_RX_FIFO (I2C5_REG_BASE + 0x24)
305854 +#define I2C6_TX_FIFO (I2C6_REG_BASE + 0x20)
305855 +#define I2C6_RX_FIFO (I2C6_REG_BASE + 0x24)
305857 +#define I2C7_TX_FIFO (I2C7_REG_BASE + 0x20)
305858 +#define I2C7_RX_FIFO (I2C7_REG_BASE + 0x24)
305860 +#define EDMAC_TX 0
305864 + {0, I2C0_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305865 + {1, I2C0_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305866 + {2, I2C1_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305867 + {3, I2C1_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305868 + {4, I2C2_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305869 + {5, I2C2_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305870 + {6, I2C3_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305871 + {7, I2C3_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305872 + {8, I2C4_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305873 + {9, I2C4_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305874 + {10, I2C5_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305875 + {11, I2C5_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305876 + {12, I2C6_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305877 + {13, I2C6_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305878 + {14, I2C7_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305879 + {15, I2C7_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305880 + {16, 0, DMAC_NOT_USE, 0, 0, 0},
305881 + {17, 0, DMAC_NOT_USE, 0, 0, 0},
305882 + {18, 0, DMAC_NOT_USE, 0, 0, 0},
305883 + {19, 0, DMAC_NOT_USE, 0, 0, 0},
305884 + {20, 0, DMAC_NOT_USE, 0, 0, 0},
305885 + {21, 0, DMAC_NOT_USE, 0, 0, 0},
305886 + {22, 0, DMAC_NOT_USE, 0, 0, 0},
305887 + {23, 0, DMAC_NOT_USE, 0, 0, 0},
305888 + {24, 0, DMAC_NOT_USE, 0, 0, 0},
305889 + {25, 0, DMAC_NOT_USE, 0, 0, 0},
305890 + {26, 0, DMAC_NOT_USE, 0, 0, 0},
305891 + {27, 0, DMAC_NOT_USE, 0, 0, 0},
305892 + {28, 0, DMAC_NOT_USE, 0, 0, 0},
305893 + {29, 0, DMAC_NOT_USE, 0, 0, 0},
305894 + {30, 0, DMAC_NOT_USE, 0, 0, 0},
305895 + {31, 0, DMAC_NOT_USE, 0, 0, 0},
305903 @@ -0,0 +1,83 @@
305928 +#define UART2_REG_BASE 0x12042000
305929 +#define UART1_REG_BASE 0x12041000
305930 +#define UART0_REG_BASE 0x12040000
305932 +#define UART0_DR (UART0_REG_BASE + 0x0)
305933 +#define UART1_DR (UART1_REG_BASE + 0x0)
305934 +#define UART2_DR (UART2_REG_BASE + 0x0)
305936 +#define I2C2_REG_BASE 0x12062000
305937 +#define I2C1_REG_BASE 0x12061000
305938 +#define I2C0_REG_BASE 0x12060000
305940 +#define I2C0_TX_FIFO (I2C0_REG_BASE + 0x20)
305941 +#define I2C0_RX_FIFO (I2C0_REG_BASE + 0x24)
305943 +#define I2C1_TX_FIFO (I2C1_REG_BASE + 0x20)
305944 +#define I2C1_RX_FIFO (I2C1_REG_BASE + 0x24)
305946 +#define I2C2_TX_FIFO (I2C2_REG_BASE + 0x20)
305947 +#define I2C2_RX_FIFO (I2C2_REG_BASE + 0x24)
305949 +#define EDMAC_TX 0
305953 + {0, I2C0_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305954 + {1, I2C0_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305955 + {2, I2C1_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305956 + {3, I2C1_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305957 + {4, I2C2_RX_FIFO, DMAC_HOST0, (0x40000004), PERI_8BIT_MODE, 0},
305958 + {5, I2C2_TX_FIFO, DMAC_HOST0, (0x80000004), PERI_8BIT_MODE, 0},
305959 + {6, 0, DMAC_NOT_USE, 0, 0, 0},
305960 + {7, 0, DMAC_NOT_USE, 0, 0, 0},
305961 + {8, 0, DMAC_NOT_USE, 0, 0, 0},
305962 + {9, 0, DMAC_NOT_USE, 0, 0, 0},
305963 + {10, 0, DMAC_NOT_USE, 0, 0, 0},
305964 + {11, 0, DMAC_NOT_USE, 0, 0, 0},
305965 + {12, 0, DMAC_NOT_USE, 0, 0, 0},
305966 + {13, 0, DMAC_NOT_USE, 0, 0, 0},
305967 + {14, 0, DMAC_NOT_USE, 0, 0, 0},
305968 + {15, 0, DMAC_NOT_USE, 0, 0, 0},
305969 + {16, 0, DMAC_NOT_USE, 0, 0, 0},
305970 + {17, 0, DMAC_NOT_USE, 0, 0, 0},
305971 + {18, 0, DMAC_NOT_USE, 0, 0, 0},
305972 + {19, 0, DMAC_NOT_USE, 0, 0, 0},
305973 + {20, 0, DMAC_NOT_USE, 0, 0, 0},
305974 + {21, 0, DMAC_NOT_USE, 0, 0, 0},
305975 + {22, 0, DMAC_NOT_USE, 0, 0, 0},
305976 + {23, 0, DMAC_NOT_USE, 0, 0, 0},
305977 + {24, 0, DMAC_NOT_USE, 0, 0, 0},
305978 + {25, 0, DMAC_NOT_USE, 0, 0, 0},
305979 + {26, 0, DMAC_NOT_USE, 0, 0, 0},
305980 + {27, 0, DMAC_NOT_USE, 0, 0, 0},
305981 + {28, 0, DMAC_NOT_USE, 0, 0, 0},
305982 + {29, 0, DMAC_NOT_USE, 0, 0, 0},
305983 + {30, 0, DMAC_NOT_USE, 0, 0, 0},
305984 + {31, 0, DMAC_NOT_USE, 0, 0, 0},
305989 index 000000000..0b3028bae
305992 @@ -0,0 +1,156 @@
306017 +#define UART8_REG_BASE 0x04548000
306018 +#define UART7_REG_BASE 0x04547000
306019 +#define UART6_REG_BASE 0x04546000
306020 +#define UART5_REG_BASE 0x04545000
306021 +#define UART4_REG_BASE 0x04544000
306022 +#define UART3_REG_BASE 0x04543000
306023 +#define UART2_REG_BASE 0x04542000
306024 +#define UART1_REG_BASE 0x04541000
306025 +#define UART0_REG_BASE 0x04540000
306027 +#define UART0_DR (UART0_REG_BASE + 0x0)
306028 +#define UART1_DR (UART1_REG_BASE + 0x0)
306029 +#define UART2_DR (UART2_REG_BASE + 0x0)
306030 +#define UART3_DR (UART3_REG_BASE + 0x0)
306031 +#define UART4_DR (UART4_REG_BASE + 0x0)
306032 +#define UART5_DR (UART4_REG_BASE + 0x0)
306033 +#define UART6_DR (UART4_REG_BASE + 0x0)
306034 +#define UART7_DR (UART4_REG_BASE + 0x0)
306035 +#define UART8_DR (UART4_REG_BASE + 0x0)
306037 +#define I2C9_REG_BASE 0x04569000
306038 +#define I2C8_REG_BASE 0x04568000
306039 +#define I2C7_REG_BASE 0x04567000
306040 +#define I2C6_REG_BASE 0x04566000
306041 +#define I2C5_REG_BASE 0x04565000
306042 +#define I2C4_REG_BASE 0x04564000
306043 +#define I2C3_REG_BASE 0x04563000
306044 +#define I2C2_REG_BASE 0x04562000
306045 +#define I2C1_REG_BASE 0x04561000
306046 +#define I2C0_REG_BASE 0x04560000
306048 +#define I2C0_TX_FIFO (I2C0_REG_BASE + 0x20)
306049 +#define I2C0_RX_FIFO (I2C0_REG_BASE + 0x24)
306051 +#define I2C1_TX_FIFO (I2C1_REG_BASE + 0x20)
306052 +#define I2C1_RX_FIFO (I2C1_REG_BASE + 0x24)
306054 +#define I2C2_TX_FIFO (I2C2_REG_BASE + 0x20)
306055 +#define I2C2_RX_FIFO (I2C2_REG_BASE + 0x24)
306057 +#define I2C3_TX_FIFO (I2C3_REG_BASE + 0x20)
306058 +#define I2C3_RX_FIFO (I2C3_REG_BASE + 0x24)
306060 +#define I2C4_TX_FIFO (I2C4_REG_BASE + 0x20)
306061 +#define I2C4_RX_FIFO (I2C4_REG_BASE + 0x24)
306063 +#define I2C5_TX_FIFO (I2C5_REG_BASE + 0x20)
306064 +#define I2C5_RX_FIFO (I2C5_REG_BASE + 0x24)
306066 +#define I2C6_TX_FIFO (I2C6_REG_BASE + 0x20)
306067 +#define I2C6_RX_FIFO (I2C6_REG_BASE + 0x24)
306069 +#define I2C7_TX_FIFO (I2C7_REG_BASE + 0x20)
306070 +#define I2C7_RX_FIFO (I2C7_REG_BASE + 0x24)
306072 +#define I2C8_TX_FIFO (I2C8_REG_BASE + 0x20)
306073 +#define I2C8_RX_FIFO (I2C8_REG_BASE + 0x24)
306075 +#define I2C9_TX_FIFO (I2C9_REG_BASE + 0x20)
306076 +#define I2C9_RX_FIFO (I2C9_REG_BASE + 0x24)
306079 +#define EDMAC_TX 0
306083 + {0, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306084 + {1, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306085 + {2, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306086 + {3, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306087 + {4, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306088 + {5, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306089 + {6, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306090 + {7, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306091 + {8, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306092 + {9, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306093 + {10, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306094 + {11, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306095 + {12, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306096 + {13, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306097 + {14, I2C0_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306098 + {15, I2C0_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306099 + {16, I2C1_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306100 + {17, I2C1_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306101 + {18, I2C2_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306102 + {19, I2C2_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306103 + {20, I2C3_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306104 + {21, I2C3_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306105 + {22, I2C4_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306106 + {23, I2C4_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306107 + {24, I2C5_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306108 + {25, I2C5_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306109 + {26, I2C6_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306110 + {27, I2C6_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306111 + {28, I2C7_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306112 + {29, I2C7_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306113 + {30, I2C8_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306114 + {31, I2C8_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306115 + {32, I2C9_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306116 + {33, I2C9_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306117 + {34, 0, DMAC_NOT_USE, 0, 0, 0},
306118 + {35, 0, DMAC_NOT_USE, 0, 0, 0},
306119 + {36, 0, DMAC_NOT_USE, 0, 0, 0},
306120 + {37, 0, DMAC_NOT_USE, 0, 0, 0},
306121 + {38, 0, DMAC_NOT_USE, 0, 0, 0},
306122 + {39, 0, DMAC_NOT_USE, 0, 0, 0},
306123 + {40, 0, DMAC_NOT_USE, 0, 0, 0},
306124 + {41, 0, DMAC_NOT_USE, 0, 0, 0},
306125 + {42, 0, DMAC_NOT_USE, 0, 0, 0},
306126 + {43, 0, DMAC_NOT_USE, 0, 0, 0},
306127 + {44, 0, DMAC_NOT_USE, 0, 0, 0},
306128 + {45, 0, DMAC_NOT_USE, 0, 0, 0},
306129 + {46, 0, DMAC_NOT_USE, 0, 0, 0},
306130 + {47, 0, DMAC_NOT_USE, 0, 0, 0},
306131 + {48, 0, DMAC_NOT_USE, 0, 0, 0},
306132 + {49, 0, DMAC_NOT_USE, 0, 0, 0},
306133 + {50, 0, DMAC_NOT_USE, 0, 0, 0},
306134 + {51, 0, DMAC_NOT_USE, 0, 0, 0},
306135 + {52, 0, DMAC_NOT_USE, 0, 0, 0},
306136 + {53, 0, DMAC_NOT_USE, 0, 0, 0},
306137 + {54, 0, DMAC_NOT_USE, 0, 0, 0},
306138 + {55, 0, DMAC_NOT_USE, 0, 0, 0},
306139 + {56, 0, DMAC_NOT_USE, 0, 0, 0},
306140 + {57, 0, DMAC_NOT_USE, 0, 0, 0},
306141 + {58, 0, DMAC_NOT_USE, 0, 0, 0},
306142 + {59, 0, DMAC_NOT_USE, 0, 0, 0},
306143 + {60, 0, DMAC_NOT_USE, 0, 0, 0},
306144 + {61, 0, DMAC_NOT_USE, 0, 0, 0},
306145 + {62, 0, DMAC_NOT_USE, 0, 0, 0},
306146 + {63, 0, DMAC_NOT_USE, 0, 0, 0},
306154 @@ -0,0 +1,140 @@
306179 +#define UART4_REG_BASE 0x12104000
306180 +#define UART3_REG_BASE 0x12103000
306181 +#define UART2_REG_BASE 0x12102000
306182 +#define UART1_REG_BASE 0x12101000
306183 +#define UART0_REG_BASE 0x12100000
306185 +#define UART0_DR (UART0_REG_BASE + 0x0)
306186 +#define UART1_DR (UART1_REG_BASE + 0x0)
306187 +#define UART2_DR (UART2_REG_BASE + 0x0)
306188 +#define UART3_DR (UART3_REG_BASE + 0x0)
306189 +#define UART4_DR (UART4_REG_BASE + 0x0)
306191 +#define I2C11_REG_BASE 0x1211b000
306192 +#define I2C10_REG_BASE 0x1211a000
306193 +#define I2C9_REG_BASE 0x12119000
306194 +#define I2C8_REG_BASE 0x12118000
306195 +#define I2C7_REG_BASE 0x12117000
306196 +#define I2C6_REG_BASE 0x12116000
306197 +#define I2C5_REG_BASE 0x12115000
306198 +#define I2C4_REG_BASE 0x12114000
306199 +#define I2C3_REG_BASE 0x12113000
306200 +#define I2C2_REG_BASE 0x12112000
306201 +#define I2C1_REG_BASE 0x12111000
306202 +#define I2C0_REG_BASE 0x12110000
306204 +#define I2C0_TX_FIFO (I2C0_REG_BASE + 0x20)
306205 +#define I2C0_RX_FIFO (I2C0_REG_BASE + 0x24)
306207 +#define I2C1_TX_FIFO (I2C1_REG_BASE + 0x20)
306208 +#define I2C1_RX_FIFO (I2C1_REG_BASE + 0x24)
306210 +#define I2C2_TX_FIFO (I2C2_REG_BASE + 0x20)
306211 +#define I2C2_RX_FIFO (I2C2_REG_BASE + 0x24)
306213 +#define I2C3_TX_FIFO (I2C3_REG_BASE + 0x20)
306214 +#define I2C3_RX_FIFO (I2C3_REG_BASE + 0x24)
306216 +#define I2C4_TX_FIFO (I2C4_REG_BASE + 0x20)
306217 +#define I2C4_RX_FIFO (I2C4_REG_BASE + 0x24)
306219 +#define I2C5_TX_FIFO (I2C5_REG_BASE + 0x20)
306220 +#define I2C5_RX_FIFO (I2C5_REG_BASE + 0x24)
306222 +#define I2C6_TX_FIFO (I2C6_REG_BASE + 0x20)
306223 +#define I2C6_RX_FIFO (I2C6_REG_BASE + 0x24)
306225 +#define I2C7_TX_FIFO (I2C7_REG_BASE + 0x20)
306226 +#define I2C7_RX_FIFO (I2C7_REG_BASE + 0x24)
306228 +#define I2C8_TX_FIFO (I2C8_REG_BASE + 0x20)
306229 +#define I2C8_RX_FIFO (I2C8_REG_BASE + 0x24)
306231 +#define I2C9_TX_FIFO (I2C9_REG_BASE + 0x20)
306232 +#define I2C9_RX_FIFO (I2C9_REG_BASE + 0x24)
306234 +#define I2C10_TX_FIFO (I2C10_REG_BASE + 0x20)
306235 +#define I2C10_RX_FIFO (I2C10_REG_BASE + 0x24)
306237 +#define I2C11_TX_FIFO (I2C11_REG_BASE + 0x20)
306238 +#define I2C11_RX_FIFO (I2C11_REG_BASE + 0x24)
306241 +#define EDMAC_TX 0
306245 + {0, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306246 + {1, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306247 + {2, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306248 + {3, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306249 + {4, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306250 + {5, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306251 + {6, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306252 + {7, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306253 + {8, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306254 + {9, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306255 + {10, I2C0_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306256 + {11, I2C0_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306257 + {12, I2C1_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306258 + {13, I2C1_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306259 + {14, I2C2_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306260 + {15, I2C2_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306261 + {16, I2C3_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306262 + {17, I2C3_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306263 + {18, I2C4_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306264 + {19, I2C4_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306265 + {20, I2C5_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306266 + {21, I2C5_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306267 + {22, I2C6_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306268 + {23, I2C6_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306269 + {24, I2C7_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306270 + {25, I2C7_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306271 + {26, I2C8_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306272 + {27, I2C8_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306273 + {28, I2C9_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306274 + {29, I2C9_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306275 + {30, I2C10_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306276 + {31, I2C10_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306277 + {32, I2C11_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306278 + {33, I2C11_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306279 + {34, 0, DMAC_NOT_USE, 0, 0, 0},
306280 + {35, 0, DMAC_NOT_USE, 0, 0, 0},
306281 + {36, 0, DMAC_NOT_USE, 0, 0, 0},
306282 + {37, 0, DMAC_NOT_USE, 0, 0, 0},
306283 + {38, 0, DMAC_NOT_USE, 0, 0, 0},
306284 + {39, 0, DMAC_NOT_USE, 0, 0, 0},
306285 + {40, 0, DMAC_NOT_USE, 0, 0, 0},
306286 + {41, 0, DMAC_NOT_USE, 0, 0, 0},
306287 + {42, 0, DMAC_NOT_USE, 0, 0, 0},
306288 + {43, 0, DMAC_NOT_USE, 0, 0, 0},
306289 + {44, 0, DMAC_NOT_USE, 0, 0, 0},
306290 + {45, 0, DMAC_NOT_USE, 0, 0, 0},
306291 + {46, 0, DMAC_NOT_USE, 0, 0, 0},
306292 + {47, 0, DMAC_NOT_USE, 0, 0, 0},
306300 @@ -0,0 +1,90 @@
306327 +#define EDMAC_RX 0
306329 +#define I2C0_REG_BASE 0x011060000
306330 +#define I2C1_REG_BASE 0x011061000
306331 +#define UART0_REG_BASE 0x011040000
306332 +#define UART1_REG_BASE 0x011041000
306333 +#define UART2_REG_BASE 0x011042000
306334 +#define UART3_REG_BASE 0x011043000
306335 +#define UART4_REG_BASE 0x011044000
306336 +#define SPI_REG_BASE 0x011070000
306338 +#define I2C0_RX_FIFO (I2C0_REG_BASE + 0x0024)
306339 +#define I2C0_TX_FIFO (I2C0_REG_BASE + 0x0020)
306340 +#define I2C1_RX_FIFO (I2C1_REG_BASE + 0x0024)
306341 +#define I2C1_TX_FIFO (I2C1_REG_BASE + 0x0020)
306352 +#define SPI_RX_FIFO (0x011070000 + 0x0008)
306353 +#define SPI_TX_FIFO (0x011070000 + 0x0008)
306357 + { 0, I2C0_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306358 + { 1, I2C0_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 1},
306359 + { 2, I2C1_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 2},
306360 + { 3, I2C1_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 3},
306361 + { 4, 0, DMAC_NOT_USE, 0, 0, 0},
306362 + { 5, 0, DMAC_NOT_USE, 0, 0, 0},
306363 + { 6, 0, DMAC_NOT_USE, 0, 0, 0},
306364 + { 7, 0, DMAC_NOT_USE, 0, 0, 0},
306365 + { 8, 0, DMAC_NOT_USE, 0, 0, 0},
306366 + { 9, 0, DMAC_NOT_USE, 0, 0, 0},
306367 + {10, 0, DMAC_NOT_USE, 0, 0, 0},
306368 + {11, 0, DMAC_NOT_USE, 0, 0, 0},
306369 + {12, 0, DMAC_NOT_USE, 0, 0, 0},
306370 + {13, 0, DMAC_NOT_USE, 0, 0, 0},
306371 + {14, 0, DMAC_NOT_USE, 0, 0, 0},
306372 + {15, 0, DMAC_NOT_USE, 0, 0, 0},
306373 + {16, UART0_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 16},
306374 + {17, UART0_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 17},
306375 + {18, UART1_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 18},
306376 + {19, UART1_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 19},
306377 + {20, UART2_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 20},
306378 + {21, UART2_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 21},
306379 + {22, UART3_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 22},
306380 + {23, UART3_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 23},
306381 + {24, UART4_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 24},
306382 + {25, UART4_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 25},
306383 + {26, SPI_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 26},
306384 + {27, SPI_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 27},
306385 + {28, 0, DMAC_NOT_USE, 0, 0, 0},
306386 + {29, 0, DMAC_NOT_USE, 0, 0, 0},
306387 + {30, 0, DMAC_NOT_USE, 0, 0, 0},
306388 + {31, 0, DMAC_NOT_USE, 0, 0, 0}
306396 @@ -0,0 +1,140 @@
306421 +#define UART4_REG_BASE 0x12104000
306422 +#define UART3_REG_BASE 0x12103000
306423 +#define UART2_REG_BASE 0x12102000
306424 +#define UART1_REG_BASE 0x12101000
306425 +#define UART0_REG_BASE 0x12100000
306427 +#define UART0_DR (UART0_REG_BASE + 0x0)
306428 +#define UART1_DR (UART1_REG_BASE + 0x0)
306429 +#define UART2_DR (UART2_REG_BASE + 0x0)
306430 +#define UART3_DR (UART3_REG_BASE + 0x0)
306431 +#define UART4_DR (UART4_REG_BASE + 0x0)
306433 +#define I2C11_REG_BASE 0x1211b000
306434 +#define I2C10_REG_BASE 0x1211a000
306435 +#define I2C9_REG_BASE 0x12119000
306436 +#define I2C8_REG_BASE 0x12118000
306437 +#define I2C7_REG_BASE 0x12117000
306438 +#define I2C6_REG_BASE 0x12116000
306439 +#define I2C5_REG_BASE 0x12115000
306440 +#define I2C4_REG_BASE 0x12114000
306441 +#define I2C3_REG_BASE 0x12113000
306442 +#define I2C2_REG_BASE 0x12112000
306443 +#define I2C1_REG_BASE 0x12111000
306444 +#define I2C0_REG_BASE 0x12110000
306446 +#define I2C0_TX_FIFO (I2C0_REG_BASE + 0x20)
306447 +#define I2C0_RX_FIFO (I2C0_REG_BASE + 0x24)
306449 +#define I2C1_TX_FIFO (I2C1_REG_BASE + 0x20)
306450 +#define I2C1_RX_FIFO (I2C1_REG_BASE + 0x24)
306452 +#define I2C2_TX_FIFO (I2C2_REG_BASE + 0x20)
306453 +#define I2C2_RX_FIFO (I2C2_REG_BASE + 0x24)
306455 +#define I2C3_TX_FIFO (I2C3_REG_BASE + 0x20)
306456 +#define I2C3_RX_FIFO (I2C3_REG_BASE + 0x24)
306458 +#define I2C4_TX_FIFO (I2C4_REG_BASE + 0x20)
306459 +#define I2C4_RX_FIFO (I2C4_REG_BASE + 0x24)
306461 +#define I2C5_TX_FIFO (I2C5_REG_BASE + 0x20)
306462 +#define I2C5_RX_FIFO (I2C5_REG_BASE + 0x24)
306464 +#define I2C6_TX_FIFO (I2C6_REG_BASE + 0x20)
306465 +#define I2C6_RX_FIFO (I2C6_REG_BASE + 0x24)
306467 +#define I2C7_TX_FIFO (I2C7_REG_BASE + 0x20)
306468 +#define I2C7_RX_FIFO (I2C7_REG_BASE + 0x24)
306470 +#define I2C8_TX_FIFO (I2C8_REG_BASE + 0x20)
306471 +#define I2C8_RX_FIFO (I2C8_REG_BASE + 0x24)
306473 +#define I2C9_TX_FIFO (I2C9_REG_BASE + 0x20)
306474 +#define I2C9_RX_FIFO (I2C9_REG_BASE + 0x24)
306476 +#define I2C10_TX_FIFO (I2C10_REG_BASE + 0x20)
306477 +#define I2C10_RX_FIFO (I2C10_REG_BASE + 0x24)
306479 +#define I2C11_TX_FIFO (I2C11_REG_BASE + 0x20)
306480 +#define I2C11_RX_FIFO (I2C11_REG_BASE + 0x24)
306483 +#define EDMAC_TX 0
306487 + {0, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306488 + {1, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306489 + {2, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306490 + {3, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306491 + {4, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306492 + {5, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306493 + {6, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306494 + {7, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306495 + {8, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306496 + {9, 0, DMAC_NOT_USE, 0, PERI_8BIT_MODE, 0},
306497 + {10, I2C0_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306498 + {11, I2C0_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306499 + {12, I2C1_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306500 + {13, I2C1_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306501 + {14, I2C2_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306502 + {15, I2C2_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306503 + {16, I2C3_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306504 + {17, I2C3_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306505 + {18, I2C4_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306506 + {19, I2C4_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306507 + {20, I2C5_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306508 + {21, I2C5_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306509 + {22, I2C6_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306510 + {23, I2C6_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306511 + {24, I2C7_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306512 + {25, I2C7_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306513 + {26, I2C8_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306514 + {27, I2C8_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306515 + {28, I2C9_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306516 + {29, I2C9_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306517 + {30, I2C10_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306518 + {31, I2C10_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306519 + {32, I2C11_TX_FIFO, DMAC_HOST1, (0x80000004), PERI_8BIT_MODE, 0},
306520 + {33, I2C11_RX_FIFO, DMAC_HOST1, (0x40000004), PERI_8BIT_MODE, 0},
306521 + {34, 0, DMAC_NOT_USE, 0, 0, 0},
306522 + {35, 0, DMAC_NOT_USE, 0, 0, 0},
306523 + {36, 0, DMAC_NOT_USE, 0, 0, 0},
306524 + {37, 0, DMAC_NOT_USE, 0, 0, 0},
306525 + {38, 0, DMAC_NOT_USE, 0, 0, 0},
306526 + {39, 0, DMAC_NOT_USE, 0, 0, 0},
306527 + {40, 0, DMAC_NOT_USE, 0, 0, 0},
306528 + {41, 0, DMAC_NOT_USE, 0, 0, 0},
306529 + {42, 0, DMAC_NOT_USE, 0, 0, 0},
306530 + {43, 0, DMAC_NOT_USE, 0, 0, 0},
306531 + {44, 0, DMAC_NOT_USE, 0, 0, 0},
306532 + {45, 0, DMAC_NOT_USE, 0, 0, 0},
306533 + {46, 0, DMAC_NOT_USE, 0, 0, 0},
306534 + {47, 0, DMAC_NOT_USE, 0, 0, 0},
306542 @@ -0,0 +1,946 @@
306613 +unsigned long pllihead[2] = {0, 0};
306638 + for (i = 0; i < HIEDMAC_CHANNEL_NUM; i++) {
306665 + channel_status = (channel_status >> i) & 0x01;
306668 + channel_tc_status = (channel_tc_status >> i) & 0x01;
306676 + channel_tc_status = (channel_tc_status >> i) & 0x01;
306683 + channel_err_status[0] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR1);
306684 + channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
306686 + channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
306688 + channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
306690 + if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
306692 + channel_err_status[0] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR1);
306718 + if (channel < 0 || channel > HIEDMAC_CHANNEL_NUM - 1) {
306719 + hiedmacv310_error("invalid channel,channel=%0d\n", channel);
306725 + return 0;
306734 + if ((channel >= 0) && (channel < HIEDMAC_CHANNEL_NUM))
306737 + return 0;
306756 + if ((channel >= 0) && (channel < HIEDMAC_CHANNEL_NUM))
306765 + int ret = 0;
306767 + if (channel < 0)
306822 + hiedmacv310_writel(memaddr & 0xffffffff,
306825 + hiedmacv310_writel((memaddr >> 32) & 0xffffffff,
306828 + hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n",
306831 + hiedmacv310_writel(g_peripheral[uwperipheralid].peri_addr & 0xffffffff,
306834 + hiedmacv310_writel((g_peripheral[uwperipheralid].peri_addr >> 32) & 0xffffffff,
306837 + hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n",
306840 + hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn));
306841 + hiedmacv310_trace(4, "HIEDMAC_Cx_LLI_L = 0x%x\n",
306845 + hiedmacv310_trace(4, "HIEDMAC_Cx_CNT0 = 0x%x\n",
306852 + hiedmacv310_trace(4, "HIEDMAC_Cx_CONFIG = 0x%x\n", temp);
306878 + hiedmacv310_writel(memaddr & 0xffffffff,
306881 + hiedmacv310_writel((memaddr >> 32) & 0xffffffff,
306884 + hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n",
306887 + hiedmacv310_writel(g_peripheral[uwperipheralid].peri_addr & 0xffffffff,
306890 + hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(ulchnn));
306892 + hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n",
306895 + hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn));
306896 + hiedmacv310_trace(4, "HIEDMAC_Cx_LLI_L = 0x%x\n",
306900 + hiedmacv310_trace(4, "HIEDMAC_Cx_CNT0 = 0x%x\n",
306907 + hiedmacv310_trace(4, "HIEDMAC_Cx_CONFIG = 0x%x\n", temp);
306915 + int ret = 0;
306919 + if (uwperipheralid < 0) {
306941 + if (uwperipheralid < 0) {
306965 + int lli_num = 0;
306970 + if (uwnumtransfers == 0)
306974 + if ((totaltransfersize % uwnumtransfers) != 0)
306979 + phy_address = ppheadlli[0];
306981 + hiedmacv310_trace(4, "phy_address: 0x%lx\n", phy_address);
306982 + hiedmacv310_trace(4, "address: 0x%p\n", plli);
306983 + for (j = 0; j < lli_num; j++) {
306984 + memset(plli, 0x0, sizeof(dmac_lli));
306986 + * at the last transfer, chain_en should be set to 0x0;
306987 + * others tansfer,chain_en should be set to 0x2;
307008 + return 0;
307021 + hiedmacv310_trace(4, "plli.src_addr: 0x%lx\n", plli->src_addr);
307022 + hiedmacv310_trace(4, "plli.dst_addr: 0x%lx\n", plli->dest_addr);
307023 + hiedmacv310_trace(4, "plli.next_lli: 0x%lx\n", plli->next_lli);
307024 + hiedmacv310_trace(4, "plli.count: 0x%d\n", plli->count);
307026 + hiedmacv310_writel(plli->dest_addr & 0xffffffff,
307029 + hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff,
307034 + hiedmacv310_writel(plli->src_addr & 0xffffffff,
307037 + hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff,
307040 + hiedmacv310_writel(plli->dest_addr & 0xffffffff,
307043 + hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff,
307049 + return 0;
307061 + if (uwnumtransfers > HIEDMAC_TRANS_MAXSIZE || uwnumtransfers == 0) {
307065 + hiedmacv310_trace(4, "channel[%d],source=0x%lx,dest=0x%lx,length=%d\n",
307068 + hiedmacv310_writel(psource & 0xffffffff,
307070 + hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n",
307073 + hiedmacv310_writel((psource >> 32) & 0xffffffff,
307075 + hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_H = 0x%x\n",
307078 + hiedmacv310_writel(pdest & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(i));
307079 + hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n",
307082 + hiedmacv310_writel((pdest >> 32) & 0xffffffff,
307084 + hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_H = 0x%x\n",
307087 + hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(i));
307094 + return 0;
307104 + unsigned int dma_size = 0;
307108 + dma_count = 0;
307110 + if (ulchnn < 0) {
307114 + hiedmacv310_trace(6, "using channel[%d],source=0x%lx,dest=0x%lx,length=%d\n",
307136 + return 0;
307151 + int ret = 0;
307155 + if (chnn < 0) {
307162 + if (pllihead[0] == 0) {
307163 + hiedmacv310_error("ppheadlli[0] is NULL.\n");
307189 + * ppheadlli[0]: memory physics address
307206 + ppheadlli[0] = (unsigned long)(dma_phys);
307213 + return 0;
307221 + int i = 0;
307222 + unsigned int count = 0;
307223 + unsigned int offset = 0;
307224 + unsigned ctrl = 0;
307226 + for (i = 0; i < EDMAC_MAX_PERIPHERALS; i++) {
307233 + offset = hiedmac->misc_ctrl_base + (count & (~0x3));
307235 + ctrl &= ~(0x3f << ((count & 0x3) << 3));
307236 + ctrl |= peripheral_info[i].peri_id << ((count & 0x3) << 3);
307244 + return 0;
307279 + res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
307292 + hiedmac->misc_regmap = 0;
307307 + hiedmac->irq = platform_get_irq(platdev, 0);
307308 + if (unlikely(hiedmac->irq < 0))
307328 + return 0;
307337 + unsigned int channel_tc_status = 0;
307338 + unsigned int channel_status = 0;
307339 + int i = 0;
307340 + unsigned int mask = 0;
307344 + hiedmacv310_error("channel_status = 0x%x\n", channel_status);
307348 + for (i = 0; i < hiedmac->channels; i++) {
307349 + channel_status = (channel_status >> i) & 0x1;
307352 + channel_tc_status = (channel_tc_status >> i) & 0x01;
307357 + channel_tc_status = (channel_tc_status >> i) & 0x01;
307361 + channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
307362 + channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
307364 + channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
307366 + channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
307368 + if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
307369 + hiedmacv310_error("Error in hiedmac %d finish!,ERR1 = 0x%x,ERR2 = 0x%x,ERR3 = 0x%x\n",
307370 + i, channel_err_status[0], channel_err_status[1], channel_err_status[2]);
307390 + int ret = 0;
307391 + int i = 0;
307430 + for (i = 0; i < HIEDMAC_CHANNEL_NUM; i++)
307437 + if (ret < 0)
307442 + ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
307448 + return 0;
307458 + int err = 0;
307494 @@ -0,0 +1,184 @@
307535 +} while (0)
307545 +} while (0)
307551 +} while (0)
307555 +#define hiedmacv310_trace(level, msg...) do { } while (0)
307556 +#define hiedmacv310_assert(level, msg...) do { } while (0)
307557 +#define hiedmacv310_error(level, msg...) do { } while (0)
307565 +} while (0)
307568 +#define MAX_TRANSFER_BYTES 0xffff
307571 +#define HIEDMAC_INT_STAT (0x0)
307572 +#define HIEDMAC_INT_TC1 (0x4)
307573 +#define HIEDMAC_INT_TC2 (0x8)
307574 +#define HIEDMAC_INT_ERR1 (0xc)
307575 +#define HIEDMAC_INT_ERR2 (0x10)
307576 +#define HIEDMAC_INT_ERR3 (0x14)
307577 +#define HIEDMAC_INT_TC1_MASK (0x18)
307578 +#define HIEDMAC_INT_TC2_MASK (0x1c)
307579 +#define HIEDMAC_INT_ERR1_MASK (0x20)
307580 +#define HIEDMAC_INT_ERR2_MASK (0x24)
307581 +#define HIEDMAC_INT_ERR3_MASK (0x28)
307583 +#define HIEDMAC_INT_TC1_RAW (0x600)
307584 +#define HIEDMAC_INT_TC2_RAW (0x608)
307585 +#define HIEDMAC_INT_ERR1_RAW (0x610)
307586 +#define HIEDMAC_INT_ERR2_RAW (0x618)
307587 +#define HIEDMAC_INT_ERR3_RAW (0x620)
307589 +#define HIEDMAC_Cx_CURR_CNT0(cn) (0x404 + cn * 0x20)
307590 +#define HIEDMAC_Cx_CURR_SRC_ADDR_L(cn) (0x408 + cn * 0x20)
307591 +#define HIEDMAC_Cx_CURR_SRC_ADDR_H(cn) (0x40c + cn * 0x20)
307592 +#define HIEDMAC_Cx_CURR_DEST_ADDR_L(cn) (0x410 + cn * 0x20)
307593 +#define HIEDMAC_Cx_CURR_DEST_ADDR_H(cn) (0x414 + cn * 0x20)
307595 +#define HIEDMAC_CH_PRI (0x688)
307596 +#define HIEDMAC_CH_STAT (0x690)
307597 +#define HIEDMAC_DMA_CTRL (0x698)
307599 +#define HIEDMAC_Cx_BASE(cn) (0x800 + cn * 0x40)
307600 +#define HIEDMAC_Cx_LLI_L(cn) (0x800 + cn * 0x40)
307601 +#define HIEDMAC_Cx_LLI_H(cn) (0x804 + cn * 0x40)
307602 +#define HIEDMAC_Cx_CNT0(cn) (0x81c + cn * 0x40)
307603 +#define HIEDMAC_Cx_SRC_ADDR_L(cn) (0x820 + cn * 0x40)
307604 +#define HIEDMAC_Cx_SRC_ADDR_H(cn) (0x824 + cn * 0x40)
307605 +#define HIEDMAC_Cx_DEST_ADDR_L(cn) (0x828 + cn * 0x40)
307606 +#define HIEDMAC_Cx_DEST_ADDR_H(cn) (0x82c + cn * 0x40)
307607 +#define HIEDMAC_Cx_CONFIG(cn) (0x830 + cn * 0x40)
307609 +#define HIEDMAC_CxCONFIG_M2M 0xCFF33000
307610 +#define HIEDMAC_CxCONFIG_M2M_LLI 0xCFF00000
307611 +#define HIEDMAC_CxCONFIG_CHN_START 0x1
307612 +#define HIEDMAC_Cx_DISABLE 0x0
307614 +#define HIEDMAC_ALL_CHAN_CLR (0xff)
307615 +#define HIEDMAC_INT_ENABLE_ALL_CHAN (0xff)
307623 +#define HIEDMAC_WIDTH_8BIT (0x0)
307624 +#define HIEDMAC_WIDTH_16BIT (0x1)
307625 +#define HIEDMAC_WIDTH_32BIT (0x10)
307626 +#define HIEDMAC_WIDTH_64BIT (0x11)
307633 +#define HIEDMAC_LLI_ALIGN 0x40
307634 +#define HIEDMAC_LLI_DISABLE 0x0
307635 +#define HIEDMAC_LLI_ENABLE 0x2
307637 +#define HIEDMAC_CXCONFIG_SIGNAL_SHIFT (0x4)
307638 +#define HIEDMAC_CXCONFIG_MEM_TYPE (0x0)
307639 +#define HIEDMAC_CXCONFIG_DEV_MEM_TYPE (0x1)
307640 +#define HIEDMAC_CXCONFIG_TSF_TYPE_SHIFT (0x2)
307641 +#define HIEDMAC_CxCONFIG_LLI_START (0x1)
307643 +#define HIEDMAC_CXCONFIG_ITC_EN (0x1)
307644 +#define HIEDMAC_CXCONFIG_ITC_EN_SHIFT (0x1)
307646 +#define CCFG_EN 0x1
307656 +#define DMAC_HOST0 0
307672 +#define PERI_8BIT_MODE 0
307677 +#define HIEDMAC_LLI_PAGE_NUM 0x4 /* 4*4K*65535B/64�?16MB */
307684 @@ -0,0 +1,4 @@
307691 index 000000000..0ba50a756
307694 @@ -0,0 +1 @@
307701 @@ -0,0 +1,16 @@
307723 @@ -0,0 +1,2 @@
307731 @@ -0,0 +1,199 @@
307759 + u64 total = 0;
307761 + for (i = 0; i < num_zones; i++) {
307774 + for (i = 0; i < num_zones; i++) {
307786 + return 0;
307797 + return 0;
307800 + tmpline[sizeof(tmpline) - 1] = '\0';
307807 + for (i = 0; (argv[i] = strsep(&line, ",")) != NULL;)
307813 + return 0;
307816 + strlcpy(hisi_zone[num_zones].name, argv[0], NAME_LEN_MAX);
307823 + strlcpy(hisi_zone[num_zones].name, argv[0], NAME_LEN_MAX);
307836 + if (num_zones != 0) {
307840 + return 0;
307849 + for (i = 0; i < num_zones; i++) {
307861 + u32 i = 0;
307865 + for (i = 0; i < num_zones; i++)
307866 + if (strcmp(hisi_zone[i].name, name) == 0) {
307880 + u32 i = 0;
307885 + for (i = 0; i < num_zones; i++)
307886 + if (strcmp(hisi_zone[i].name, name) == 0) {
307901 + int ret = 0;
307903 + if (use_bootargs == 0) {
307908 + for (i = 0; i < num_zones; i++) {
307910 + hisi_zone[i].nbytes, hisi_zone[i].phys_start, 0);
307927 + return 0;
307971 + because DMA for 0xFFC one-time largest data transfers;
307990 @@ -0,0 +1,1451 @@
308032 +#define HIBVT_I2C_GLB 0x0
308033 +#define HIBVT_I2C_SCL_H 0x4
308034 +#define HIBVT_I2C_SCL_L 0x8
308035 +#define HIBVT_I2C_DATA1 0x10
308036 +#define HIBVT_I2C_TXF 0x20
308037 +#define HIBVT_I2C_RXF 0x24
308038 +#define HIBVT_I2C_CMD_BASE 0x30
308039 +#define HIBVT_I2C_LOOP1 0xb0
308040 +#define HIBVT_I2C_DST1 0xb4
308041 +#define HIBVT_I2C_LOOP2 0xb8
308042 +#define HIBVT_I2C_DST2 0xbc
308043 +#define HIBVT_I2C_TX_WATER 0xc8
308044 +#define HIBVT_I2C_RX_WATER 0xcc
308045 +#define HIBVT_I2C_CTRL1 0xd0
308046 +#define HIBVT_I2C_CTRL2 0xd4
308047 +#define HIBVT_I2C_STAT 0xd8
308048 +#define HIBVT_I2C_INTR_RAW 0xe0
308049 +#define HIBVT_I2C_INTR_EN 0xe4
308050 +#define HIBVT_I2C_INTR_STAT 0xe8
308055 +#define GLB_EN_MASK BIT(0)
308061 + * I2C Timing CMD Register -- HIBVT_I2C_CMD_BASE + n * 4 (n = 0, 1, 2, ... 31)
308063 +#define CMD_EXIT 0x0
308064 +#define CMD_TX_S 0x1
308065 +#define CMD_TX_D1_2 0x4
308066 +#define CMD_TX_D1_1 0x5
308067 +#define CMD_TX_FIFO 0x9
308068 +#define CMD_RX_FIFO 0x12
308069 +#define CMD_RX_ACK 0x13
308070 +#define CMD_IGN_ACK 0x15
308071 +#define CMD_TX_ACK 0x16
308072 +#define CMD_TX_NACK 0x17
308073 +#define CMD_JMP1 0x18
308074 +#define CMD_JMP2 0x19
308075 +#define CMD_UP_TXF 0x1d
308076 +#define CMD_TX_RS 0x1e
308077 +#define CMD_TX_P 0x1f
308082 +#define CTRL1_CMD_START_MASK BIT(0)
308083 +#define CTRL1_DMA_OP_MASK (0x3 << 8)
308084 +#define CTRL1_DMA_R (0x3 << 8)
308085 +#define CTRL1_DMA_W (0x2 << 8)
308097 +#define INTR_ABORT_MASK (BIT(0) | BIT(11))
308105 +#define INTR_ALL_MASK GENMASK(31, 0)
308112 +#define I2C_WAIT_TIMEOUT 0x400
308142 +#define FORCE_SDA_OEN_SHIFT (0)
308151 + hibvt_i2c_cfg_irq(i2c, 0);
308154 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) |
308155 + (0x1 << FORCE_SDA_OEN_SHIFT);
308158 + time_cnt = 0;
308160 + for (index = 0; index < 9; index++) {
308161 + val = (0x1 << GPIO_MODE_SHIFT) | 0x1;
308166 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) |
308167 + (0x1 << FORCE_SDA_OEN_SHIFT);
308180 + } while (!(val & (0x1 << CHECK_SDA_IN_SHIFT)));
308182 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) |
308183 + (0x1 << FORCE_SDA_OEN_SHIFT);
308186 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT);
308191 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) |
308192 + (0x1 << FORCE_SDA_OEN_SHIFT);
308196 + val = (0x1 << FORCE_SCL_OEN_SHIFT) | 0x1;
308247 + dev_dbg(i2c->dev, "hii2c reg: offset=0x%x, cmd=0x%x...\n",
308263 + addr = ((msg->addr & 0x300) << 1) | 0xf000;
308268 + addr |= msg->addr & 0xff;
308270 + addr = (msg->addr & 0x7f) << 1;
308292 + unsigned int time_cnt = 0;
308298 + return 0;
308305 + dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
308312 + unsigned int time_cnt = 0;
308318 + return 0;
308325 + dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
308332 + unsigned int time_cnt = 0;
308338 + dev_err(i2c->dev, "wait idle abort!, RIS: 0x%x\n",
308344 + return 0;
308351 + dev_err(i2c->dev, "wait idle timeout, RIS: 0x%x, SR: 0x%x\n",
308398 + val |= ((0xa << GLB_SDA_HOLD_SHIFT) & GLB_SDA_HOLD_MASK);
308432 + int offset = 0;
308434 + if (i2c->msg_idx == 0)
308440 + if (i2c->msg_idx == 0) {
308491 + int offset = 0;
308494 + if (i2c->msg_idx == 0) {
308501 + if (i2c->msg_idx == 0) {
308528 + for(i = 0; i < reg_data_width - 1; i++){
308539 + if(((msg->len / reg_data_width) - 1) > 0){
308540 + writel(0, i2c->base + HIBVT_I2C_DST2);
308585 + int status = 0;
308590 + writel(0x1, i2c->base + HIBVT_I2C_TX_WATER);
308627 + int chan, val, status = 0;
308633 + writel(0x1, i2c->base + HIBVT_I2C_TX_WATER);
308660 + int status = 0;
308665 + writel(0x0, i2c->base + HIBVT_I2C_RX_WATER);
308712 + return 0;
308721 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308782 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308836 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308846 + i2c->msg_buf_ptr = 0;
308883 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308893 + i2c->msg_buf_ptr = 0;
308933 + dev_dbg(i2c->dev, "%s RIS: 0x%x\n", __func__, irq_status);
308941 + dev_err(i2c->dev, "irq handle abort, RIS: 0x%x\n",
308971 + i2c->status = 0;
308990 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308994 + i2c->msg_buf_ptr = 0;
309015 + if (timeout == 0) {
309040 + if (!msgs || (num <= 0)) {
309041 + dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
309049 + i2c->msg_idx = 0;
309058 + } else if (i2c->irq >= 0) {
309060 + if (i2c->irq >= 0) {
309076 + if (!status || i2c->msg_idx > 0)
309093 + if (!msgs || (num <= 0)) {
309094 + dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
309100 + i2c->msg_idx = 0;
309117 + if (!status || i2c->msg_idx > 0)
309129 + if (!msgs || (num <= 0)) {
309130 + dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
309136 + i2c->msg_idx = 0;
309154 + if (!status || i2c->msg_idx > 0) {
309194 + (count < 0)) {
309199 + if ((client->addr > 0x3ff) ||
309200 + (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) {
309226 + if ((client->addr > 0x3ff)
309227 + || (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) {
309236 + if ((!buf)||(count < 0)) {
309237 + printk(KERN_ERR "buf == NULL || count < 0, Invalid argument!\n");
309269 + if ((msgs[0].addr > 0x3ff) ||
309270 + (((msgs[0].flags & I2C_M_TEN) == 0) && (msgs[0].addr > 0x7f))) {
309271 + printk(KERN_ERR "msgs[0] dev address out of range\n");
309275 + if ((msgs[1].addr > 0x3ff) ||
309276 + (((msgs[1].flags & I2C_M_TEN) == 0) && (msgs[1].addr > 0x7f))) {
309318 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
309348 + i2c->irq = platform_get_irq(pdev, 0);
309374 + return 0;
309388 + return 0;
309400 + return 0;
309412 + return 0;
309476 + if(msg.len == 0 || reg_data_width > msg.len || msg.len % reg_data_width != 0){
309483 + return 0;
309508 + return 0;
309602 return 0;
309615 int ret = 0;
309718 + for (idx = 0; idx < DIS_IRQ_CNT; idx++) {
309721 + dis_irq_handle[idx].handle(((irqstat >> 10) & 0x7),
309727 + return 0;
309807 +#define GIC_DIST_INIT_FLAG 0x47444946
309808 +#define GIC_DIST_INIT_FLAG_OFFSET 0x0130
309809 + /* 0x47444946('G''D''I''F') is abbreviation of GIC_DIST_INIT_FLAG. */
309812 + sysctrl_reg_base = of_iomap(np, 0);
309834 @@ -0,0 +1,115 @@
309838 +#define TO_A53MP0 (1<<0x00)
309839 +#define TO_A53MP1 (1<<0x01)
309840 +#define TO_A73MP0 (1<<0x02)
309841 +#define TO_A73MP1 (1<<0x03)
309842 +#define TO_A53UP_ (1<<0x04) // Local
309844 + 0, 0, 0, 0,
309845 + 0, 0, 0, 0,
309846 + 0, 0, 0, 0,
309847 + 0, 0, 0, 0,
309848 + 0, 0, 0, 0,
309849 + 0, 0, 0, 0,
309850 + 0, 0, 0, 0,
309851 + 0, 0, 0, 0,
309852 + /* time 0 timer 2 timer 4 timer 6 */
309854 + /* time 8 timer 10 uart 0 uart 1 */
309858 + /* i2c 0 i2c 1 i2c 2 i2c 3 */
309894 + /* USB 0 USB 1 SLVS-EC res */
309896 + /* MIPI RX DDRT 0 DDRT 1 VDH_OLP */
309904 + /* RSA WDG CAN 0 CAN 1 */
309918 + /* A73MP_NCOMMIRQ1 PMU CTIIRQ0 COMMRX 0 */
309924 + /* AVSP 0 AVSP 1 AVSP 2 AVSP 3 */
309963 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
309975 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
310017 @@ -0,0 +1,134 @@
310112 + ret = mfd_add_devices(dev, 0, hisi_fmc_devs,
310113 + ARRAY_SIZE(hisi_fmc_devs), NULL, 0, NULL);
310119 + return 0;
310131 + return 0;
310186 index 56f7f3600..0ae99386d 100644
310205 host->ops->get_cd(host) == 0) {
310213 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
310310 ret = mmc_io_rw_direct(card, 0, 0,
310338 + err = mmc_send_io_op_cond(host, 0, &ocr);
310346 + err = mmc_sdio_init_card(host, rocr, card, 0);
310350 + return 0;
310487 cqhci_set_irqs(cq_host, 0);
310516 return 0;
310595 #define CQHCI_SSC1 0x40
310600 +#define SEND_QSR_INTERVAL 0x70001
310604 #define CQHCI_SSC2 0x44
310606 #define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32)
310607 #define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0)
310609 +#define SYNOPSYS_DMA_LIMIT 0x8000000
310616 #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
310617 +#define CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT 0x2
310639 @@ -0,0 +1,23 @@
310668 @@ -0,0 +1,2 @@
310676 @@ -0,0 +1,2582 @@
310782 +#define PWR_CTRL0_REG 0x12090000
310783 +#define GPIO_AT_PMC_ENABLE_BIT 0x80
310784 +#define REG_SLEEP_TIME_MS 0x30
310791 +unsigned int slot_index = 0;
310855 + reg_value &= ~(0x1 << port);
310857 + reg_value |= (0x1 << port);
310878 + * 0: card on
310889 + card_status = 0;
310896 + * 0: card read/write
310904 +static int tuning_reset_flag = 0;
310908 + int wait_retry_count = 0;
310910 + unsigned int reg_data = 0;
310919 + * start_cmd = 0 means MMC Host controller has loaded registers
310923 + if ((reg_data & START_CMD) == 0)
310924 + return 0;
310980 + cmd_reg.bits.cmd_index = 0;
310981 + cmd_reg.bits.data_transfer_expected = 0;
310983 + cmd_reg.bits.response_expect = 0;
310984 + cmd_reg.bits.send_auto_stop = 0;
310985 + cmd_reg.bits.wait_prvdata_complete = 0;
310986 + cmd_reg.bits.check_response_crc = 0;
310993 + if (himci_wait_cmd(host) != 0) {
310997 + return 0;
311024 + if (reg_value > 0xFF)
311025 + reg_value = 0xFF;
311036 + clk_cmd.bits.cmd_index = 0;
311037 + clk_cmd.bits.data_transfer_expected = 0;
311038 + clk_cmd.bits.response_expect = 0;
311040 + if (himci_wait_cmd(host) != 0)
311053 + unsigned int tmp_reg = 0;
311072 + himci_writel(0x4, host->base + MCI_CLKSRC);
311076 + tmp_reg = 0;
311087 + host->pending_events = 0;
311106 + tmp_reg = 0;
311110 + host->error_count = 0;
311111 + host->data_error_count = 0;
311118 + unsigned int detect_retry_count = 0;
311123 + for (i = 0; i < 5; i++) {
311127 + if ((status[0] == status[1])
311128 + && (status[0] == status[2])
311129 + && (status[0] == status[3])
311130 + && (status[0] == status[4]))
311139 + curr_status = status[0];
311151 + mmc_detect_change(host->mmc, 0);
311198 + unsigned int ret = 0;
311227 + himci_trace(2, "host->dma_paddr is 0x%08lx,host->dma_vaddr is 0x%08lx\n",
311233 + des_cnt = 0;
311235 + for (i = 0; i < host->dma_sg_num; i++) {
311238 + himci_trace(2, "sg[%d] sg_length is 0x%08X, " \
311239 + "sg_phyaddr is 0x%08X\n", \
311251 + if (sg_length >= 0x1000) {
311252 + des[des_cnt].idmac_des_buf_size = 0x1000;
311253 + sg_length -= 0x1000;
311254 + sg_phyaddr += 0x1000;
311258 + sg_length = 0;
311261 + himci_trace(2, "des[%d] vaddr is 0x%08X", i,
311263 + himci_trace(2, "des[%d].idmac_des_ctrl is 0x%08X",
311265 + himci_trace(2, "des[%d].idmac_des_buf_size is 0x%08X",
311267 + himci_trace(2, "des[%d].idmac_des_buf_addr 0x%08X",
311269 + himci_trace(2, "des[%d].idmac_des_next_addr is 0x%08X",
311276 + des[0].idmac_des_ctrl |= DMA_DES_FIRST_DES;
311278 + des[des_cnt - 1].idmac_des_next_addr = 0;
311295 + himci_trace(4, "arg_reg 0x%x, val 0x%x", MCI_CMDARG, cmd->arg);
311300 + cmd_regs.bits.transfer_mode = 0;
311305 + cmd_regs.bits.read_write = 0;
311307 + cmd_regs.bits.data_transfer_expected = 0;
311308 + cmd_regs.bits.transfer_mode = 0;
311309 + cmd_regs.bits.read_write = 0;
311312 + cmd_regs.bits.send_auto_stop = 0;
311321 + cmd_regs.bits.wait_prvdata_complete = 0;
311323 + cmd_regs.bits.stop_abort_cmd = 0;
311324 + cmd_regs.bits.wait_prvdata_complete = 0;
311326 + cmd_regs.bits.stop_abort_cmd = 0;
311332 + cmd_regs.bits.response_expect = 0;
311333 + cmd_regs.bits.response_length = 0;
311334 + cmd_regs.bits.check_response_crc = 0;
311339 + cmd_regs.bits.response_length = 0;
311350 + cmd_regs.bits.response_length = 0;
311351 + cmd_regs.bits.check_response_crc = 0;
311360 + himci_trace(3, "cmd->opcode = %d cmd->arg = 0x%X\n",
311368 + cmd_regs.bits.send_initialization = 0;
311373 + cmd_regs.bits.volt_switch = 0;
311378 + cmd_regs.bits.update_clk_reg_only = 0;
311382 + himci_trace(4, "cmd_reg 0x%x, val 0x%x\n", MCI_CMD, cmd_regs.cmd_arg);
311384 + if (himci_wait_cmd(host) != 0) {
311388 + return 0;
311421 + for (i = 0; i < 4; i++) {
311424 + MCI_RESP3 - i * 0x4);
311430 + MCI_RESP0 + i * 0x4);
311435 + himci_trace(3, "irq cmd status stat = 0x%x is timeout error!",
311439 + himci_trace(3, "irq cmd status stat = 0x%x is response error!",
311445 + if ((cmd->resp[0] & CMD_ERRORS) && !host->is_tuning) {
311448 + himci_trace(5, "The status of the card is abnormal, cmd->resp[0]: %x",
311449 + cmd->resp[0]);
311455 + if ((cmd->resp[0] & R1_READY_FOR_DATA) && (R1_CURRENT_STATE(cmd->resp[0]) ==
311459 + himci_trace(5, "The status of the card is abnormal, cmd->resp[0]: %x",
311460 + cmd->resp[0]);
311479 + himci_trace(3, "irq data status stat = 0x%x is timeout error!",
311484 + himci_trace(3, "irq data status stat = 0x%x is data error!",
311491 + data->bytes_xfered = 0;
311498 + unsigned int cmd_retry_count = 0;
311500 + unsigned int cmd_irq_reg = 0;
311520 + return 0;
311526 + return 0;
311532 + cmd_retry_count = 0;
311540 + unsigned int i = 0;
311541 + for (i = 0; i < 4; i++) {
311544 + i * 0x4);
311546 + pr_err("%d : 0x%x\n", i, cmd->resp[i]);
311563 + unsigned int cmd_retry_count = 0;
311565 + unsigned int cmd_irq_reg = 0;
311582 + return 0;
311588 + cmd_retry_count = 0;
311624 + if (((time <= 0)
311628 + himci_trace(5, "wait data request complete is timeout! 0x%08X",
311637 + return 0;
311643 + unsigned int card_retry_count = 0;
311645 + unsigned int card_status_reg = 0;
311656 + return 0;
311661 + card_retry_count = 0;
311682 + int byte_cnt = 0;
311683 + int fifo_count = 0;
311684 + int ret = 0;
311694 + host->irq_status = 0;
311737 + himci_writel(0, host->base + MCI_BYTCNT);
311738 + himci_writel(0, host->base + MCI_BLKSIZ);
311780 + unsigned int wait_retry_count = 0;
311788 + himci_trace(3, "data status = 0x%x is error!", stat);
311871 + himci_set_drv_cap(host, 0);
311872 + return 0;
311901 + return 0;
311914 + return 0;
311921 + * sequence by setting S18R to 0.
311942 + himci_error("voltage failed, retrying with S18R set to 0\n");
311946 + return 0;
311961 + struct mmc_command cmd = {0};
311966 + err = mmc_wait_for_cmd(host, &cmd, 0);
311991 + void __iomem *tmp_reg = 0;
311993 + if (host->devid == 0)
311994 + tmp_reg = crg_ctrl + 0x14c;
311996 + tmp_reg = crg_ctrl + 0x164;
311998 + tmp_reg = crg_ctrl + 0x158;
312004 + himci_writel(0x80001, tmp_reg);
312014 + void __iomem *tmp_reg = 0;
312016 + if (host->devid == 0)
312017 + tmp_reg = crg_ctrl + 0x14c;
312019 + tmp_reg = crg_ctrl + 0x164;
312021 + tmp_reg = crg_ctrl + 0x158;
312038 + struct mmc_command cmd = {0};
312053 + return 0;
312058 + int err = 0;
312072 + tuning_reset_flag = 0;
312074 + if (cmd_count == 0) {
312089 + u32 regval = 0;
312090 + void __iomem *reg_sap_dll_status = 0;
312092 + if (host->devid == 0)
312093 + reg_sap_dll_status = crg_ctrl + 0x150;
312095 + reg_sap_dll_status = crg_ctrl + 0x168;
312097 + reg_sap_dll_status = crg_ctrl + 0x15c;
312100 + return 0;
312104 + return (regval & 0xff);
312110 + void __iomem *reg_sap_dll_ctrl = 0;
312112 + if (host->devid == 0)
312113 + reg_sap_dll_ctrl = crg_ctrl + 0x14c;
312115 + reg_sap_dll_ctrl = crg_ctrl + 0x164;
312117 + reg_sap_dll_ctrl = crg_ctrl + 0x158;
312123 + regval &= ~(0xFF << 8);
312154 + u32 found = 0;
312157 + u32 startp_init = 0;
312158 + u32 endp_init = 0;
312159 + u32 phaseoffset = 0;
312160 + u32 totalphases = 0;
312162 + u8 mdly_tap_flag = 0;
312163 + int prev_err = 0, err = 0;
312205 + err = 0;
312232 + err = 0;
312237 + phaseoffset = 0;
312238 + for (index = 0; index < edge_f2p; index++) {
312259 + err = 0;
312271 + if (totalphases == 0) {
312288 + return 0;
312305 + host->pending_events = 0;
312321 + u32 found = 0, prefound = 0;
312323 + u32 edge_num = 0;
312328 + edge_p2f = 0;
312333 + for (index = 0; index < HIMCI_PHASE_SCALE; index++) {
312356 + if ((edge_p2f != 0) && (edge_f2p != phase_num))
312360 + found = 0;
312363 + if ((edge_p2f == 0) && (edge_f2p == phase_num)) {
312382 +#if 0
312387 + unsigned int found = 0;
312388 + unsigned int prev_found = 0;
312389 + unsigned int prev_point = 0;
312391 + unsigned int phase = 0;
312397 + for (index = 0; index < HIMCI_PHASE_SCALE; index++) {
312407 + himci_trace(3, "try phase:%02d, found:0x%x\n", index, found);
312412 + if (index != 0)
312420 + found = 0;
312427 + return 0;
312455 + return 0;
312462 + * 1.Set a phase shift of 0° on cclk_in_sample
312494 + host->is_tuning = 0;
312502 + unsigned int err = 0;
312503 + unsigned int found = 0; /* identify if we have found a valid phase */
312516 + himci_writel(0x1, host->base + MCI_CARDTHRCTL);
312518 + himci_trace(3, "start sd3.0 phase tuning...");
312524 + count = 0;
312553 + err = 0;
312557 + host->is_tuning = 0;
312573 + phase = (phase < 0) ? (HIMCI_PHASE_SCALE + phase) : phase;
312585 + return 0;
312613 + int ret = 0;
312671 + himci_set_drv_cap(host, 0);
312701 + return 0;
312759 + memset(c_info, 0, sizeof(struct card_info));
312776 + return 0;
312795 + u32 state = 0;
312796 + int handle = 0;
312797 + u32 mstate = 0;
312859 + if (host->devid == 0 || host->devid == 1)
312861 + return 0;
312871 + pwr_ctrl = ioremap(PWR_CTRL0_REG, 0x4);
312889 + int ret = 0, irq;
312919 + crg_ctrl = ioremap(0x12010000, 0x1000);
312926 + misc_ctrl_1 = ioremap(0x12030004, 0x4);
312934 + regval &= ~(0x1 << 2);
312939 + host_ioaddr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
312977 + host->port = 0;
312979 + host->port = 0;
313024 + timer_setup(&host->timer, himci_detect_card, 0);
313029 + irq = platform_get_irq(pdev, 0);
313030 + if (irq < 0) {
313036 + ret = request_irq(irq, hisd_irq, 0, DRIVER_NAME, host);
313043 + return 0;
313088 + return 0;
313101 + himci_writel(0, host->base + MCI_IDINTEN);
313102 + himci_writel(0, host->base + MCI_INTMASK);
313116 + int ret = 0;
313133 + int ret = 0;
313180 + if (slot >= HIMCI_SLOT_NUM || slot < 0) {
313264 @@ -0,0 +1,156 @@
313273 + 0 - all message
313283 +#define POWER_OFF 0
313285 +#define FORCE_DISABLE 0
313288 +#define CARD_PLUGED 0
313291 +#define DISABLE 0
313310 +} while (0)
313319 +} while (0)
313325 +} while (0)
313328 + himci_trace(1, "readl(0x%04X) = 0x%08X", (unsigned int)(uintptr_t)addr, reg); \
313332 + himci_trace(1, "writel(0x%04X) = 0x%08X", (unsigned int)(uintptr_t)addr, \
313334 +} while (0)
313348 +#define CARD_DISCONNECT 0
313373 +#define HIMCI_PEND_DTO_B (0)
313426 @@ -0,0 +1,94 @@
313446 +#define TUNING_START_PHASE 0
313449 +#define DRV_PHASE_DFLT (0x2<<23)
313450 +#define SMPL_PHASE_DFLT (0x3<<16)
313452 +#define REG_PAD_CTRL 0x200f0800
313454 +#define REG_CTRL_SDIO0_CLK 0xcc
313455 +#define REG_CTRL_SDIO0_CMD 0xdc
313456 +#define REG_CTRL_SDIO0_DATA0 0xe0
313457 +#define REG_CTRL_SDIO0_DATA1 0xe4
313458 +#define REG_CTRL_SDIO0_DATA2 0xe8
313459 +#define REG_CTRL_SDIO0_DATA3 0xec
313461 +#define REG_CTRL_SDIO1_CLK 0x104
313462 +#define REG_CTRL_SDIO1_CMD 0x114
313463 +#define REG_CTRL_SDIO1_DATA0 0x118
313464 +#define REG_CTRL_SDIO1_DATA1 0x11c
313465 +#define REG_CTRL_SDIO1_DATA2 0x120
313466 +#define REG_CTRL_SDIO1_DATA3 0x124
313468 +#define SDIO_CLK_DS_3V3 0x60
313469 +#define SDIO_CMD_DS_3V3 0xe0
313470 +#define SDIO_DATA0_DS_3V3 0xe0
313471 +#define SDIO_DATA1_DS_3V3 0xe0
313472 +#define SDIO_DATA2_DS_3V3 0xe0
313473 +#define SDIO_DATA3_DS_3V3 0xe0
313475 +#define SDIO_CLK_DS_1V8 0x40
313476 +#define SDIO_CMD_DS_1V8 0xd0
313477 +#define SDIO_DATA0_DS_1V8 0xd0
313478 +#define SDIO_DATA1_DS_1V8 0xd0
313479 +#define SDIO_DATA2_DS_1V8 0xd0
313480 +#define SDIO_DATA3_DS_1V8 0xd0
313512 + for (i = 0; i < 6; i++) {
313526 @@ -0,0 +1,162 @@
313546 +#define TUNING_START_PHASE 0
313549 +#define DRV_PHASE_DFLT (0x4<<23)
313550 +#define SMPL_PHASE_DFLT (0x0<<16)
313553 +#define REG_CTRL_EMMC_START (0x10ff0000 + 0x0)
313555 +#define REG_CTRL_SDIO0_START (0x10ff0000 + 0x24)
313557 +#define REG_CTRL_SDIO1_START (0x112f0000 + 0x8)
313562 +static unsigned int emmc_hs200_drv[] = {0x2b0, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313563 +static unsigned int emmc_hs_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313564 +static unsigned int emmc_ds_drv[] = {0x6b0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
313565 +static unsigned int emmc_ds_400k_drv[] = {0x6c0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
313567 +static unsigned int sdio0_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313568 +static unsigned int sdio0_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313569 +static unsigned int sdio0_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
313570 +static unsigned int sdio0_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313571 +static unsigned int sdio0_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
313572 +static unsigned int sdio0_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313574 +static unsigned int sdio1_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313575 +static unsigned int sdio1_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313576 +static unsigned int sdio1_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
313577 +static unsigned int sdio1_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313578 +static unsigned int sdio1_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
313579 +static unsigned int sdio1_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313591 + if (devid == 0) {
313631 + (size_t)0x1000);
313633 + for (i = start, j = 0; j < 6; i = i + 4, j++) {
313641 + reg = reg & (~(0x7f0));
313648 +#define DRV_PHASE_180 (0x4<<23)
313649 +#define DRV_PHASE_135 (0x3<<23)
313650 +#define DRV_PHASE_90 (0x2<<23)
313652 +#define SMP_PHASE_45 (0x1<<16)
313653 +#define SMP_PHASE_0 (0x0<<16)
313662 + if (devid == 0) {
313694 @@ -0,0 +1,160 @@
313714 +#define TUNING_START_PHASE 0
313717 +#define DRV_PHASE_DFLT (0x4<<23)
313718 +#define SMPL_PHASE_DFLT (0x0<<16)
313721 +#define REG_CTRL_EMMC_START (0x10ff0000 + 0x0)
313723 +#define REG_CTRL_SDIO0_START (0x10ff0000 + 0x24)
313725 +#define REG_CTRL_SDIO1_START (0x112f0000 + 0x8)
313730 +static unsigned int emmc_hs200_drv[] = {0x2b0, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313731 +static unsigned int emmc_hs_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313732 +static unsigned int emmc_ds_drv[] = {0x6b0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
313733 +static unsigned int emmc_ds_400k_drv[] = {0x6c0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
313735 +static unsigned int sdio0_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313736 +static unsigned int sdio0_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313737 +static unsigned int sdio0_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
313738 +static unsigned int sdio0_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313739 +static unsigned int sdio0_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
313740 +static unsigned int sdio0_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313742 +static unsigned int sdio1_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313743 +static unsigned int sdio1_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
313744 +static unsigned int sdio1_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
313745 +static unsigned int sdio1_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313746 +static unsigned int sdio1_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
313747 +static unsigned int sdio1_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
313758 + if (devid == 0) {
313798 + (size_t)0x1000);
313799 + for (i = start, j = 0; j < 6; i = i + 4, j++) {
313807 + reg = reg & (~(0x7f0));
313814 +#define DRV_PHASE_180 (0x4<<23)
313815 +#define DRV_PHASE_135 (0x3<<23)
313816 +#define DRV_PHASE_90 (0x2<<23)
313818 +#define SMP_PHASE_45 (0x1<<16)
313819 +#define SMP_PHASE_0 (0x0<<16)
313828 + if (devid == 0) {
313860 @@ -0,0 +1,152 @@
313880 +#define TUNING_START_PHASE 0
313883 +#define DRV_PHASE_DFLT (0x2<<23)
313884 +#define SMPL_PHASE_DFLT (0x2<<16)
313886 +#define REG_PAD_CTRL 0x200f0800
313889 +#define REG_CTRL_SDIO0_CLK 0xb4
313890 +#define REG_CTRL_SDIO0_CMD 0xb8
313891 +#define REG_CTRL_SDIO0_DATA0 0xbc
313892 +#define REG_CTRL_SDIO0_DATA1 0xc0
313893 +#define REG_CTRL_SDIO0_DATA2 0xc4
313894 +#define REG_CTRL_SDIO0_DATA3 0xc8
313897 +#define REG_CTRL_EMMC_CLK 0xcc
313898 +#define REG_CTRL_EMMC_CMD 0xd8
313899 +#define REG_CTRL_EMMC_DATA0 0xdc
313900 +#define REG_CTRL_EMMC_DATA1 0xf8
313901 +#define REG_CTRL_EMMC_DATA2 0xfc
313902 +#define REG_CTRL_EMMC_DATA3 0xd4
313903 +#define REG_CTRL_EMMC_DATA4 0xd0
313904 +#define REG_CTRL_EMMC_DATA5 0xec
313905 +#define REG_CTRL_EMMC_DATA6 0xe8
313906 +#define REG_CTRL_EMMC_DATA7 0xf0
313909 +#define REG_CTRL_SDIO1_CLK 0x10
313910 +#define REG_CTRL_SDIO1_CMD 0x28
313911 +#define REG_CTRL_SDIO1_DATA0 0x20
313912 +#define REG_CTRL_SDIO1_DATA1 0x1c
313913 +#define REG_CTRL_SDIO1_DATA2 0x34
313914 +#define REG_CTRL_SDIO1_DATA3 0x24
313917 +#define SDIO_CLK_DS_3V3 0xe0
313918 +#define SDIO_CMD_DS_3V3 0xe0
313919 +#define SDIO_DATA0_DS_3V3 0xe0
313920 +#define SDIO_DATA1_DS_3V3 0xe0
313921 +#define SDIO_DATA2_DS_3V3 0xe0
313922 +#define SDIO_DATA3_DS_3V3 0xe0
313925 +#define SDIO_CLK_DS_1V8 0xb0
313926 +#define SDIO_CMD_DS_1V8 0xd0
313927 +#define SDIO_DATA0_DS_1V8 0xd0
313928 +#define SDIO_DATA1_DS_1V8 0xd0
313929 +#define SDIO_DATA2_DS_1V8 0xd0
313930 +#define SDIO_DATA3_DS_1V8 0xd0
313933 +#define EMMC_CLK_DS 0x40
313934 +#define EMMC_CMD_DS 0x20
313935 +#define EMMC_DATA0_DS 0x20
313936 +#define EMMC_DATA1_DS 0x20
313937 +#define EMMC_DATA2_DS 0x20
313938 +#define EMMC_DATA3_DS 0x20
313939 +#define EMMC_DATA4_DS 0x20
313940 +#define EMMC_DATA5_DS 0x20
313941 +#define EMMC_DATA6_DS 0x20
313942 +#define EMMC_DATA7_DS 0x20
313997 + for (i = 0; i < 10; i++)
314003 + for (i = 0; i < 6; i++) {
314018 @@ -0,0 +1,162 @@
314038 +#define TUNING_START_PHASE 0
314041 +#define DRV_PHASE_DFLT (0x4<<23)
314042 +#define SMPL_PHASE_DFLT (0x0<<16)
314045 +#define REG_CTRL_EMMC_START (0x10ff0000 + 0x0)
314047 +#define REG_CTRL_SDIO0_START (0x10ff0000 + 0x24)
314049 +#define REG_CTRL_SDIO1_START (0x112f0000 + 0x8)
314054 +static unsigned int emmc_hs200_drv[] = {0x2b0, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314055 +static unsigned int emmc_hs_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314056 +static unsigned int emmc_ds_drv[] = {0x6b0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
314057 +static unsigned int emmc_ds_400k_drv[] = {0x6c0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
314059 +static unsigned int sdio0_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314060 +static unsigned int sdio0_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314061 +static unsigned int sdio0_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
314062 +static unsigned int sdio0_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314063 +static unsigned int sdio0_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
314064 +static unsigned int sdio0_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314066 +static unsigned int sdio1_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314067 +static unsigned int sdio1_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314068 +static unsigned int sdio1_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
314069 +static unsigned int sdio1_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314070 +static unsigned int sdio1_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
314071 +static unsigned int sdio1_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314082 + if (devid == 0) {
314122 + (size_t)0x1000);
314124 + for (i = start, j = 0; j < 6; i = i + 4, j++) {
314132 + reg = reg & (~(0x7f0));
314139 +#define DRV_PHASE_180 (0x4<<23)
314140 +#define DRV_PHASE_135 (0x3<<23)
314141 +#define DRV_PHASE_90 (0x2<<23)
314143 +#define SMP_PHASE_45 (0x1<<16)
314144 +#define SMP_PHASE_0 (0x0<<16)
314154 + if (devid == 0) {
314186 @@ -0,0 +1,164 @@
314206 +#define TUNING_START_PHASE 0
314209 +#define DRV_PHASE_DFLT (0x4<<23)
314210 +#define SMPL_PHASE_DFLT (0x0<<16)
314213 +#define REG_CTRL_EMMC_START (0x10ff0000 + 0x0)
314215 +#define REG_CTRL_SDIO0_START (0x10ff0000 + 0x24)
314217 +#define REG_CTRL_SDIO1_START (0x112f0000 + 0x8)
314222 +static unsigned int emmc_hs200_drv[] = {0x2b0, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314223 +static unsigned int emmc_hs_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314224 +static unsigned int emmc_ds_drv[] = {0x6b0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
314225 +static unsigned int emmc_ds_400k_drv[] = {0x6c0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
314227 +static unsigned int sdio0_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314228 +static unsigned int sdio0_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314229 +static unsigned int sdio0_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
314230 +static unsigned int sdio0_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314231 +static unsigned int sdio0_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
314232 +static unsigned int sdio0_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314234 +static unsigned int sdio1_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314235 +static unsigned int sdio1_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
314236 +static unsigned int sdio1_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
314237 +static unsigned int sdio1_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314238 +static unsigned int sdio1_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
314239 +static unsigned int sdio1_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
314251 + if (devid == 0) {
314291 + (size_t)0x1000);
314293 + for (i = start, j = 0; j < 6; i = i + 4, j++) {
314301 + reg = reg & (~(0x7f0));
314308 +#define DRV_PHASE_180 (0x4<<23)
314309 +#define DRV_PHASE_135 (0x3<<23)
314310 +#define DRV_PHASE_90 (0x2<<23)
314312 +#define SMP_PHASE_45 (0x1<<16)
314313 +#define SMP_PHASE_0 (0x0<<16)
314323 + if (devid == 0) {
314356 @@ -0,0 +1,246 @@
314394 + const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
314433 + unsigned int scale = 0;
314438 + if (0 < tmp) {
314464 + unsigned int clock_value = 0;
314479 + for (index_mci = 0; index_mci < HIMCI_SLOT_NUM; index_mci++) {
314531 + (0x00 == speed_class) ? "0" :
314532 + (0x01 == speed_class) ? "2" :
314533 + (0x02 == speed_class) ? "4" :
314534 + (0x03 == speed_class) ? "6" :
314535 + (0x04 == speed_class) ? "10" :
314538 + (0x00 == grade_speed_uhs) ?
314539 + "Less than 10MB/sec(0h)" :
314540 + (0x01 == grade_speed_uhs) ?
314571 + return 0;
314583 + proc_stats_entry = proc_create_single_data(MCI_STATS_PROC, 0,
314590 + return 0;
314601 + return 0;
314608 @@ -0,0 +1,36 @@
314650 @@ -0,0 +1,241 @@
314671 +#define HI_MCI_IO_SIZE 0x1000
314673 +#define MCI_CTRL 0x00
314674 +#define MCI_PWREN 0x04
314675 +#define MCI_CLKDIV 0x08
314676 +#define MCI_CLKSRC 0x0C
314677 +#define MCI_CLKENA 0x10
314678 +#define MCI_TIMEOUT 0x14
314679 +#define MCI_CTYPE 0x18
314680 +#define MCI_BLKSIZ 0x1c
314681 +#define MCI_BYTCNT 0x20
314682 +#define MCI_INTMASK 0x24
314683 +#define MCI_CMDARG 0x28
314684 +#define MCI_CMD 0x2C
314685 +#define MCI_RESP0 0x30
314686 +#define MCI_RESP1 0x34
314687 +#define MCI_RESP2 0x38
314688 +#define MCI_RESP3 0x3C
314689 +#define MCI_MINTSTS 0x40
314690 +#define MCI_RINTSTS 0x44
314691 +#define MCI_STATUS 0x48
314692 +#define MCI_FIFOTH 0x4C
314693 +#define MCI_CDETECT 0x50
314694 +#define MCI_WRTPRT 0x54
314695 +#define MCI_GPIO 0x58
314696 +#define MCI_TCBCNT 0x5C
314697 +#define MCI_TBBCNT 0x60
314698 +#define MCI_DEBNCE 0x64
314699 +#define MCI_USRID 0x68
314700 +#define MCI_VERID 0x6C
314701 +#define MCI_HCON 0x70
314702 +#define MCI_UHS_REG 0x74
314703 +#define MCI_RESET_N 0x78
314704 +#define MCI_BMOD 0x80
314705 +#define MCI_DBADDR 0x88
314706 +#define MCI_IDSTS 0x8C
314707 +#define MCI_IDINTEN 0x90
314708 +#define MCI_DSCADDR 0x94
314709 +#define MCI_BUFADDR 0x98
314710 +#define MCI_CARDTHRCTL 0x100
314711 +#define MCI_UHS_REG_EXT 0x108
314713 +#define MCI_TUNING_CTRL 0x118
314715 +/* MCI_IDSTS(0x8c) detals */
314716 +#define CMD_LOCK_ERR (0x1 << 29)
314717 +#define OWNBIT_ERR (0x1 << 28)
314718 +#define QUEUE_OVERFLOW (0x1 << 27)
314719 +#define RESP_CHECK_ERR (0x1 << 26)
314720 +#define PACKET_INT (0x1 << 25)
314721 +#define PACKET_TO_INT (0x1 << 24)
314722 +#define AUTO_STOP_ERR (0x1 << 23)
314723 +#define QUEUE_FULL (0x1 << 22)
314724 +#define QUEUE_EMPTY (0x1 << 21)
314727 +#define CES (0x1 << 5)
314728 +#define DU (0x1 << 4)
314729 +#define FBE (0x1 << 2)
314731 +/* MCI_BMOD(0x80) details */
314732 +#define BMOD_SWR (0x1 << 0)
314733 +#define BURST_INCR (0x1 << 1)
314734 +#define BMOD_DMA_EN (0x1 << 7)
314735 +#define BURST_8 (0x2 << 8)
314736 +#define BURST_16 (0x3 << 8)
314738 +#define DMA_BUFFER (0x2000)
314747 +/* MCI_CTRL(0x00) details */
314748 +#define CTRL_RESET (1 << 0)
314754 +/* MCI_CLKENA(0x10) details */
314755 +#define CCLK_ENABLE (0x1 << 0)
314756 +#define CCLK_LOW_POWER (0x1 << 16)
314758 +/* MCI_TIMEOUT(0x14) details: */
314760 +#define DATA_TIMEOUT (0xffffff << 8)
314761 +/* bit 7-0: response timeout param */
314762 +#define RESPONSE_TIMEOUT 0xff
314764 +/* MCI_CTYPE(0x18) details */
314765 +#define CARD_WIDTH_0 (0x1 << 16)
314766 +#define CARD_WIDTH_1 (0x1 << 0)
314768 +/* MCI_INTMASK(0x24) details:
314771 +#define ALL_INT_MASK 0x1ffff
314772 +#define DTO_INT_MASK (0x1 << 3)
314773 +#define SDIO_INT_MASK (0x1 << 16)
314775 +/* MCI_UHS_REG_EXT(0x108) details */
314778 +#define CLK_SMPL_PHS_MASK (0x7 << 16)
314782 +#define CLK_DRV_PHS_MASK (0x7 << 23)
314783 +#define DEFAULT_PHASE 0x1050000
314785 +/* MCI_CMD(0x2c) details:
314788 +#define START_CMD (0x1<<31)
314790 +/* MCI_INTSTS(0x44) details */
314793 +#define SDIO_INT_STATUS (0x1 << 16)
314796 +#define EBE_INT_STATUS (0x1 << 15)
314799 +#define ACD_INT_STATUS (0x1 << 14)
314802 +#define SBE_INT_STATUS (0x1 << 13)
314805 +#define HLE_INT_STATUS (0x1 << 12)
314808 +#define FRUN_INT_STATUS (0x1 << 11)
314811 +#define HTO_INT_STATUS (0x1 << 10)
314814 +#define VOLT_SWITCH_INT_STATUS (0x1 << 10)
314817 +#define DRTO_INT_STATUS (0x1 << 9)
314820 +#define RTO_INT_STATUS (0x1 << 8)
314823 +#define DCRC_INT_STATUS (0x1 << 7)
314826 +#define RCRC_INT_STATUS (0x1<<6)
314829 +#define RXDR_INT_STATUS (0x1<<5)
314832 +#define TXDR_INT_STATUS (0x1<<4)
314835 +#define DTO_INT_STATUS (0x1<<3)
314838 +#define CD_INT_STATUS (0x1<<2)
314841 +#define RE_INT_STATUS (0x1<<1)
314848 +/* MCI_RINTSTS(0x44) details:bit 16-1: clear
314852 +#define ALL_INT_CLR 0x1efff
314853 +#define ALL_SD_INT_CLR 0xefff
314855 +/* MCI_STATUS(0x48) details */
314856 +#define DATA_BUSY (0x1<<9)
314858 +/* MCI_FIFOTH(0x4c) details */
314859 +#define BURST_SIZE (0x6<<28)
314860 +#define RX_WMARK (0x7f<<16)
314861 +#define TX_WMARK (0x80)
314863 +/* MCI_CDETECT(0x50) details */
314864 +#define HIMCI_CARD0 (0x1<<0)
314866 +/* MCI_GPIO(0x58) details */
314867 +#define DTO_FIX_BYPASS (0x1<<23)
314868 +#define CMD_OUT_EN_FIX_BYPASS (0x1<<8)
314870 +/* MCI_UHS_REG(0x74) details */
314871 +#define HI_SDXC_CTRL_VDD_180 (0x1<<0)
314872 +#define HI_SDXC_CTRL_DDR_REG (0x1<<16)
314874 +/* MCI_RESET_N(0x78) details */
314875 +#define MMC_RST_N (0x1<<0)
314877 +/* MCI_CARDTHRCTL(0x100) details */
314881 +#define RW_THRESHOLD_SIZE (0x2000005)
314883 +#define RW_THRESHOLD_SIZE (0x2000001)
314886 +/* MCI_TUNING_CTRL(0x118) details */
314887 +#define HW_TUNING_EN (0x1 << 0)
314888 +#define EDGE_CTRL (0x1 << 1)
314889 +#define FOUND_EDGE (0x1 << 5)
314897 @@ -0,0 +1,301 @@
314952 + const u32 mask = ((size < BIT_WIDTH) ? 1 << size : 0) - 1;
314953 + const int off = 0x3 - ((start) / BIT_WIDTH);
314976 + unsigned int scale = 0;
314981 + if (tmp > 0) {
315007 + unsigned int clock_value = 0;
315023 + for (index_mci = 0; index_mci < MCI_SLOT_NUM; index_mci++) {
315075 + (speed_class == 0x00) ? "0" :
315076 + (speed_class == 0x01) ? "2" :
315077 + (speed_class == 0x02) ? "4" :
315078 + (speed_class == 0x03) ? "6" :
315079 + (speed_class == 0x04) ? "10" :
315082 + (grade_speed_uhs == 0x00) ?
315083 + "Less than 10MB/sec(0h)" :
315084 + (grade_speed_uhs == 0x01) ?
315119 + if (*pos == 0)
315137 + return 0;
315179 + 0, proc_mci_dir, &mci_stats_proc_ops);
315186 + return 0;
315197 + return 0;
315204 @@ -0,0 +1,50 @@
315260 @@ -0,0 +1,674 @@
315285 +#define REG_EMMC_DRV_DLL_CTRL 0x1fc
315286 +#define REG_SDIO0_DRV_DLL_CTRL 0x1fc
315287 +#define REG_SDIO1_DRV_DLL_CTRL 0x220
315289 +#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
315292 +#define REG_EMMC_DRV_DLL_STATUS 0x210
315293 +#define REG_SDIO0_DRV_DLL_STATUS 0x210
315294 +#define REG_SDIO1_DRV_DLL_STATUS 0x228
315299 +#define REG_EMMC_SAMPL_DLL_STATUS 0x208
315300 +#define REG_SDIO0_SAMPL_DLL_STATUS 0x208
315301 +#define REG_SDIO1_SAMPL_DLL_STATUS 0x224
315303 +#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
315305 +#define REG_EMMC_SAMPL_DLL_CTRL 0x1f4
315306 +#define REG_SDIO0_SAMPL_DLL_CTRL 0x1f4
315307 +#define REG_SDIO1_SAMPL_DLL_CTRL 0x22c
315311 +#define REG_EMMC_SAMPLB_DLL_CTRL 0x1f8
315312 +#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1f8
315313 +#define REG_SDIO1_SAMPLB_DLL_CTRL 0x21c
315315 +#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
315316 +#define sdio_samplb_sel(phase) ((phase) << 0)
315318 +#define REG_EMMC_DS_DLL_CTRL 0x200
315320 +#define EMMC_DS_DLL_SSEL_MASK 0x7f
315322 +#define REG_EMMC_DS180_DLL_CTRL 0x204
315324 +#define REG_EMMC_DS180_DLL_STATUS 0x218
315325 +#define EMMC_DS180_DLL_READY BIT(0)
315327 +#define REG_EMMC_DS_DLL_STATUS 0x214
315328 +#define EMMC_DS_DLL_READY BIT(0)
315330 +#define REG_EMMC_CLK_CTRL 0x1f4
315331 +#define REG_SDIO0_CLK_CTRL 0x1f4
315332 +#define REG_SDIO1_CLK_CTRL 0x22c
315340 +#define IO_CFG_DRV_STR_MASK (0xf << 4)
315342 +#define IO_CFG_PIN_MUX_MASK (0xf << 0)
315343 +#define io_cfg_pin_mux_sel(type) ((type) << 0)
315344 +#define IO_CFG_PIN_MUX_TYPE_CLK_EMMC 0x0
315345 +#define IO_CFG_PIN_MUX_TYPE_CLK_SD 0x1
315348 +#define REG_CTRL_EMMC_CLK 0x0014
315349 +#define REG_CTRL_EMMC_CMD 0x0018
315350 +#define REG_CTRL_EMMC_DATA0 0x001c
315351 +#define REG_CTRL_EMMC_DATA1 0x0028
315352 +#define REG_CTRL_EMMC_DATA2 0x0024
315353 +#define REG_CTRL_EMMC_DATA3 0x0020
315354 +#define REG_CTRL_EMMC_DATA4 0x0030
315355 +#define REG_CTRL_EMMC_DATA5 0x0034
315356 +#define REG_CTRL_EMMC_DATA6 0x0038
315357 +#define REG_CTRL_EMMC_DATA7 0x003c
315358 +#define REG_CTRL_EMMC_DS 0x0058
315359 +#define REG_CTRL_EMMC_RST 0x005c
315368 +#define REG_CTRL_SDIO0_CLK 0x0040
315369 +#define REG_CTRL_SDIO0_CMD 0x0044
315370 +#define REG_CTRL_SDIO0_DATA0 0x0048
315371 +#define REG_CTRL_SDIO0_DATA1 0x004C
315372 +#define REG_CTRL_SDIO0_DATA2 0x0050
315373 +#define REG_CTRL_SDIO0_DATA3 0x0054
315380 +#define REG_CTRL_SDIO1_CLK 0x0060
315381 +#define REG_CTRL_SDIO1_CMD 0x0064
315382 +#define REG_CTRL_SDIO1_DATA0 0x0068
315383 +#define REG_CTRL_SDIO1_DATA1 0x006C
315384 +#define REG_CTRL_SDIO1_DATA2 0x0070
315385 +#define REG_CTRL_SDIO1_DATA3 0x0074
315527 + return 0;
315549 + reg = 0;
315556 + } while (timeout > 0);
315600 + reg = 0;
315607 + } while (timeout > 0);
315631 + reg = 0;
315638 + } while (timeout > 0);
315650 + reg = 0;
315658 + } while (timeout > 0);
315675 + mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) |
315676 + SDHCI_GM_RD_OSRC_LMT_SEL(0x7));
315684 + host->error_count = 0;
315691 + unsigned int reg = 0;
315697 + reg |= (pull_up ? IO_CFG_PULL_UP : 0);
315698 + reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
315699 + reg |= (sr ? IO_CFG_SR : 0);
315724 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0,
315725 + 0x3); /* set drv level 3 */
315726 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0,
315727 + 0x4); /* set drv level 4 */
315728 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
315730 + io_emmc_data_reg[i], 1, 0, 0, 0x4); /* set drv level 4 */
315731 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1,
315732 + 0x3); /* set drv level 3 */
315733 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
315734 + 0x3); /* set drv level 3 */
315738 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0,
315739 + 0x2); /* set drv level 2 */
315740 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
315741 + 0x4); /* set drv level 4 */
315742 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
315744 + io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
315745 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
315746 + 0x3); /* set drv level 3 */
315750 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1,
315751 + 0x4); /* set drv level 4 */
315752 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
315753 + 0x6); /* set drv level 6 */
315754 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
315756 + io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
315757 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
315758 + 0x3); /* set drv level 3 */
315762 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1,
315763 + 0x5); /* set drv level 5 */
315764 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
315765 + 0x6); /* set drv level 6 */
315766 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
315768 + io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
315769 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
315770 + 0x3); /* set drv level 3 */
315783 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1,
315784 + 0x5); /* set drv level 5 */
315785 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1,
315786 + 0x7); /* set drv level 7 */
315787 + for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
315789 + io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
315793 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1,
315794 + 0x7); /* set drv level 7 */
315795 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1,
315796 + 0x7); /* set drv level 7 */
315797 + for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
315799 + io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
315810 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1,
315811 + 0x5); /* set drv level 5 */
315812 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0,
315813 + 0x7); /* set drv level 7 */
315814 + for (i = 0; i < IO_CFG_SDIO1_DATA_LINE_COUNT; i++)
315816 + io_sdio1_data_reg[i], 1, 0, 0, 0x7); /* set drv level 7 */
315824 + unsigned int reg = 0;
315826 + if (devid == 0) {
315848 + if (devid == 0) {
315864 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
315878 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
315888 + host->mmc->actual_clock = 0;
315892 + if (clock == 0)
315930 + if (devid == 0)
315933 + return 0;
315940 @@ -0,0 +1,669 @@
315965 +#define REG_EMMC_DRV_DLL_CTRL 0x1fc
315966 +#define REG_SDIO0_DRV_DLL_CTRL 0x1fc
315967 +#define REG_SDIO1_DRV_DLL_CTRL 0x220
315969 +#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
315972 +#define REG_EMMC_DRV_DLL_STATUS 0x210
315973 +#define REG_SDIO0_DRV_DLL_STATUS 0x210
315974 +#define REG_SDIO1_DRV_DLL_STATUS 0x228
315979 +#define REG_EMMC_SAMPL_DLL_STATUS 0x208
315980 +#define REG_SDIO0_SAMPL_DLL_STATUS 0x208
315981 +#define REG_SDIO1_SAMPL_DLL_STATUS 0x224
315983 +#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
315985 +#define REG_EMMC_SAMPL_DLL_CTRL 0x1f4
315986 +#define REG_SDIO0_SAMPL_DLL_CTRL 0x1f4
315987 +#define REG_SDIO1_SAMPL_DLL_CTRL 0x22c
315991 +#define REG_EMMC_SAMPLB_DLL_CTRL 0x1f8
315992 +#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1f8
315993 +#define REG_SDIO1_SAMPLB_DLL_CTRL 0x21c
315995 +#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
315996 +#define sdio_samplb_sel(phase) ((phase) << 0)
315998 +#define REG_EMMC_DS_DLL_CTRL 0x200
316000 +#define EMMC_DS_DLL_SSEL_MASK 0x7f
316002 +#define REG_EMMC_DS180_DLL_CTRL 0x204
316004 +#define REG_EMMC_DS180_DLL_STATUS 0x218
316005 +#define EMMC_DS180_DLL_READY BIT(0)
316007 +#define REG_EMMC_DS_DLL_STATUS 0x214
316008 +#define EMMC_DS_DLL_READY BIT(0)
316010 +#define REG_EMMC_CLK_CTRL 0x1f4
316011 +#define REG_SDIO0_CLK_CTRL 0x1f4
316012 +#define REG_SDIO1_CLK_CTRL 0x22c
316020 +#define IO_CFG_DRV_STR_MASK (0xf << 4)
316022 +#define IO_CFG_PIN_MUX_MASK (0xf << 0)
316023 +#define io_cfg_pin_mux_sel(type) ((type) << 0)
316024 +#define IO_CFG_PIN_MUX_TYPE_CLK_EMMC 0x0
316025 +#define IO_CFG_PIN_MUX_TYPE_CLK_SD 0x1
316028 +#define REG_CTRL_EMMC_CLK 0x0014
316029 +#define REG_CTRL_EMMC_CMD 0x0018
316030 +#define REG_CTRL_EMMC_DATA0 0x001c
316031 +#define REG_CTRL_EMMC_DATA1 0x0028
316032 +#define REG_CTRL_EMMC_DATA2 0x0024
316033 +#define REG_CTRL_EMMC_DATA3 0x0020
316035 +#define REG_CTRL_EMMC_DS 0x0058
316036 +#define REG_CTRL_EMMC_RST 0x005c
316043 +#define REG_CTRL_SDIO0_CLK 0x0040
316044 +#define REG_CTRL_SDIO0_CMD 0x0044
316045 +#define REG_CTRL_SDIO0_DATA0 0x0048
316046 +#define REG_CTRL_SDIO0_DATA1 0x004C
316047 +#define REG_CTRL_SDIO0_DATA2 0x0050
316048 +#define REG_CTRL_SDIO0_DATA3 0x0054
316055 +#define REG_CTRL_SDIO1_CLK 0x0048
316056 +#define REG_CTRL_SDIO1_CMD 0x004C
316057 +#define REG_CTRL_SDIO1_DATA0 0x0064
316058 +#define REG_CTRL_SDIO1_DATA1 0x0060
316059 +#define REG_CTRL_SDIO1_DATA2 0x005C
316060 +#define REG_CTRL_SDIO1_DATA3 0x0058
316202 + return 0;
316224 + reg = 0;
316231 + } while (timeout > 0);
316275 + reg = 0;
316282 + } while (timeout > 0);
316306 + reg = 0;
316313 + } while (timeout > 0);
316325 + reg = 0;
316333 + } while (timeout > 0);
316350 + mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) |
316351 + SDHCI_GM_RD_OSRC_LMT_SEL(0x7));
316359 + host->error_count = 0;
316366 + unsigned int reg = 0;
316372 + reg |= (pull_up ? IO_CFG_PULL_UP : 0);
316373 + reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
316374 + reg |= (sr ? IO_CFG_SR : 0);
316399 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0,
316400 + 0x3); /* set drv level 3 */
316401 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0,
316402 + 0x4); /* set drv level 4 */
316403 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
316405 + io_emmc_data_reg[i], 1, 0, 0, 0x4); /* set drv level 4 */
316406 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1,
316407 + 0x3); /* set drv level 3 */
316408 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
316409 + 0x3); /* set drv level 3 */
316413 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0,
316414 + 0x2); /* set drv level 2 */
316415 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
316416 + 0x4); /* set drv level 4 */
316417 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
316419 + io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
316420 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
316421 + 0x3); /* set drv level 3 */
316425 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1,
316426 + 0x4); /* set drv level 4 */
316427 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
316428 + 0x6); /* set drv level 6 */
316429 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
316431 + io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
316432 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
316433 + 0x3); /* set drv level 3 */
316437 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1,
316438 + 0x5); /* set drv level 5 */
316439 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
316440 + 0x6); /* set drv level 6 */
316441 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
316443 + io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
316444 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
316445 + 0x3); /* set drv level 3 */
316458 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1,
316459 + 0x5); /* set drv level 5 */
316460 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1,
316461 + 0x7); /* set drv level 7 */
316462 + for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
316464 + io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
316468 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1,
316469 + 0x7); /* set drv level 7 */
316470 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1,
316471 + 0x7); /* set drv level 7 */
316472 + for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
316474 + io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
316485 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1,
316486 + 0x5); /* set drv level 5 */
316487 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0,
316488 + 0x7); /* set drv level 7 */
316489 + for (i = 0; i < IO_CFG_SDIO1_DATA_LINE_COUNT; i++)
316491 + io_sdio1_data_reg[i], 1, 0, 0, 0x7); /* set drv level 7 */
316499 + unsigned int reg = 0;
316501 + if (devid == 0) {
316523 + if (devid == 0) {
316539 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
316553 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
316563 + host->mmc->actual_clock = 0;
316567 + if (clock == 0)
316605 + if (devid == 0)
316608 + return 0;
316615 @@ -0,0 +1,674 @@
316640 +#define REG_EMMC_DRV_DLL_CTRL 0x1fc
316641 +#define REG_SDIO0_DRV_DLL_CTRL 0x1fc
316642 +#define REG_SDIO1_DRV_DLL_CTRL 0x220
316644 +#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
316647 +#define REG_EMMC_DRV_DLL_STATUS 0x210
316648 +#define REG_SDIO0_DRV_DLL_STATUS 0x210
316649 +#define REG_SDIO1_DRV_DLL_STATUS 0x228
316654 +#define REG_EMMC_SAMPL_DLL_STATUS 0x208
316655 +#define REG_SDIO0_SAMPL_DLL_STATUS 0x208
316656 +#define REG_SDIO1_SAMPL_DLL_STATUS 0x224
316658 +#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
316660 +#define REG_EMMC_SAMPL_DLL_CTRL 0x1f4
316661 +#define REG_SDIO0_SAMPL_DLL_CTRL 0x1f4
316662 +#define REG_SDIO1_SAMPL_DLL_CTRL 0x22c
316666 +#define REG_EMMC_SAMPLB_DLL_CTRL 0x1f8
316667 +#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1f8
316668 +#define REG_SDIO1_SAMPLB_DLL_CTRL 0x21c
316670 +#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
316671 +#define sdio_samplb_sel(phase) ((phase) << 0)
316673 +#define REG_EMMC_DS_DLL_CTRL 0x200
316675 +#define EMMC_DS_DLL_SSEL_MASK 0x7f
316677 +#define REG_EMMC_DS180_DLL_CTRL 0x204
316679 +#define REG_EMMC_DS180_DLL_STATUS 0x218
316680 +#define EMMC_DS180_DLL_READY BIT(0)
316682 +#define REG_EMMC_DS_DLL_STATUS 0x214
316683 +#define EMMC_DS_DLL_READY BIT(0)
316685 +#define REG_EMMC_CLK_CTRL 0x1f4
316686 +#define REG_SDIO0_CLK_CTRL 0x1f4
316687 +#define REG_SDIO1_CLK_CTRL 0x22c
316695 +#define IO_CFG_DRV_STR_MASK (0xf << 4)
316697 +#define IO_CFG_PIN_MUX_MASK (0xf << 0)
316698 +#define io_cfg_pin_mux_sel(type) ((type) << 0)
316699 +#define IO_CFG_PIN_MUX_TYPE_CLK_EMMC 0x0
316700 +#define IO_CFG_PIN_MUX_TYPE_CLK_SD 0x1
316703 +#define REG_CTRL_EMMC_CLK 0x0014
316704 +#define REG_CTRL_EMMC_CMD 0x0018
316705 +#define REG_CTRL_EMMC_DATA0 0x001c
316706 +#define REG_CTRL_EMMC_DATA1 0x0028
316707 +#define REG_CTRL_EMMC_DATA2 0x0024
316708 +#define REG_CTRL_EMMC_DATA3 0x0020
316709 +#define REG_CTRL_EMMC_DATA4 0x0030
316710 +#define REG_CTRL_EMMC_DATA5 0x0034
316711 +#define REG_CTRL_EMMC_DATA6 0x0038
316712 +#define REG_CTRL_EMMC_DATA7 0x003c
316713 +#define REG_CTRL_EMMC_DS 0x0058
316714 +#define REG_CTRL_EMMC_RST 0x005c
316723 +#define REG_CTRL_SDIO0_CLK 0x0040
316724 +#define REG_CTRL_SDIO0_CMD 0x0044
316725 +#define REG_CTRL_SDIO0_DATA0 0x0048
316726 +#define REG_CTRL_SDIO0_DATA1 0x004C
316727 +#define REG_CTRL_SDIO0_DATA2 0x0050
316728 +#define REG_CTRL_SDIO0_DATA3 0x0054
316735 +#define REG_CTRL_SDIO1_CLK 0x0060
316736 +#define REG_CTRL_SDIO1_CMD 0x0064
316737 +#define REG_CTRL_SDIO1_DATA0 0x0068
316738 +#define REG_CTRL_SDIO1_DATA1 0x006C
316739 +#define REG_CTRL_SDIO1_DATA2 0x0070
316740 +#define REG_CTRL_SDIO1_DATA3 0x0074
316882 + return 0;
316904 + reg = 0;
316911 + } while (timeout > 0);
316955 + reg = 0;
316962 + } while (timeout > 0);
316986 + reg = 0;
316993 + } while (timeout > 0);
317005 + reg = 0;
317013 + } while (timeout > 0);
317030 + mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) |
317031 + SDHCI_GM_RD_OSRC_LMT_SEL(0x7));
317039 + host->error_count = 0;
317046 + unsigned int reg = 0;
317052 + reg |= (pull_up ? IO_CFG_PULL_UP : 0);
317053 + reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
317054 + reg |= (sr ? IO_CFG_SR : 0);
317079 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0,
317080 + 0x3); /* set drv level 3 */
317081 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0,
317082 + 0x4); /* set drv level 4 */
317083 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
317085 + io_emmc_data_reg[i], 1, 0, 0, 0x4); /* set drv level 4 */
317086 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1,
317087 + 0x3); /* set drv level 3 */
317088 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
317089 + 0x3); /* set drv level 3 */
317093 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0,
317094 + 0x2); /* set drv level 2 */
317095 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
317096 + 0x4); /* set drv level 4 */
317097 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
317099 + io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
317100 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
317101 + 0x3); /* set drv level 3 */
317105 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1,
317106 + 0x4); /* set drv level 4 */
317107 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
317108 + 0x6); /* set drv level 6 */
317109 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
317111 + io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
317112 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
317113 + 0x3); /* set drv level 3 */
317117 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1,
317118 + 0x5); /* set drv level 5 */
317119 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
317120 + 0x6); /* set drv level 6 */
317121 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
317123 + io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
317124 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
317125 + 0x3); /* set drv level 3 */
317138 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1,
317139 + 0x5); /* set drv level 5 */
317140 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1,
317141 + 0x7); /* set drv level 7 */
317142 + for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
317144 + io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
317148 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1,
317149 + 0x7); /* set drv level 7 */
317150 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1,
317151 + 0x7); /* set drv level 7 */
317152 + for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
317154 + io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
317165 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1,
317166 + 0x5); /* set drv level 5 */
317167 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0,
317168 + 0x7); /* set drv level 7 */
317169 + for (i = 0; i < IO_CFG_SDIO1_DATA_LINE_COUNT; i++)
317171 + io_sdio1_data_reg[i], 1, 0, 0, 0x7); /* set drv level 7 */
317179 + unsigned int reg = 0;
317181 + if (devid == 0) {
317203 + if (devid == 0) {
317219 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
317233 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
317243 + host->mmc->actual_clock = 0;
317247 + if (clock == 0)
317285 + if (devid == 0)
317288 + return 0;
317295 @@ -0,0 +1,669 @@
317320 +#define REG_EMMC_DRV_DLL_CTRL 0x1fc
317321 +#define REG_SDIO0_DRV_DLL_CTRL 0x1fc
317322 +#define REG_SDIO1_DRV_DLL_CTRL 0x220
317324 +#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
317327 +#define REG_EMMC_DRV_DLL_STATUS 0x210
317328 +#define REG_SDIO0_DRV_DLL_STATUS 0x210
317329 +#define REG_SDIO1_DRV_DLL_STATUS 0x228
317334 +#define REG_EMMC_SAMPL_DLL_STATUS 0x208
317335 +#define REG_SDIO0_SAMPL_DLL_STATUS 0x208
317336 +#define REG_SDIO1_SAMPL_DLL_STATUS 0x224
317338 +#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
317340 +#define REG_EMMC_SAMPL_DLL_CTRL 0x1f4
317341 +#define REG_SDIO0_SAMPL_DLL_CTRL 0x1f4
317342 +#define REG_SDIO1_SAMPL_DLL_CTRL 0x22c
317346 +#define REG_EMMC_SAMPLB_DLL_CTRL 0x1f8
317347 +#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1f8
317348 +#define REG_SDIO1_SAMPLB_DLL_CTRL 0x21c
317350 +#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
317351 +#define sdio_samplb_sel(phase) ((phase) << 0)
317353 +#define REG_EMMC_DS_DLL_CTRL 0x200
317355 +#define EMMC_DS_DLL_SSEL_MASK 0x7f
317357 +#define REG_EMMC_DS180_DLL_CTRL 0x204
317359 +#define REG_EMMC_DS180_DLL_STATUS 0x218
317360 +#define EMMC_DS180_DLL_READY BIT(0)
317362 +#define REG_EMMC_DS_DLL_STATUS 0x214
317363 +#define EMMC_DS_DLL_READY BIT(0)
317365 +#define REG_EMMC_CLK_CTRL 0x1f4
317366 +#define REG_SDIO0_CLK_CTRL 0x1f4
317367 +#define REG_SDIO1_CLK_CTRL 0x22c
317375 +#define IO_CFG_DRV_STR_MASK (0xf << 4)
317377 +#define IO_CFG_PIN_MUX_MASK (0xf << 0)
317378 +#define io_cfg_pin_mux_sel(type) ((type) << 0)
317379 +#define IO_CFG_PIN_MUX_TYPE_CLK_EMMC 0x0
317380 +#define IO_CFG_PIN_MUX_TYPE_CLK_SD 0x1
317383 +#define REG_CTRL_EMMC_CLK 0x0014
317384 +#define REG_CTRL_EMMC_CMD 0x0018
317385 +#define REG_CTRL_EMMC_DATA0 0x001c
317386 +#define REG_CTRL_EMMC_DATA1 0x0028
317387 +#define REG_CTRL_EMMC_DATA2 0x0024
317388 +#define REG_CTRL_EMMC_DATA3 0x0020
317390 +#define REG_CTRL_EMMC_DS 0x0058
317391 +#define REG_CTRL_EMMC_RST 0x005c
317398 +#define REG_CTRL_SDIO0_CLK 0x0040
317399 +#define REG_CTRL_SDIO0_CMD 0x0044
317400 +#define REG_CTRL_SDIO0_DATA0 0x0048
317401 +#define REG_CTRL_SDIO0_DATA1 0x004C
317402 +#define REG_CTRL_SDIO0_DATA2 0x0050
317403 +#define REG_CTRL_SDIO0_DATA3 0x0054
317410 +#define REG_CTRL_SDIO1_CLK 0x0048
317411 +#define REG_CTRL_SDIO1_CMD 0x004C
317412 +#define REG_CTRL_SDIO1_DATA0 0x0064
317413 +#define REG_CTRL_SDIO1_DATA1 0x0060
317414 +#define REG_CTRL_SDIO1_DATA2 0x005C
317415 +#define REG_CTRL_SDIO1_DATA3 0x0058
317557 + return 0;
317579 + reg = 0;
317586 + } while (timeout > 0);
317630 + reg = 0;
317637 + } while (timeout > 0);
317661 + reg = 0;
317668 + } while (timeout > 0);
317680 + reg = 0;
317688 + } while (timeout > 0);
317705 + mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) |
317706 + SDHCI_GM_RD_OSRC_LMT_SEL(0x7));
317714 + host->error_count = 0;
317721 + unsigned int reg = 0;
317727 + reg |= (pull_up ? IO_CFG_PULL_UP : 0);
317728 + reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
317729 + reg |= (sr ? IO_CFG_SR : 0);
317754 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0,
317755 + 0x3); /* set drv level 3 */
317756 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 0,
317757 + 0x4); /* set drv level 4 */
317758 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
317760 + io_emmc_data_reg[i], 1, 0, 0, 0x4); /* set drv level 4 */
317761 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_DS, 0, 1, 1,
317762 + 0x3); /* set drv level 3 */
317763 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
317764 + 0x3); /* set drv level 3 */
317768 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 0,
317769 + 0x2); /* set drv level 2 */
317770 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
317771 + 0x4); /* set drv level 4 */
317772 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
317774 + io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
317775 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
317776 + 0x3); /* set drv level 3 */
317780 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1,
317781 + 0x4); /* set drv level 4 */
317782 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
317783 + 0x6); /* set drv level 6 */
317784 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
317786 + io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
317787 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
317788 + 0x3); /* set drv level 3 */
317792 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CLK, 0, 1, 1,
317793 + 0x5); /* set drv level 5 */
317794 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_CMD, 1, 0, 1,
317795 + 0x6); /* set drv level 6 */
317796 + for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
317798 + io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
317799 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_EMMC_RST, 1, 0, 1,
317800 + 0x3); /* set drv level 3 */
317813 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1,
317814 + 0x5); /* set drv level 5 */
317815 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1,
317816 + 0x7); /* set drv level 7 */
317817 + for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
317819 + io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
317823 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CLK, 0, 1, 1,
317824 + 0x7); /* set drv level 7 */
317825 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO0_CMD, 1, 0, 1,
317826 + 0x7); /* set drv level 7 */
317827 + for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
317829 + io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
317840 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CLK, 0, 1, 1,
317841 + 0x3); /* set drv level 3 */
317842 + hisi_set_drv_str(iocfg_regmap, REG_CTRL_SDIO1_CMD, 1, 0, 0,
317843 + 0x6); /* set drv level 6 */
317844 + for (i = 0; i < IO_CFG_SDIO1_DATA_LINE_COUNT; i++)
317846 + io_sdio1_data_reg[i], 1, 0, 0, 0x6); /* set drv level 6 */
317854 + unsigned int reg = 0;
317856 + if (devid == 0) {
317878 + if (devid == 0) {
317894 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
317908 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
317918 + host->mmc->actual_clock = 0;
317922 + if (clock == 0)
317960 + if (devid == 0)
317963 + return 0;
317970 @@ -0,0 +1,19 @@
317995 @@ -0,0 +1,573 @@
318018 +#define PERI_CRG_MMC_DRV_DLL 0x34c8
318020 +#define CRG_DRV_PHASE_SEL_MASK (0x1F << 15)
318022 +#define PERI_CRG_MMC_STAT 0x34d8
318028 +#define REG_MMC_CLK_IO 0xc8
318029 +#define REG_MMC_CMD_IO 0xcc
318030 +#define REG_MMC_D0_IO 0xd0
318031 +#define REG_MMC_D1_IO 0xd4
318032 +#define REG_MMC_D2_IO 0xd8
318033 +#define REG_MMC_D3_IO 0xdc
318034 +#define REG_MMC_D4_IO 0xec
318035 +#define REG_MMC_D6_IO 0xf0
318036 +#define REG_MMC_D5_IO 0xe0
318037 +#define REG_MMC_D7_IO 0xe4
318038 +#define REG_MMC_DQS_IO 0xf4
318039 +#define REG_MMC_RST_IO 0xc4
318041 +#define REG_SD_PWR_EN_IO 0xc4
318042 +#define REG_SD_DETECT_IO 0xfc
318045 +#define IO_CFG_DRV_STR_MASK (0xf << 4)
318052 +#define IO_CFG_SDIO_MUX 0x2
318053 +#define IO_CFG_EMMC_MUX 0x1
318054 +#define IO_CFG_MUX_MASK 0xF
318058 +#define REG_SYSSTAT 0x11020018
318061 +#define BOOT_FLAG_MASK (0x3 << 2)
318063 +#define IO_CLK 0
318072 +#define DRIVE 0
318088 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318089 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318090 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318091 + io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
318094 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318095 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318096 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318097 + io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
318100 + io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
318101 + io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
318102 + io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
318103 + io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
318106 + io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
318107 + io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP,
318108 + io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP,
318109 + io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP,
318110 + io_cfg_drv_str_sel(0x3)
318116 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318117 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318118 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP
318121 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318122 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318123 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP
318129 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318130 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318131 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP
318134 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318135 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318136 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP
318139 + io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_DOWN,
318140 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_UP,
318141 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_UP
318144 + io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_DOWN,
318145 + io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
318146 + io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP
318149 + io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
318150 + io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP,
318151 + io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP
318154 + io_cfg_drv_str_sel(0x0) | IO_CFG_PULL_DOWN,
318155 + io_cfg_drv_str_sel(0x9) | IO_CFG_PULL_UP,
318156 + io_cfg_drv_str_sel(0x9) | IO_CFG_PULL_UP
318161 + [MMC_TIMING_LEGACY] = { 16, 0 },
318164 + [MMC_TIMING_UHS_SDR12] = { 16, 0 },
318166 + [MMC_TIMING_UHS_SDR50] = { 20, 0 },
318167 + [MMC_TIMING_UHS_SDR104] = { 20, 0 },
318168 + [MMC_TIMING_MMC_HS200] = { 22, 0 },
318170 + [MMC_TIMING_MMC_HS400] = { 9, 0 }
318172 + [MMC_TIMING_MMC_HS400] = { 11, 0 }
318186 + if (priv->devid == 0) {
318192 + host->error_count = 0;
318209 + if (priv->devid == 0) { /* emmc devices */
318214 + for (i = 0; i < priv->bus_width; i++)
318227 + for (i = 0; i < priv->bus_width; i++)
318235 + for (i = 0; i < priv->bus_width; i++)
318333 + if (priv->devid == 0) {
318387 + pin_mux = (devid == 0) ? IO_CFG_EMMC_MUX : IO_CFG_SDIO_MUX;
318390 + for (i = 0; i < bus_width; i++)
318393 + if (devid == 0) { /* eMMC device */
318450 + return 0;
318515 + return 0;
318528 + if (clk == 0) {
318529 + host->mmc->actual_clock = 0;
318567 + return (priv->devid == 0 || priv->devid == 1) ? 1 : 0;
318574 @@ -0,0 +1,548 @@
318597 +#define PERI_CRG_MMC_DRV_DLL 0x34c8
318599 +#define CRG_DRV_PHASE_SEL_MASK (0x1F << 15)
318601 +#define PERI_CRG_MMC_STAT 0x34d8
318607 +#define REG_MMC_CLK_IO 0x10
318608 +#define REG_MMC_CMD_IO 0x14
318609 +#define REG_MMC_D0_IO 0x00
318610 +#define REG_MMC_D1_IO 0x04
318611 +#define REG_MMC_D2_IO 0x08
318612 +#define REG_MMC_D3_IO 0x0c
318613 +#define REG_MMC_D4_IO 0x1c
318614 +#define REG_MMC_D6_IO 0x20
318615 +#define REG_MMC_D5_IO 0x28
318616 +#define REG_MMC_D7_IO 0x2C
318617 +#define REG_MMC_DQS_IO 0x30
318618 +#define REG_MMC_RST_IO 0x18
318621 +#define IO_CFG_DRV_STR_MASK (0xf << 4)
318628 +#define IO_CFG_SDIO_MUX 0x1
318629 +#define IO_CFG_EMMC_MUX 0x2
318630 +#define IO_CFG_MUX_MASK 0xF
318634 +#define REG_SYSSTAT 0x11020018
318637 +#define BOOT_FLAG_MASK (0x3 << 2)
318639 +#define IO_CLK 0
318648 +#define DRIVE 0
318661 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318662 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318663 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318664 + io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
318667 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318668 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318669 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318670 + io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
318673 + io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
318674 + io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
318675 + io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
318676 + io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
318679 + io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
318680 + io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_UP,
318681 + io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_UP,
318682 + io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP,
318683 + io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_DOWN
318689 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318690 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318691 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP
318694 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
318695 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
318696 + io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP
318699 + io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_DOWN,
318700 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_UP,
318701 + io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_UP
318704 + io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_DOWN,
318705 + io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
318706 + io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP
318709 + io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
318710 + io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP,
318711 + io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP
318714 + io_cfg_drv_str_sel(0x0) | IO_CFG_PULL_DOWN,
318715 + io_cfg_drv_str_sel(0x9) | IO_CFG_PULL_UP,
318716 + io_cfg_drv_str_sel(0x9) | IO_CFG_PULL_UP
318721 + [MMC_TIMING_LEGACY] = { 16, 0 },
318724 + [MMC_TIMING_UHS_SDR12] = { 16, 0 },
318726 + [MMC_TIMING_UHS_SDR50] = { 20, 0 },
318727 + [MMC_TIMING_UHS_SDR104] = { 20, 0 },
318728 + [MMC_TIMING_MMC_HS200] = { 22, 0 },
318729 + [MMC_TIMING_MMC_HS400] = { 9, 0 }
318742 + if (priv->devid == 0) {
318748 + host->error_count = 0;
318765 + if (priv->devid == 0) { /* emmc devices */
318770 + for (i = 0; i < priv->bus_width; i++)
318783 + for (i = 0; i < priv->bus_width; i++)
318802 + } while (timeout > 0);
318820 + } while (timeout > 0);
318838 + } while (timeout > 0);
318894 + if (priv->devid == 0) {
318948 + pin_mux = (devid == 0) ? IO_CFG_EMMC_MUX : IO_CFG_SDIO_MUX;
318951 + for (i = 0; i < bus_width; i++)
318954 + if (devid == 0) { /* eMMC device */
319004 + return 0;
319069 + return 0;
319082 + if (clk == 0) {
319083 + host->mmc->actual_clock = 0;
319121 + return (priv->devid == 0) ? 1 : 0;
319128 @@ -0,0 +1,627 @@
319149 +#define REG_EMMC_DRV_DLL_CTRL 0x1b0
319150 +#define REG_SDIO0_DRV_DLL_CTRL 0x1d4
319151 +#define REG_SDIO1_DRV_DLL_CTRL 0x1fc
319153 +#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
319156 +#define REG_EMMC_DRV_DLL_STATUS 0x1c4
319157 +#define REG_SDIO0_DRV_DLL_STATUS 0x1e8
319158 +#define REG_SDIO1_DRV_DLL_STATUS 0x210
319162 +#define REG_EMMC_SAMPL_DLL_STATUS 0x1bc
319163 +#define REG_SDIO0_SAMPL_DLL_STATUS 0x1e0
319164 +#define REG_SDIO1_SAMPL_DLL_STATUS 0x208
319168 +#define REG_EMMC_SAMPL_DLL_CTRL 0x1a8
319169 +#define REG_SDIO0_SAMPL_DLL_CTRL 0x1ec
319170 +#define REG_SDIO1_SAMPL_DLL_CTRL 0x214
319174 +#define REG_EMMC_SAMPLB_DLL_CTRL 0x1ac
319175 +#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1d0
319176 +#define REG_SDIO1_SAMPLB_DLL_CTRL 0x1f8
319178 +#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 24)
319181 +#define REG_EMMC_DS_DLL_CTRL 0x1b4
319183 +#define EMMC_DS_DLL_SSEL_MASK 0x1fff
319184 +#define REG_EMMC_DS180_DLL_CTRL 0x1b8
319186 +#define REG_EMMC_DS_DLL_STATUS 0x1c8
319188 +#define EMMC_DS_DLL_MDLY_TAP_MASK 0x1fff
319190 +#define REG_MISC_CTRL1 0x4
319194 +#define REG_MISC_CTRL18 0x48
319198 +#define SDIO0_PWR_CTRL_BY_MISC BIT(0)
319200 +#define REG_IOCTL_RONSEL_1_0 0x264
319201 +#define REG_IOCTL_OD_RONSEL_2 0x268
319203 +#define REG_CTRL_SDIO0_CLK 0x006c
319204 +#define REG_CTRL_SDIO0_CMD 0x0070
319205 +#define REG_CTRL_SDIO0_DATA0 0x0074
319206 +#define REG_CTRL_SDIO0_DATA1 0x0078
319207 +#define REG_CTRL_SDIO0_DATA2 0x007c
319208 +#define REG_CTRL_SDIO0_DATA3 0x0080
319209 +#define REG_CTRL_SDIO1_CLK 0x0084
319210 +#define REG_CTRL_SDIO1_CMD 0x0088
319211 +#define REG_CTRL_SDIO1_DATA0 0x008c
319212 +#define REG_CTRL_SDIO1_DATA1 0x0090
319213 +#define REG_CTRL_SDIO1_DATA2 0x0094
319214 +#define REG_CTRL_SDIO1_DATA3 0x0098
319218 +static unsigned int sd_sdr104_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
319219 +static unsigned int sd_sdr50_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
319220 +static unsigned int sd_sdr25_hs_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
319221 +static unsigned int sd_other_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
319225 +static unsigned int sdio_sdr104_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
319227 +static unsigned int sdio_sdr104_drv[] = { 0xc0, 0x90, 0x90, 0x90, 0x90, 0x90 };
319229 +static unsigned int sdio_sdr50_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
319230 +static unsigned int sdio_sdr25_hs_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
319231 +static unsigned int sdio_other_drv[] = { 0x60, 0x20, 0x20, 0x20, 0x20, 0x20 };
319266 + unsigned int ctrl = 0;
319280 + unsigned int ctrl = 0;
319299 + return 0;
319312 + unsigned int ctrl = 0;
319316 + if (hisi_priv->devid == 0)
319317 + return 0;
319332 + return 0;
319336 + return 0;
319394 + if (hisi_priv->devid == 0) {
319460 + return 0;
319492 + reg = 0;
319499 + } while (timeout > 0);
319511 + reg = 0;
319518 + } while (timeout > 0);
319547 + reg = 0;
319554 + } while (timeout > 0);
319573 + return 0;
319588 + mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x7) |
319589 + SDHCI_GM_RD_OSRC_LMT_SEL(0x7));
319596 + host->error_count = 0;
319617 + reg_addr <= REG_CTRL_SDIO0_DATA3; reg_addr += 0x4) {
319618 + regmap_write_bits(iocfg_regmap, reg_addr, 0xf0, *pin_drv_cap);
319641 + reg_addr <= REG_CTRL_SDIO1_DATA3; reg_addr += 0x4) {
319642 + regmap_write_bits(iocfg_regmap, reg_addr, 0xf0, *pin_drv_cap);
319654 + if (devid == 0) {
319663 + writel(0x6ff, phy_addr + REG_IOCTL_RONSEL_1_0);
319664 + writel(0x6ff, phy_addr + REG_IOCTL_OD_RONSEL_2);
319699 + hisi_priv->sample_phase = 0; /* 0 for 0 egree */
319707 + host->mmc->actual_clock = 0;
319711 + if (clock == 0)
319754 + return 0;
319761 @@ -0,0 +1,630 @@
319782 +#define REG_EMMC_DRV_DLL_CTRL 0x1b0
319783 +#define REG_SDIO0_DRV_DLL_CTRL 0x1d4
319784 +#define REG_SDIO1_DRV_DLL_CTRL 0x1fc
319785 +#define REG_SDIO2_DRV_DLL_CTRL 0x224
319786 +#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
319789 +#define REG_EMMC_DRV_DLL_STATUS 0x1c4
319790 +#define REG_SDIO0_DRV_DLL_STATUS 0x1e8
319791 +#define REG_SDIO1_DRV_DLL_STATUS 0x210
319792 +#define REG_SDIO2_DRV_DLL_STATUS 0x238
319795 +#define REG_EMMC_SAMPL_DLL_STATUS 0x1bc
319796 +#define REG_SDIO0_SAMPL_DLL_STATUS 0x1e0
319797 +#define REG_SDIO1_SAMPL_DLL_STATUS 0x208
319798 +#define REG_SDIO2_SAMPL_DLL_STATUS 0x230
319801 +#define REG_EMMC_SAMPL_DLL_CTRL 0x1a8
319802 +#define REG_SDIO0_SAMPL_DLL_CTRL 0x1ec
319803 +#define REG_SDIO1_SAMPL_DLL_CTRL 0x214
319804 +#define REG_SDIO2_SAMPL_DLL_CTRL 0x23c
319807 +#define REG_EMMC_SAMPLB_DLL_CTRL 0x1ac
319808 +#define REG_SDIO0_SAMPLB_DLL_CTRL 0x1d0
319809 +#define REG_SDIO1_SAMPLB_DLL_CTRL 0x1f8
319810 +#define REG_SDIO2_SAMPLB_DLL_CTRL 0x220
319811 +#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 24)
319814 +#define REG_EMMC_DS_DLL_CTRL 0x1b4
319816 +#define EMMC_DS_DLL_SSEL_MASK 0x1fff
319817 +#define REG_EMMC_DS180_DLL_CTRL 0x1b8
319819 +#define REG_EMMC_DS_DLL_STATUS 0x1c8
319821 +#define EMMC_DS_DLL_MDLY_TAP_MASK 0x1fff
319823 +#define REG_MISC_CTRL3 0xc
319828 +#define REG_MISC_CTRL18 0x48
319833 +#define SDIO0_PWR_CTRL_BY_MISC BIT(0)
319836 +#define REG_IOCTL_RONSEL_1_0 0x264
319837 +#define REG_IOCTL_OD_RONSEL_2 0x268
319839 +#define REG_CTRL_SDIO0_CLK 0x104c
319840 +#define REG_CTRL_SDIO0_CMD 0x1050
319841 +#define REG_CTRL_SDIO0_DATA0 0x1054
319842 +#define REG_CTRL_SDIO0_DATA1 0x1058
319843 +#define REG_CTRL_SDIO0_DATA2 0x105c
319844 +#define REG_CTRL_SDIO0_DATA3 0x1060
319845 +#define REG_CTRL_SDIO1_CLK 0x106c
319846 +#define REG_CTRL_SDIO1_CMD 0x1070
319847 +#define REG_CTRL_SDIO1_DATA0 0x1074
319848 +#define REG_CTRL_SDIO1_DATA1 0x1078
319849 +#define REG_CTRL_SDIO1_DATA2 0x107c
319850 +#define REG_CTRL_SDIO1_DATA3 0x1080
319851 +#define REG_CTRL_SDIO2_CLK 0x10b0
319852 +#define REG_CTRL_SDIO2_CMD 0x10b8
319853 +#define REG_CTRL_SDIO2_DATA0 0x10ac
319854 +#define REG_CTRL_SDIO2_DATA1 0x1084
319855 +#define REG_CTRL_SDIO2_DATA2 0x10a0
319856 +#define REG_CTRL_SDIO2_DATA3 0x10bc
319867 +static unsigned int sdr104_drv[] = { 0x60, 0x60, 0x60, 0x60, 0x60, 0x60 };
319868 +static unsigned int sdrxx_drv[] = { 0x40, 0x40, 0x40, 0x40, 0x40, 0x40 };
319869 +static unsigned int hs_ds_drv[] = { 0x70, 0x40, 0x40, 0x40, 0x40, 0x40 };
319922 + return 0;
319941 + return 0;
319951 + return 0;
319968 + if (hisi_priv->devid == 0 || hisi_priv->devid == 3) /* for device id 0 and 3 */
319969 + return 0;
319983 + return 0;
320042 + if (hisi_priv->devid == 0) {
320110 + return 0;
320142 + reg = 0;
320149 + } while (timeout > 0);
320161 + reg = 0;
320168 + } while (timeout > 0);
320203 + reg = 0;
320210 + } while (timeout > 0);
320229 + return 0;
320244 + mbiiu_ctrl |= (SDHCI_GM_WR_OSRC_LMT_SEL(0x3) |
320245 + SDHCI_GM_RD_OSRC_LMT_SEL(0x3));
320252 + host->error_count = 0;
320275 + for (i = 0; i < 6; i++) { /* for 6 pins */
320277 + 0xf0, *pin_drv_cap);
320286 + for (reg_addr = start; reg_addr <= end; reg_addr += 0x4) {
320287 + regmap_write_bits(iocfg_regmap, reg_addr, 0xf0, *pin_drv_cap);
320299 + if (devid == 0) {
320308 + writel(0x0, phy_addr + REG_IOCTL_RONSEL_1_0);
320309 + writel(0x6ff, phy_addr + REG_IOCTL_OD_RONSEL_2);
320335 + hisi_priv->sample_phase = 0; /* 0 or 0 degree */
320343 + host->mmc->actual_clock = 0;
320347 + if (clock == 0)
320390 + return 0;
320397 @@ -0,0 +1,783 @@
320438 + if (of_property_read_u32(np, "bus-width", &bus_width) == 0) {
320452 + return 0;
320512 + if (timeout == 0) {
320537 + count = 0;
320569 + host->is_tuning = 0;
320581 + int win_max = 0;
320583 + for (i = 0; i < PHASE_SCALE; i++) {
320584 + if ((candidates & 0x3) == 0x2)
320587 + if ((candidates & 0x3) == 0x1) {
320630 + unsigned int candidates = 0;
320635 + for (sample = 0; sample < PHASE_SCALE; sample++) {
320643 + candidates |= (0x1 << sample);
320646 + pr_info("%s: tuning done! candidates 0x%X: ",
320659 + return 0;
320685 + unsigned int prev_found = 0;
320688 + unsigned int fall_updat_flag = 0;
320690 + int prev_err = 0;
320695 + start = 0;
320700 + for (index = 0; index <= end; index++) {
320775 + return 0;
320813 + sdhci_writel(host, 0x0, SDHCI_EMMC_HW_RESET);
320815 + sdhci_writel(host, 0x1, SDHCI_EMMC_HW_RESET);
320826 + if ((slot >= MCI_SLOT_NUM) || (slot <= 0)) {
320837 + mmc_detect_change(mmc, 0);
320838 + return 0;
320873 + int cmd_error = 0;
320874 + int data_error = 0;
320881 + return 0;
320957 + sdhci_hisi_controller_v4_enable(mmc_priv(mmc), 0);
321010 + cq_host->mmio = host->ioaddr + 0x180;
321033 + return 0;
321085 + return 0;
321103 + 0xffffffff);
321114 + return 0;
321123 + return 0;
321131 + return 0;
321186 @@ -0,0 +1,126 @@
321252 +#define SDHCI_CTRL_HOST_VER4_ENABLE 0x1000
321253 +#define SDHCI_CLOCK_PLL_EN 0x0008
321254 +#define SDHCI_CTRL_64BIT_ADDR 0x2000
321255 +#define SDHCI_CAN_DO_ADMA3 0x08000000
321258 +#define SDHCI_MSHC_CTRL 0x508
321259 +#define SDHCI_CMD_CONFLIT_CHECK 0x01
321261 +#define SDHCI_AXI_MBIIU_CTRL 0x510
321262 +#define SDHCI_GM_WR_OSRC_LMT_MASK (0x7 << 24)
321264 +#define SDHCI_GM_RD_OSRC_LMT_MASK (0x7 << 16)
321266 +#define SDHCI_UNDEFL_INCR_EN 0x1
321268 +#define SDHCI_EMMC_CTRL 0x52C
321269 +#define SDHCI_CARD_IS_EMMC 0x0001
321270 +#define SDHCI_ENH_STROBE_EN 0x0100
321272 +#define SDHCI_EMMC_HW_RESET 0x534
321274 +#define SDHCI_AT_CTRL 0x540
321275 +#define SDHCI_SAMPLE_EN 0x00000010
321277 +#define SDHCI_AT_STAT 0x544
321278 +#define SDHCI_PHASE_SEL_MASK 0x000000FF
321280 +#define SDHCI_MULTI_CYCLE 0x54C
321281 +#define SDHCI_FOUND_EDGE (0x1 << 11)
321282 +#define SDHCI_EDGE_DETECT_EN (0x1 << 8)
321283 +#define SDHCI_DOUT_EN_F_EDGE (0x1 << 6)
321284 +#define SDHCI_DATA_DLY_EN (0x1 << 3)
321285 +#define SDHCI_CMD_DLY_EN (0x1 << 2)
321327 host->clock = 0;
321345 + attr_addr[0] = cpu_to_le32(attr);
321346 + reg_addr[0] = cpu_to_le32(reg);
321354 + attr_addr[0] = cpu_to_le32(attr);
321358 + cmd_ddr[0] = cpu_to_le64(addr);
321361 + cmd_ddr[0] = cpu_to_le32(addr);
321372 + blksz = SDHCI_MAKE_BLKSZ(0, data->blksz);
321377 + sdhci_write_cmd_table(host->cmd_table + 0x8, blksz, ADMA3_CMD_VALID); // add 0x8
321378 + sdhci_write_cmd_table(host->cmd_table + 0x10, // add 0x10
321380 + sdhci_write_cmd_table(host->cmd_table + 0x18, // add 0x18
321382 + sdhci_adma_write_desc(host, host->cmd_table + 0x20, // add 0x20
321383 + host->adma_addr, 0x0, ADMA2_LINK_VALID);
321439 if (sg_cnt <= 0) {
321518 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
321523 + if ((cmd->resp[0] & CMD_ERRORS) && !host->is_tuning)
321530 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
321574 + memset(c_info,0,sizeof(struct card_info));
321592 + return 0;
321645 - pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
321647 + /*pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
321669 DBG("IRQ status 0x%08x\n", intmask);
321698 sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
321712 return 0;
321835 if (curr > 0) {
321877 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
321878 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
321897 #define SDHCI_CTRL_ADMA1 0x08
321898 #define SDHCI_CTRL_ADMA32 0x10
321899 #define SDHCI_CTRL_ADMA64 0x18
321900 +#define SDHCI_CTRL_ADMA3 0x18
321901 #define SDHCI_CTRL_8BITBUS 0x20
321902 #define SDHCI_CTRL_CDTEST_INS 0x40
321903 #define SDHCI_CTRL_CDTEST_EN 0x80
321906 #define SDHCI_DIV_HI_MASK 0x300
321907 #define SDHCI_PROG_CLOCK_MODE 0x0020
321908 +#define SDHCI_CLOCK_PLL_EN 0x0008
321909 #define SDHCI_CLOCK_CARD_EN 0x0004
321910 #define SDHCI_CLOCK_INT_STABLE 0x0002
321911 #define SDHCI_CLOCK_INT_EN 0x0001
321913 #define SDHCI_INT_CARD_INT 0x00000100
321914 #define SDHCI_INT_RETUNE 0x00001000
321915 #define SDHCI_INT_CQE 0x00004000
321916 +#define SDHCI_INT_CQE 0x00004000
321917 #define SDHCI_INT_ERROR 0x00008000
321918 #define SDHCI_INT_TIMEOUT 0x00010000
321919 #define SDHCI_INT_CRC 0x00020000
321923 #define SDHCI_AUTO_CMD_STATUS 0x3C
321924 +#define SDHCI_AUTO_CMD12_NOT_EXEC 0x0001
321925 #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
321926 #define SDHCI_AUTO_CMD_CRC 0x00000004
321927 #define SDHCI_AUTO_CMD_END_BIT 0x00000008
321928 #define SDHCI_AUTO_CMD_INDEX 0x00000010
321929 +#define SDHCI_AUTO_CMD12_NOT_ISSUED 0x0080
321931 #define SDHCI_HOST_CONTROL2 0x3E
321932 #define SDHCI_CTRL_UHS_MASK 0x0007
321934 #define SDHCI_CTRL_UHS_SDR50 0x0002
321935 #define SDHCI_CTRL_UHS_SDR104 0x0003
321936 #define SDHCI_CTRL_UHS_DDR50 0x0004
321937 -#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
321938 +#define SDHCI_CTRL_HS400 0x0007 /* Non-standard */
321939 #define SDHCI_CTRL_VDD_180 0x0008
321940 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
321941 #define SDHCI_CTRL_DRV_TYPE_B 0x0000
321943 #define SDHCI_CTRL_DRV_TYPE_D 0x0030
321944 #define SDHCI_CTRL_EXEC_TUNING 0x0040
321945 #define SDHCI_CTRL_TUNED_CLK 0x0080
321946 +#define SDHCI_CTRL_HOST_VER4_ENABLE 0x1000
321947 +#define SDHCI_CTRL_ADDRESSING_64BIT 0x2000
321948 +#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000
321949 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
321951 #define SDHCI_CAPABILITIES 0x40
321953 #define SDHCI_CAN_VDD_300 0x02000000
321954 #define SDHCI_CAN_VDD_180 0x04000000
321955 #define SDHCI_CAN_64BIT 0x10000000
321956 +#define SDHCI_CAN_ASYNC_INT 0x20000000
321958 #define SDHCI_SUPPORT_SDR50 0x00000001
321959 #define SDHCI_SUPPORT_SDR104 0x00000002
321962 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
321964 +#define SDHCI_CAN_DO_ADMA3 0x08000000
321965 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
321967 #define SDHCI_CAPABILITIES_1 0x44
321969 #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
321970 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
321972 +#define SDHCI_ADMA3_ID_ADDR_LOW 0x78
321973 +#define SDHCI_ADMA3_ID_ADDR_HI 0x7C
321975 #define SDHCI_SLOT_INT_STATUS 0xFC
321977 #define SDHCI_HOST_VERSION 0xFE
321979 #define SDHCI_SPEC_100 0
321992 +#define SDHCI_DMA_BOUNDARY_SIZE (0x1 << 27)
322010 #define ADMA2_TRAN_VALID 0x21
322011 #define ADMA2_NOP_END_VALID 0x3
322012 #define ADMA2_END 0x2
322013 +#define ADMA2_LINK_VALID 0x31
322014 +#define ADMA3_CMD_VALID 0x9
322015 +#define ADMA3_END 0x3b
322029 +#define CARD_DISCONNECT 0
322086 unsigned long private[0] ____cacheline_aligned;
322165 @@ -0,0 +1,17 @@
322188 @@ -0,0 +1,26 @@
322220 @@ -0,0 +1,1218 @@
322278 + unsigned long clkrate = 0;
322364 + *host->epm = 0x0000;
322369 + FMC_PR(WR_DBG, "|-Set DMA_SADDR_D[0x40]%#x\n", reg);
322446 + if ((host->addr_value[0] == host->cache_addr_value[0])
322449 + op, host->addr_value[1], host->addr_value[0]);
322529 + host->cache_addr_value[0] = host->addr_value[0];
322573 + | FMC_ADDRL_BLOCK_L_MASK(host->addr_value[0]);
322671 + host->addr_cycle = 0x0;
322725 + host->addr_cycle = 0;
322726 + host->addr_value[0] = 0;
322727 + host->addr_value[1] = 0;
322728 + host->cache_addr_value[0] = ~0;
322729 + host->cache_addr_value[1] = ~0;
322758 + unsigned char ret_val = 0;
322764 + host->cmd_op.l_cmd = 0;
322869 + if (err_num == 0xff) {
322886 + if (chipselect < 0) {
322918 + unsigned int addr_value = 0;
322919 + unsigned int addr_offset = 0;
322922 + host->addr_cycle = 0x0;
322923 + host->addr_value[0] = 0x0;
322924 + host->addr_value[1] = 0x0;
322934 + ((udat & 0xff) << addr_offset);
322940 + cmd = udat & 0xff;
322944 + host->offset = 0;
322949 + is_cache_invalid = 0;
322950 + if (host->addr_value[0] == host->pagesize) {
322961 + memset((u_char *)(host->iobase), 0,
322991 + host->offset = 0x0;
322992 + host->column = (host->addr_value[0] & 0xffff);
322997 + host->cache_addr_value[0] = ~0;
322998 + host->cache_addr_value[1] = ~0;
323031 + return 0;
323035 + * 'host->epm' only use the first oobfree[0] field, it looks very simple, But...
323048 + return 0;
323061 + return 0;
323080 + return 0;
323093 + return 0;
323111 + return 0;
323124 + return 0;
323139 + {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
323145 + {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
323146 + {0, 0, 0, 0, NULL},
323208 + struct mtd_oob_region hifmc_oobregion = {0, 0};
323228 + info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
323256 + return 0;
323269 + return 0;
323279 + unsigned int block_reg = 0;
323280 + unsigned int page_per_block = 0;
323285 + return 0;
323291 + return 0;
323349 + return 0;
323356 + /* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
323363 + return 0;
323410 + return 0;
323416 + return 0;
323429 + for (cs = 0; cs < chip->numchips; cs++) {
323436 + return 0;
323444 @@ -0,0 +1,354 @@
323471 +#define INFINITE (0xFFFFFFFF)
323473 +#define SPI_IF_READ_STD (0x01)
323474 +#define SPI_IF_READ_FAST (0x02)
323475 +#define SPI_IF_READ_DUAL (0x04)
323476 +#define SPI_IF_READ_DUAL_ADDR (0x08)
323477 +#define SPI_IF_READ_QUAD (0x10)
323478 +#define SPI_IF_READ_QUAD_ADDR (0x20)
323480 +#define SPI_IF_WRITE_STD (0x01)
323481 +#define SPI_IF_WRITE_DUAL (0x02)
323482 +#define SPI_IF_WRITE_DUAL_ADDR (0x04)
323483 +#define SPI_IF_WRITE_QUAD (0x08)
323484 +#define SPI_IF_WRITE_QUAD_ADDR (0x10)
323486 +#define SPI_IF_ERASE_SECTOR_4K (0x01)
323487 +#define SPI_IF_ERASE_SECTOR_32K (0x02)
323488 +#define SPI_IF_ERASE_SECTOR_64K (0x04)
323489 +#define SPI_IF_ERASE_SECTOR_128K (0x08)
323490 +#define SPI_IF_ERASE_SECTOR_256K (0x10)
323503 +#define SPI_CMD_READ_STD 0x03 /* Standard read cache */
323504 +#define SPI_CMD_READ_FAST 0x0B /* Higher speed read cache */
323505 +#define SPI_CMD_READ_DUAL 0x3B /* 2 IO read cache only date */
323506 +#define SPI_CMD_READ_DUAL_ADDR 0xBB /* 2 IO read cache date&addr */
323507 +#define SPI_CMD_READ_QUAD 0x6B /* 4 IO read cache only date */
323508 +#define SPI_CMD_READ_QUAD_ADDR 0xEB /* 4 IO read cache date&addr */
323510 +#define SPI_CMD_WRITE_STD 0x02 /* Standard page program */
323511 +#define SPI_CMD_WRITE_DUAL 0xA2 /* 2 IO program only date */
323512 +#define SPI_CMD_WRITE_DUAL_ADDR 0xD2 /* 2 IO program date&addr */
323513 +#define SPI_CMD_WRITE_QUAD 0x32 /* 4 IO program only date */
323514 +#define SPI_CMD_WRITE_QUAD_ADDR 0x12 /* 4 IO program date&addr */
323516 +#define SPI_CMD_SE_4K 0x20 /* 4KB sector Erase */
323517 +#define SPI_CMD_SE_32K 0x52 /* 32KB sector Erase */
323518 +#define SPI_CMD_SE_64K 0xD8 /* 64KB sector Erase */
323519 +#define SPI_CMD_SE_128K 0xD8 /* 128KB sector Erase */
323520 +#define SPI_CMD_SE_256K 0xD8 /* 256KB sector Erase */
323614 +#define SPI_CMD_WREN 0x06 /* Write Enable */
323615 +#define SPI_CMD_WRDI 0x04 /* Write Disable */
323617 +#define SPI_CMD_RDID 0x9F /* Read Identification */
323619 +#define SPI_CMD_GET_FEATURES 0x0F /* Get Features */
323620 +#define SPI_CMD_SET_FEATURE 0x1F /* Set Feature */
323622 +#define SPI_CMD_PAGE_READ 0x13 /* Page Read to Cache */
323624 +#define SPI_CMD_RESET 0xff /* Reset the device */
323634 +#define HIFMC100_ECC_ERR_NUM0_BUF0 0xc0
323636 +#define GET_ECC_ERR_NUM(_i, _reg) (((_reg) >> ((_i) * 8)) & 0xff)
323640 +#define REG_CNT_BLOCK_NUM_MASK 0x3ff
323643 +#define REG_CNT_PAGE_NUM_MASK 0x3f
323648 +#define HIFMC100_ADDR_CYCLE_MASK 0x2
323649 +#define OP_STYPE_NONE 0x0
323650 +#define OP_STYPE_READ 0x01
323651 +#define OP_STYPE_WRITE 0x02
323652 +#define OP_STYPE_ERASE 0x04
323702 +#define BBP_LAST_PAGE 0x01
323703 +#define BBP_FIRST_PAGE 0x02
323766 +#define HIFMC_BAD_BLOCK_POS 0
323804 @@ -0,0 +1,247 @@
323851 + host->offset = 0;
323852 + memset((unsigned char *)(chip->IO_ADDR_R), 0, 0x10);
323856 + if (nand_maf_id == 0x00 || nand_maf_id == 0xff) {
323861 + return 0;
323866 + int result = 0;
323872 + for (cs = 0; chip_num && (cs < HIFMC_MAX_CHIP_NUM); cs++) {
323895 + result = 0;
323904 + int result = 0;
323925 + memset((char *)host, 0, len);
323940 + memset((char *)host->iobase, 0xff, fmc->dma_len);
323976 + result = mtd_device_register(mtd, NULL, 0);
323979 + return 0;
324001 + return 0;
324014 + return 0;
324025 + return 0;
324057 @@ -0,0 +1,313 @@
324121 + return 0;
324181 + return 0;
324185 + Read status[C0H]:[0]bit OIP, judge whether the device is busy or not
324213 + return 0;
324249 + return 0;
324294 + return 0;
324313 + return 0;
324317 + Send set features cmd to SPI Nand, feature[B0H]:[0]bit QE would be set
324376 @@ -0,0 +1,2457 @@
324454 +SET_WRITE_STD(0, 256, 24);
324455 +SET_WRITE_STD(0, 256, 75);
324456 +SET_WRITE_STD(0, 256, 80);
324457 +SET_WRITE_STD(0, 256, 100);
324458 +SET_WRITE_STD(0, 256, 104);
324459 +SET_WRITE_STD(0, 256, 133);
324461 +SET_WRITE_QUAD(0, 256, 80);
324462 +SET_WRITE_QUAD(0, 256, 100);
324463 +SET_WRITE_QUAD(0, 256, 104);
324464 +SET_WRITE_QUAD(0, 256, 108);
324465 +SET_WRITE_QUAD(0, 256, 120);
324466 +SET_WRITE_QUAD(0, 256, 133);
324468 +SET_ERASE_SECTOR_128K(0, _128K, 24);
324469 +SET_ERASE_SECTOR_128K(0, _128K, 75);
324470 +SET_ERASE_SECTOR_128K(0, _128K, 80);
324471 +SET_ERASE_SECTOR_128K(0, _128K, 104);
324472 +SET_ERASE_SECTOR_128K(0, _128K, 133);
324474 +SET_ERASE_SECTOR_256K(0, _256K, 24);
324475 +SET_ERASE_SECTOR_256K(0, _256K, 75);
324476 +SET_ERASE_SECTOR_256K(0, _256K, 80);
324477 +SET_ERASE_SECTOR_256K(0, _256K, 100);
324478 +SET_ERASE_SECTOR_256K(0, _256K, 104);
324479 +SET_ERASE_SECTOR_256K(0, _256K, 133);
324554 + .id = {0x2C, 0x14},
324568 + 0
324571 + &WRITE_STD(0, 256, 80),
324572 + &WRITE_QUAD(0, 256, 80),
324573 + 0
324576 + &ERASE_SECTOR_128K(0, _128K, 80),
324577 + 0
324585 + .id = {0x2C, 0x15},
324599 + 0
324602 + &WRITE_STD(0, 256, 80),
324603 + &WRITE_QUAD(0, 256, 80),
324604 + 0
324607 + &ERASE_SECTOR_128K(0, _128K, 80),
324608 + 0
324616 + .id = {0x2C, 0x24},
324630 + 0
324633 + &WRITE_STD(0, 256, 80),
324634 + &WRITE_QUAD(0, 256, 108),
324635 + 0
324638 + &ERASE_SECTOR_128K(0, _128K, 80),
324639 + 0
324647 + .id = {0x2C, 0x25},
324661 + 0
324664 + &WRITE_STD(0, 256, 80),
324665 + &WRITE_QUAD(0, 256, 80),
324666 + 0
324669 + &ERASE_SECTOR_128K(0, _128K, 80),
324670 + 0
324678 + .id = {0x2C, 0x36},
324692 + 0
324695 + &WRITE_STD(0, 256, 80),
324696 + &WRITE_QUAD(0, 256, 108),
324697 + 0
324700 + &ERASE_SECTOR_128K(0, _128K, 80),
324701 + 0
324709 + .id = {0xC8, 0x20},
324721 + 0
324724 + &WRITE_STD(0, 256, 24),
324725 + &WRITE_QUAD(0, 256, 104),
324726 + 0
324729 + &ERASE_SECTOR_128K(0, _128K, 24),
324730 + 0
324738 + .id = {0xC8, 0x21},
324750 + 0
324753 + &WRITE_STD(0, 256, 24),
324754 + &WRITE_QUAD(0, 256, 104),
324755 + 0
324758 + &ERASE_SECTOR_128K(0, _128K, 24),
324759 + 0
324767 + .id = {0xc8, 0x51},
324779 + 0
324782 + &WRITE_STD(0, 256, 133),
324783 + &WRITE_QUAD(0, 256, 133),
324784 + 0
324787 + &ERASE_SECTOR_128K(0, _128K, 133),
324788 + 0
324796 + .id = {0xC8, 0x01, 0X7F},
324808 + 0
324811 + &WRITE_STD(0, 256, 104),
324812 + &WRITE_QUAD(0, 256, 104),
324813 + 0
324816 + &ERASE_SECTOR_128K(0, _128K, 104),
324817 + 0
324825 + .id = {0xc8, 0xf1},
324839 + 0
324842 + &WRITE_STD(0, 256, 24),
324843 + &WRITE_QUAD(0, 256, 120),
324844 + 0
324847 + &ERASE_SECTOR_128K(0, _128K, 24),
324848 + 0
324856 + .id = {0xc8, 0x41},
324868 + 0
324871 + &WRITE_STD(0, 256, 24),
324872 + &WRITE_QUAD(0, 256, 104),
324873 + 0
324876 + &ERASE_SECTOR_128K(0, _128K, 104),
324877 + 0
324885 + .id = {0xc8, 0xd9},
324899 + 0
324902 + &WRITE_STD(0, 256, 104),
324903 + &WRITE_QUAD(0, 256, 120),
324904 + 0
324907 + &ERASE_SECTOR_128K(0, _128K, 104),
324908 + 0
324916 + .id = {0xc8, 0xc1},
324930 + 0
324933 + &WRITE_STD(0, 256, 24),
324934 + &WRITE_QUAD(0, 256, 120),
324935 + 0
324938 + &ERASE_SECTOR_128K(0, _128K, 24),
324939 + 0
324947 + .id = {0xc8, 0xd1},
324961 + 0
324964 + &WRITE_STD(0, 256, 24),
324965 + &WRITE_QUAD(0, 256, 120),
324966 + 0
324969 + &ERASE_SECTOR_128K(0, _128K, 24),
324970 + 0
324978 + .id = {0xc8, 0xf2},
324992 + 0
324995 + &WRITE_STD(0, 256, 24),
324996 + &WRITE_QUAD(0, 256, 120),
324997 + 0
325000 + &ERASE_SECTOR_128K(0, _128K, 24),
325001 + 0
325009 + .id = {0xc8, 0xd2},
325023 + 0
325026 + &WRITE_STD(0, 256, 24),
325027 + &WRITE_QUAD(0, 256, 120),
325028 + 0
325031 + &ERASE_SECTOR_128K(0, _128K, 24),
325032 + 0
325040 + .id = {0xc8, 0x52},
325054 + 0
325057 + &WRITE_STD(0, 256, 104),
325058 + &WRITE_QUAD(0, 256, 120),
325059 + 0
325062 + &ERASE_SECTOR_128K(0, _128K, 104),
325063 + 0
325071 + .id = {0xc8, 0x42},
325085 + 0
325088 + &WRITE_STD(0, 256, 104),
325089 + &WRITE_QUAD(0, 256, 104),
325090 + 0
325093 + &ERASE_SECTOR_128K(0, _128K, 104),
325094 + 0
325102 + .id = {0xc8, 0xf4},
325116 + 0
325119 + &WRITE_STD(0, 256, 24),
325120 + &WRITE_QUAD(0, 256, 120),
325121 + 0
325124 + &ERASE_SECTOR_128K(0, _128K, 24),
325125 + 0
325133 + .id = {0xc8, 0xd4},
325147 + 0
325150 + &WRITE_STD(0, 256, 24),
325151 + &WRITE_QUAD(0, 256, 120),
325152 + 0
325155 + &ERASE_SECTOR_256K(0, _256K, 24),
325156 + 0
325164 + .id = {0xc8, 0x55},
325178 + 0
325181 + &WRITE_STD(0, 256, 24), /* 24MHz */
325182 + &WRITE_QUAD(0, 256, 104), /* 104MHz */
325183 + 0
325186 + &ERASE_SECTOR_128K(0, _128K, 104), /* 104MHz */
325187 + 0
325195 + .id = {0xc8, 0xc1},
325209 + 0
325212 + &WRITE_STD(0, 256, 24),
325213 + &WRITE_QUAD(0, 256, 104),
325214 + 0
325217 + &ERASE_SECTOR_128K(0, _128K, 24),
325218 + 0
325226 + .id = {0xc8, 0xc2},
325240 + 0
325243 + &WRITE_STD(0, 256, 24),
325244 + &WRITE_QUAD(0, 256, 104),
325245 + 0
325248 + &ERASE_SECTOR_128K(0, _128K, 24),
325249 + 0
325256 + .id = {0xc8, 0x45},
325270 + 0
325273 + &WRITE_STD(0, 256, 80),
325274 + &WRITE_QUAD(0, 256, 80),
325275 + 0
325278 + &ERASE_SECTOR_128K(0, _128K, 80),
325279 + 0
325286 + .id = {0xc8, 0xe4},
325300 + 0
325303 + &WRITE_STD(0, 256, 24),
325304 + &WRITE_QUAD(0, 256, 104),
325305 + 0
325308 + &ERASE_SECTOR_256K(0, _256K, 24),
325309 + 0
325317 + .id = {0xef, 0xbf, 0x22},
325331 + 0
325334 + &WRITE_STD(0, 256, 104),
325335 + &WRITE_QUAD(0, 256, 104),
325336 + 0
325339 + &ERASE_SECTOR_128K(0, _128K, 104),
325340 + 0
325348 + .id = {0xc8, 0xc4},
325362 + 0
325365 + &WRITE_STD(0, 256, 24),
325366 + &WRITE_QUAD(0, 256, 120),
325367 + 0
325370 + &ERASE_SECTOR_256K(0, _256K, 24),
325371 + 0
325379 + .id = {0xef, 0xaa, 0x21},
325393 + 0
325396 + &WRITE_STD(0, 256, 24),
325397 + &WRITE_QUAD(0, 256, 104),
325398 + 0
325401 + &ERASE_SECTOR_128K(0, _128K, 24),
325402 + 0
325410 + .id = {0xef, 0xba, 0x21},
325424 + 0
325427 + &WRITE_STD(0, 256, 24),
325428 + &WRITE_QUAD(0, 256, 80),
325429 + 0
325432 + &ERASE_SECTOR_128K(0, _128K, 24),
325433 + 0
325441 + .id = {0x9b, 0x12},
325452 + 0
325455 + &WRITE_STD(0, 256, 24),
325456 + &WRITE_QUAD(0, 256, 104),
325457 + 0
325460 + &ERASE_SECTOR_128K(0, _128K, 24),
325461 + 0
325469 + .id = {0xc2, 0x12},
325480 + 0
325483 + &WRITE_STD(0, 256, 24),
325484 + &WRITE_QUAD(0, 256, 104),
325485 + 0
325488 + &ERASE_SECTOR_128K(0, _128K, 24),
325489 + 0
325497 + .id = {0xc2, 0x90},
325508 + 0
325511 + &WRITE_STD(0, 256, 24),
325512 + &WRITE_QUAD(0, 256, 104),
325513 + 0
325516 + &ERASE_SECTOR_128K(0, _128K, 104),
325517 + 0
325525 + .id = {0xc2, 0x22},
325536 + 0
325539 + &WRITE_STD(0, 256, 24),
325540 + &WRITE_QUAD(0, 256, 104),
325541 + 0
325544 + &ERASE_SECTOR_128K(0, _128K, 24),
325545 + 0
325553 + .id = {0xc2, 0x20},
325564 + 0
325567 + &WRITE_STD(0, 256, 24),
325568 + &WRITE_QUAD(0, 256, 104),
325569 + 0
325572 + &ERASE_SECTOR_128K(0, _128K, 24),
325573 + 0
325581 + .id = {0xc2, 0xa0},
325592 + 0
325595 + &WRITE_STD(0, 256, 24),
325596 + &WRITE_QUAD(0, 256, 104),
325597 + 0
325600 + &ERASE_SECTOR_128K(0, _128K, 104),
325601 + 0
325609 + .id = {0xa1, 0xe1},
325623 + 0
325626 + &WRITE_STD(0, 256, 24),
325627 + &WRITE_QUAD(0, 256, 108),
325628 + 0
325631 + &ERASE_SECTOR_128K(0, _128K, 24),
325632 + 0
325640 + .id = {0xa1, 0xe2},
325654 + 0
325657 + &WRITE_STD(0, 256, 24),
325658 + &WRITE_QUAD(0, 256, 108),
325659 + 0
325662 + &ERASE_SECTOR_128K(0, _128K, 24),
325663 + 0
325671 + .id = {0xc1, 0x51},
325685 + 0
325688 + &WRITE_STD(0, 256, 24),
325689 + &WRITE_QUAD(0, 256, 80),
325690 + 0
325693 + &ERASE_SECTOR_128K(0, _128K, 24),
325694 + 0
325702 + .id = {0xc1, 0x52},
325716 + 0
325719 + &WRITE_STD(0, 256, 24),
325720 + &WRITE_QUAD(0, 256, 80),
325721 + 0
325724 + &ERASE_SECTOR_128K(0, _128K, 24),
325725 + 0
325733 + .id = {0x98, 0xc2},
325745 + 0
325748 + &WRITE_STD(0, 256, 104),
325749 + 0
325752 + &ERASE_SECTOR_128K(0, _128K, 104),
325753 + 0
325760 + .id = {0x98, 0xe2, 0x40},
325772 + 0
325775 + &WRITE_STD(0, 256, 133),
325776 + &WRITE_QUAD(0, 256, 133),
325777 + 0
325780 + &ERASE_SECTOR_128K(0, _128K, 133),
325781 + 0
325788 + .id = {0x98, 0xb2},
325800 + 0
325803 + &WRITE_STD(0, 256, 104),
325804 + 0
325807 + &ERASE_SECTOR_128K(0, _128K, 104),
325808 + 0
325816 + .id = {0x98, 0xD2, 0x40},
325828 + 0
325831 + &WRITE_STD(0, 256, 133),
325832 + &WRITE_QUAD(0, 256, 133),
325833 + 0
325836 + &ERASE_SECTOR_128K(0, _128K, 133),
325837 + 0
325845 + .id = {0x98, 0xcb},
325857 + 0
325860 + &WRITE_STD(0, 256, 104),
325861 + 0
325864 + &ERASE_SECTOR_128K(0, _128K, 104),
325865 + 0
325873 + .id = {0x98, 0xeb, 0x40},
325885 + 0
325888 + &WRITE_STD(0, 256, 133),
325889 + &WRITE_QUAD(0, 256, 133),
325890 + 0
325893 + &ERASE_SECTOR_128K(0, _128K, 133),
325894 + 0
325902 + .id = {0x98, 0xbb},
325914 + 0
325917 + &WRITE_STD(0, 256, 75),
325918 + 0
325921 + &ERASE_SECTOR_128K(0, _128K, 75),
325922 + 0
325930 + .id = {0x98, 0xdb, 0x40},
325942 + 0
325945 + &WRITE_STD(0, 256, 133),
325946 + &WRITE_QUAD(0, 256, 133),
325947 + 0
325950 + &ERASE_SECTOR_128K(0, _128K, 133),
325951 + 0
325959 + .id = {0x98, 0xcd},
325971 + 0
325974 + &WRITE_STD(0, 256, 104),
325975 + 0
325978 + &ERASE_SECTOR_256K(0, _256K, 104),
325979 + 0
325987 + .id = {0x98, 0xed, 0x51},
325999 + 0
326002 + &WRITE_STD(0, 256, 133),
326003 + &WRITE_QUAD(0, 256, 133),
326004 + 0
326007 + &ERASE_SECTOR_256K(0, _256K, 133),
326008 + 0
326016 + .id = {0x98, 0xbd},
326028 + 0
326031 + &WRITE_STD(0, 256, 75),
326032 + 0
326035 + &ERASE_SECTOR_256K(0, _256K, 75),
326036 + 0
326044 + .id = {0x98, 0xdd, 0x51},
326056 + 0
326059 + &WRITE_STD(0, 256, 133), /* 133MHz */
326060 + &WRITE_QUAD(0, 256, 133), /* 133MHz */
326061 + 0
326064 + &ERASE_SECTOR_256K(0, _256K, 133), /* 133MHz */
326065 + 0
326073 + .id = {0x98, 0xd4, 0x51},
326085 + 0
326088 + &WRITE_STD(0, 256, 133), /* 133MHz */
326089 + &WRITE_QUAD(0, 256, 133), /* 133MHz */
326090 + 0
326093 + &ERASE_SECTOR_256K(0, _256K, 133), /* 133MHz */
326094 + 0
326102 + .id = {0xc9, 0x51},
326116 + 0
326119 + &WRITE_STD(0, 256, 80),
326120 + &WRITE_QUAD(0, 256, 80),
326121 + 0
326124 + &ERASE_SECTOR_128K(0, _128K, 80),
326125 + 0
326133 + .id = {0xc9, 0x52},
326147 + 0
326150 + &WRITE_STD(0, 256, 80),
326151 + &WRITE_QUAD(0, 256, 80),
326152 + 0
326155 + &ERASE_SECTOR_128K(0, _128K, 80),
326156 + 0
326164 + .id = {0xc9, 0xd4},
326178 + 0
326181 + &WRITE_STD(0, 256, 80),
326182 + &WRITE_QUAD(0, 256, 80),
326183 + 0
326186 + &ERASE_SECTOR_256K(0, _256K, 80),
326187 + 0
326195 + .id = {0xe5, 0x71},
326207 + 0
326210 + &WRITE_STD(0, 256, 80),
326211 + &WRITE_QUAD(0, 256, 104),
326212 + 0
326215 + &ERASE_SECTOR_128K(0, _128K, 104),
326216 + 0
326224 + .id = {0x0B, 0xF1},
326238 + 0
326241 + &WRITE_STD(0, 256, 80),
326242 + &WRITE_QUAD(0, 256, 80),
326243 + 0
326246 + &ERASE_SECTOR_128K(0, _128K, 80),
326247 + 0
326255 + .id = {0xD5, 0x8D},
326269 + 0
326272 + &WRITE_STD(0, 256, 100),
326273 + &WRITE_QUAD(0, 256, 100),
326274 + 0
326277 + &ERASE_SECTOR_256K(0, _256K, 100),
326278 + 0
326286 + .id = {0xD5, 0x8C},
326300 + 0
326303 + &WRITE_STD(0, 256, 100),
326304 + &WRITE_QUAD(0, 256, 100),
326305 + 0
326308 + &ERASE_SECTOR_256K(0, _256K, 100),
326309 + 0
326317 + .id = {0xd5, 0x81},
326331 + 0
326334 + &WRITE_STD(0, 256, 80),
326335 + &WRITE_QUAD(0, 256, 104),
326336 + 0
326339 + &ERASE_SECTOR_128K(0, _128K, 104),
326340 + 0
326348 + .id = {0xd5, 0x22},
326362 + 0
326365 + &WRITE_STD(0, 256, 104),
326366 + &WRITE_QUAD(0, 256, 120),
326367 + 0
326370 + &ERASE_SECTOR_128K(0, _128K, 104),
326371 + 0
326379 + .id = {0x2C, 0x35},
326391 + 0
326394 + &WRITE_STD(0, 256, 80),
326395 + &WRITE_QUAD(0, 256, 80),
326396 + 0
326399 + &ERASE_SECTOR_256K(0, _256K, 80),
326400 + 0
326408 + .id = {0xe5, 0x72},
326420 + 0
326423 + &WRITE_STD(0, 256, 80),
326424 + &WRITE_QUAD(0, 256, 104),
326425 + 0
326428 + &ERASE_SECTOR_128K(0, _128K, 104),
326429 + 0
326437 + .id = {0xa1, 0xa1},
326451 + 0
326454 + &WRITE_STD(0, 256, 104), /* 104MHz */
326455 + &WRITE_QUAD(0, 256, 104), /* 104MHz */
326456 + 0
326459 + &ERASE_SECTOR_128K(0, _128K, 104), /* 104MHz */
326460 + 0
326468 + .id = {0xa1, 0xe4},
326482 + 0
326485 + &WRITE_STD(0, 256, 104), /* 104MHz */
326486 + &WRITE_QUAD(0, 256, 104), /* 104MHz */
326487 + 0
326490 + &ERASE_SECTOR_128K(0, _128K, 104), /* 104MHz */
326491 + 0
326496 + { .id_len = 0, },
326503 + int ix = 0;
326523 + spiop_erase->size = 0;
326524 + for (ix = 0; ix < MAX_SPI_OP; ix++) {
326547 + 0, 0,
326552 + 0, 0,
326558 + for (ix = 0; iftype_write[ix]; ix += 2) {
326567 + for (ix = 0; iftype_read[ix]; ix += 2) {
326697 + int len = 0;
326707 + host->cmd_op.cs, id[0], id[1]);
326839 @@ -0,0 +1,50 @@
326869 + int "the width of Read/Write HIGH Hold Time (0 to 15)"
326870 + range 0 15
326876 + int "the Read pulse width (0 to 15)"
326877 + range 0 15
326883 + int "the Write pulse width (0 to 15)"
326884 + range 0 15
326895 @@ -0,0 +1,26 @@
326927 @@ -0,0 +1,1170 @@
327040 + if (*host->bbm != 0xFF && *host->bbm != 0x00) {
327042 + "page: 0x%08x, mark: 0x%02x,\n",
327052 + reg = host->addr_value[0] & 0xffff0000;
327060 + *host->epm = 0x0000;
327074 + if ((host->addr_value[0] == host->cache_addr_value[0]) &&
327077 + host->addr_value[1], host->addr_value[0]);
327081 + host->page_status = 0;
327097 + reg = host->addr_value[0] & 0xffff0000;
327111 + host->cache_addr_value[0] = host->addr_value[0];
327127 + reg = host->addr_value[0];
327159 + unsigned int change = 0;
327232 + reg = 0;
327248 + host->addr_cycle = 0x0;
327284 + unsigned char value = 0;
327292 + host->cmd_op.l_cmd = 0;
327367 + if (err_num == 0xff) {
327432 + if (chipselect < 0) {
327484 + unsigned int addr_value = 0;
327485 + unsigned int addr_offset = 0;
327488 + host->addr_cycle = 0x0;
327489 + host->addr_value[0] = 0x0;
327490 + host->addr_value[1] = 0x0;
327501 + (((unsigned int)dat & 0xff) << addr_offset);
327507 + cmd = (unsigned int)dat & 0xff;
327511 + host->offset = 0;
327516 + is_cache_invalid = 0;
327517 + if (host->addr_value[0] == host->pagesize) {
327529 + memset((u_char *)(chip->IO_ADDR_R), 0, MAX_NAND_ID_LEN);
327561 + host->offset = 0x0;
327562 + host->column = (host->addr_value[0] & 0xffff);
327567 + host->cache_addr_value[0] = ~0;
327568 + host->cache_addr_value[1] = ~0;
327575 + return 0x1;
327580 + * 'host->epm' only use the first oobfree[0] field, it looks very simple, But...
327592 + return 0;
327605 + return 0;
327624 + return 0;
327637 + return 0;
327654 + return 0;
327667 + return 0;
327680 + {NAND_PAGE_16K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
327685 + {NAND_PAGE_8K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
327692 + {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
327699 + {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
327701 + {0, 0, 0, 0, NULL},
327706 + * 0 - This NAND NOT support randomizer
327719 + return 0;
327781 + unsigned int block_reg = 0;
327865 + struct mtd_oob_region hifmc_oobregion = {0, 0};
327876 + memset(host->buffer, 0xff, buffer_len);
327882 + info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
327921 + /* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
327935 + unsigned int shift = 0;
327950 + return 0;
327958 + memset((char *)chip->IO_ADDR_R, 0xff, host->dma_len);
328020 + host->addr_cycle = 0;
328021 + host->addr_value[0] = 0;
328022 + host->addr_value[1] = 0;
328023 + host->cache_addr_value[0] = ~0;
328024 + host->cache_addr_value[1] = ~0;
328049 + return 0;
328086 + return 0;
328103 @@ -0,0 +1,151 @@
328138 +#define HIFMC100_ECC_ERR_NUM0_BUF0 0xc0
328139 +#define HIFMC100_ECC_ERR_NUM1_BUF0 0xc4
328140 +#define HIFMC100_ECC_ERR_NUM0_BUF1 0xc8
328141 +#define HIFMC100_ECC_ERR_NUM1_BUF1 0xcc
328143 +#define GET_ECC_ERR_NUM(_i, _reg) (((_reg) >> ((_i) * 8)) & 0xff)
328155 +#define REG_CNT_BLOCK_NUM_MASK 0x3ff
328158 +#define REG_CNT_PAGE_NUM_MASK 0x3f
328162 +#define HIFMC100_ADDR_CYCLE_MASK 0x4
328214 +#define HIFMC100_BAD_BLOCK_POS 0
328219 +#define HIFMC100_PS_UC_ECC 0x01 /* page has ecc error */
328220 +#define HIFMC100_PS_BAD_BLOCK 0x02 /* bad block */
328221 +#define HIFMC100_PS_EMPTY_PAGE 0x04 /* page is empty */
328222 +#define HIFMC100_PS_EPM_ERROR 0x0100 /* empty page mark word has error. */
328223 +#define HIFMC100_PS_BBM_ERROR 0x0200 /* bad block mark word has error. */
328260 @@ -0,0 +1,180 @@
328295 + int result = 0;
328299 + int nr_parts = 0;
328316 + memset((char *)host, 0, len);
328356 + return (result == 1) ? -ENODEV : 0;
328371 + return 0;
328382 + return 0;
328395 + return 0;
328405 + return 0;
328409 + for (cs = 0; cs < chip->numchips; cs++) {
328414 + return 0;
328446 @@ -0,0 +1,72 @@
328524 @@ -0,0 +1,982 @@
328570 +#define BBP_LAST_PAGE 0x01
328571 +#define BBP_FIRST_PAGE 0x02
328584 + int pagesizes[] = {_2K, _4K, _8K, 0};
328585 + int oobsizes[] = {128, 224, 448, 0, 0, 0, 0, 0};
328586 + int blocksizes[] = {_128K, _256K, _512K, _768K, _1M, _2M, 0, 0};
328588 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
328589 + int oobtype = (((id[3] >> 2) & 0x03) | ((id[3] >> 4) & 0x04));
328591 + type->options = 0;
328592 + type->pagesize = pagesizes[(id[3] & 0x03)];
328604 + int pagesizes[] = {_2K, _4K, _8K, 0};
328605 + int oobsizes[] = {0, 128, 218, 400, 436, 0, 0, 0};
328606 + int blocksizes[] = {_128K, _256K, _512K, _1M, 0, 0, 0, 0};
328608 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
328609 + int oobtype = (((id[3] >> 4) & 0x04) | ((id[3] >> 2) & 0x03));
328611 + type->options = 0;
328612 + type->pagesize = pagesizes[(id[3] & 0x03)];
328691 + .id = {0xC2, 0xAA, 0x90, 0x15, 0x06},
328698 + .options = 0,
328701 + .flags = 0,
328708 + .id = {0x01, 0xDA, 0x90, 0x95, 0x46, 0x00, 0x00, 0x00},
328715 + .options = 0,
328718 + .flags = 0,
328723 + .id = {0x01, 0xDC, 0x90, 0x95, 0x56, 0x00, 0x00, 0x00},
328730 + .options = 0,
328733 + .flags = 0,
328738 + .id = {0x01, 0xAA, 0x90, 0x15, 0x46, 0x00, 0x00, 0x00},
328745 + .options = 0,
328748 + .flags = 0,
328753 + .id = {0x01, 0xAC, 0x90, 0x15, 0x56, 0x00, 0x00, 0x00},
328760 + .options = 0,
328763 + .flags = 0,
328770 + .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
328777 + .options = 0,
328784 + .id = {0x2C, 0x44, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
328791 + .options = 0,
328798 + .id = {0x2C, 0x38, 0x00, 0x26, 0x85, 0x00, 0x00, 0x00},
328805 + .options = 0,
328808 + .flags = 0,
328812 + .id = {0x2C, 0x48, 0x04, 0x46, 0x85, 0x00, 0x00, 0x00},
328819 + .options = 0,
328822 + .flags = 0,
328826 + .id = {0x2C, 0x48, 0x04, 0x4A, 0xA5, 0x00, 0x00, 0x00},
328833 + .options = 0,
328836 + .flags = 0,
328840 + .id = {0x2C, 0x68, 0x04, 0x4A, 0xA9, 0x00, 0x00, 0x00},
328847 + .options = 0,
328850 + .flags = 0,
328854 + .id = {0x2C, 0x88, 0x04, 0x4B, 0xA9, 0x00, 0x00, 0x00},
328861 + .options = 0,
328868 + .id = {0x2C, 0xA8, 0x05, 0xCB, 0xA9, 0x00, 0x00, 0x00},
328875 + .options = 0,
328882 + .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
328889 + .options = 0,
328892 + .flags = 0,
328896 + .id = {0x2C, 0xD3, 0x90, 0xA6, 0x64, 0x00, 0x00, 0x00},
328903 + .options = 0,
328906 + .flags = 0,
328910 + .id = {0x2C, 0xDC, 0x90, 0xA6, 0x54, 0x00, 0x00, 0x00},
328917 + .options = 0,
328920 + .flags = 0,
328924 + .id = {0x2C, 0xDA, 0x90, 0x95, 0x04, 0x00, 0x00, 0x00},
328931 + .options = 0,
328934 + .flags = 0,
328938 + .id = {0x2C, 0xDA, 0x90, 0x95, 0x06, 0x00, 0x00, 0x00},
328945 + .options = 0,
328948 + .flags = 0,
328952 + .id = {0x2C, 0x48, 0x00, 0x26, 0xA9, 0x00, 0x00, 0x00},
328959 + .options = 0,
328962 + .flags = 0,
328969 + .id = {0x98, 0xD5, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
328976 + .options = 0,
328979 + .flags = 0,
328983 + .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
328990 + .options = 0,
328993 + .flags = 0,
328997 + .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x56, 0x08, 0x00},
329004 + .options = 0,
329011 + .id = {0x98, 0xDE, 0x94, 0x82, 0x76, 0x00, 0x00, 0x00},
329018 + .options = 0,
329021 + .flags = 0,
329025 + .id = {0x98, 0xDE, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
329032 + .options = 0,
329039 + .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
329046 + .options = 0,
329053 + .id = {0x98, 0xF1, 0x80, 0x15, 0x72, 0x00, 0x00, 0x00},
329060 + .options = 0,
329068 + .flags = 0,
329072 + .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x16, 0x08, 0x00},
329079 + .options = 0,
329082 + .flags = 0,
329086 + .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x14, 0x03, 0x00},
329093 + .options = 0,
329096 + .flags = 0,
329100 + .id = {0x98, 0xD3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08},
329107 + .options = 0,
329110 + .flags = 0,
329114 + .id = {0x98, 0xD3, 0x91, 0x26, 0x76, 0x16, 0x08, 0x00},
329121 + .options = 0,
329124 + .flags = 0,
329128 + .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00},
329135 + .options = 0,
329138 + .flags = 0,
329142 + .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08},
329149 + .options = 0,
329152 + .flags = 0,
329156 + .id = {0x98, 0xDC, 0x91, 0x15, 0x76},
329163 + .options = 0,
329166 + .flags = 0,
329171 + .id = {0x98, 0xD7, 0x98, 0x92, 0x72, 0x57, 0x08, 0x10},
329178 + .options = 0,
329186 + .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x50, 0x08, 0x04},
329193 + .options = 0,
329200 + .id = {0x98, 0xDE, 0x94, 0x93, 0x76, 0x50},
329207 + .options = 0,
329215 + .id = {0xEC, 0xD7, 0xD5, 0x29, 0x38, 0x41, 0x00, 0x00},
329221 + .flags = 0,
329225 + .id = {0xEC, 0xD5, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
329231 + .flags = 0,
329235 + .id = {0xEC, 0xD7, 0xC5, 0x72, 0x54, 0x42, 0x00, 0x00},
329241 + .flags = 0,
329245 + .id = {0xEC, 0xD3, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
329251 + .flags = 0,
329255 + .id = {0xEC, 0xD5, 0x94, 0x76, 0x54, 0x43, 0x00, 0x00},
329262 + .options = 0,
329265 + .flags = 0,
329269 + .id = {0xEC, 0xD7, 0x55, 0xB6, 0x78, 0x00, 0x00, 0x00},
329276 + .options = 0,
329279 + .flags = 0,
329283 + .id = {0xEC, 0xD7, 0x94, 0x7A, 0x54, 0x43, 0x00, 0x00},
329290 + .options = 0,
329297 + .id = {0xEC, 0xD7, 0x94, 0x7E, 0x64, 0x44, 0x00, 0x00},
329304 + .options = 0,
329313 + .id = { 0xAD, 0xD5, 0x94, 0x25, 0x44, 0x41, },
329319 + .flags = 0,
329323 + .id = { 0xAD, 0xD5, 0x94, 0x9A, 0x74, 0x42, },
329329 + .flags = 0,
329333 + .id = { 0xAD, 0xD7, 0x94, 0x9A, 0x74, 0x42, },
329339 + .flags = 0,
329343 + .id = { 0xAD, 0xD7, 0x94, 0xDA, 0x74, 0xC3, },
329350 + .options = 0,
329357 + .id = { 0xAD, 0xDE, 0x94, 0xDA, 0x74, 0xC4, },
329364 + .options = 0,
329371 + .id = { 0xAD, 0xD7, 0x94, 0x91, 0x60, 0x44, },
329378 + .options = 0,
329387 + .id = { 0xC8, 0xD5, 0x14, 0x29, 0x34, 0x01, },
329394 + .options = 0,
329397 + .flags = 0,
329405 + .id = { 0xC8, 0xD3, 0x90, 0x19, 0x34, 0x01, },
329412 + .options = 0,
329415 + .flags = 0,
329419 + .id = { 0x7F, 0x7F, 0x7F, 0x7F, 0xC8, 0xDA, 0x00, 0x15, },
329426 + .options = 0,
329429 + .flags = 0,
329431 + {{0}, 0, 0, 0, 0, 0, 0, 0, 0},
329446 + pr_info("Nand ID: %#X %#X %#X %#X %#X %#X %#X %#X\n", id[0], id[1],
329492 + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
329525 @@ -0,0 +1,237 @@
329587 + return ecctype_string[(ecctype & 0x07)];
329610 + return pagesize_str[(pagetype & 0x07)];
329625 + _512B, _2K, _4K, _8K, _16K, 0, 0, 0
329627 + return pagesize[(pagetype & 0x07)];
329652 + int ret = 0;
329655 + return 0;
329657 + if (n > 0xFFFF)
329658 + loop = n > 0xFFFFFF ? 32 : 24;
329660 + loop = n > 0xFF ? 16 : 8;
329662 + while (loop-- > 0 && n) {
329670 +#define et_ecc_none 0x00
329671 +#define et_ecc_4bit 0x02
329672 +#define et_ecc_8bit 0x03
329673 +#define et_ecc_24bit1k 0x04
329674 +#define et_ecc_40bit1k 0x05
329675 +#define et_ecc_64bit1k 0x06
329769 @@ -0,0 +1,281 @@
329797 +#define HINFC_VER_300 (0x300)
329798 +#define HINFC_VER_301 (0x301)
329799 +#define HINFC_VER_310 (0x310)
329800 +#define HINFC_VER_504 (0x504)
329801 +#define HINFC_VER_505 (0x505)
329802 +#define HINFC_VER_600 (0x600)
329803 +#define HINFC_VER_610 (0x610)
329804 +#define HINFC_VER_620 (0x620)
329806 +#define HISNFC_VER_100 (0x400)
329808 +#define NAND_PAGE_512B 0
329816 +#define NAND_ECC_NONE 0
329817 +#define NAND_ECC_0BIT 0
329843 + et_ecc_none = 0x00,
329844 + et_ecc_1bit = 0x01,
329845 + et_ecc_4bit = 0x02,
329846 + et_ecc_8bit = 0x03,
329847 + et_ecc_24bit1k = 0x04,
329848 + et_ecc_40bit1k = 0x05,
329849 + et_ecc_64bit1k = 0x06,
329853 + pt_pagesize_512 = 0x00,
329854 + pt_pagesize_2K = 0x01,
329855 + pt_pagesize_4K = 0x02,
329856 + pt_pagesize_8K = 0x03,
329857 + pt_pagesize_16K = 0x04,
329872 + ((((_mfr) & 0xFF) << 16) | (((_version) & 0xFF) << 8) \
329873 + | ((_onfi) & 0xFF))
329875 +#define GET_NAND_SYNC_TYPE_MFR(_type) (((_type) >> 16) & 0xFF)
329876 +#define GET_NAND_SYNC_TYPE_VER(_type) (((_type) >> 8) & 0xFF)
329877 +#define GET_NAND_SYNC_TYPE_INF(_type) ((_type) & 0xFF)
329880 + SET_NAND_SYNC_TYPE(NAND_MFR_MICRON, NAND_IS_ONFI, 0x23)
329882 + SET_NAND_SYNC_TYPE(NAND_MFR_MICRON, NAND_IS_ONFI, 0x30)
329884 + SET_NAND_SYNC_TYPE(NAND_MFR_TOSHIBA, 0, 0)
329886 + SET_NAND_SYNC_TYPE(NAND_MFR_SAMSUNG, 0, 0)
329888 +#define NAND_TYPE_TOGGLE_10 SET_NAND_SYNC_TYPE(0, 0, 0x10)
329889 +#define NAND_TYPE_ONFI_30 SET_NAND_SYNC_TYPE(0, NAND_IS_ONFI, 0x30)
329890 +#define NAND_TYPE_ONFI_23 SET_NAND_SYNC_TYPE(0, NAND_IS_ONFI, 0x23)
329923 +#define NANDC_HW_AUTO 0x01
329926 +#define NANDC_CONFIG_DONE 0x02
329928 +#define NANDC_IS_SYNC_BOOT 0x04
329931 +#define NAND_RANDOMIZER 0x10
329933 +#define NAND_IS_ONFI 0x20
329935 +#define NAND_MODE_SYNC_ASYNC 0x40
329937 +#define NAND_MODE_ONLY_SYNC 0x80
329941 + * toggle1.0 interface */
329943 +/* This NAND is only sync mode, toggle2.0 interface */
329950 +#define NAND_RR_NONE 0x00
329951 +#define NAND_RR_HYNIX_BG_BDIE 0x10
329952 +#define NAND_RR_HYNIX_BG_CDIE 0x11
329953 +#define NAND_RR_HYNIX_CG_ADIE 0x12
329954 +#define NAND_RR_MICRON 0x20
329955 +#define NAND_RR_SAMSUNG 0x30
329956 +#define NAND_RR_TOSHIBA_24nm 0x40
329957 +#define NAND_RR_TOSHIBA_19nm 0x41
329975 +#define DISABLE 0
330025 +} while (0)
330054 index 000000000..0fd7db974
330057 @@ -0,0 +1,970 @@
330093 +#define BBP_LAST_PAGE 0x01
330094 +#define BBP_FIRST_PAGE 0x02
330109 + int pagesizes[] = {SZ_2K, SZ_4K, SZ_8K, 0};
330110 + int oobsizes[] = {128, 224, 448, 0, 0, 0, 0, 0};
330112 + (SZ_256K + SZ_512K), SZ_1M, SZ_2M, 0, 0
330115 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
330116 + int oobtype = (((id[3] >> 2) & 0x03) | ((id[3] >> 4) & 0x04));
330118 + type->options = 0;
330119 + type->pagesize = pagesizes[(id[3] & 0x03)];
330133 + int pagesizes[] = {SZ_2K, SZ_4K, SZ_8K, 0};
330134 + int oobsizes[] = {0, 128, 218, 400, 436, 0, 0, 0};
330135 + int blocksizes[] = {SZ_128K, SZ_256K, SZ_512K, SZ_1M, 0, 0, 0, 0};
330137 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
330138 + int oobtype = (((id[3] >> 4) & 0x04) | ((id[3] >> 2) & 0x03));
330140 + type->options = 0;
330141 + type->pagesize = pagesizes[(id[3] & 0x03)];
330220 + .id = {0x01, 0xDA, 0x90, 0x95, 0x46, 0x00, 0x00, 0x00},
330227 + .options = 0,
330230 + .flags = 0,
330235 + .id = {0x01, 0xDC, 0x90, 0x95, 0x56, 0x00, 0x00, 0x00},
330242 + .options = 0,
330245 + .flags = 0,
330251 + .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
330258 + .options = 0,
330265 + .id = {0x2C, 0x44, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
330272 + .options = 0,
330279 + .id = {0x2C, 0x38, 0x00, 0x26, 0x85, 0x00, 0x00, 0x00},
330286 + .options = 0,
330289 + .flags = 0,
330293 + .id = {0x2C, 0x48, 0x04, 0x46, 0x85, 0x00, 0x00, 0x00},
330300 + .options = 0,
330303 + .flags = 0,
330307 + .id = {0x2C, 0x48, 0x04, 0x4A, 0xA5, 0x00, 0x00, 0x00},
330314 + .options = 0,
330317 + .flags = 0,
330321 + .id = {0x2C, 0x68, 0x04, 0x4A, 0xA9, 0x00, 0x00, 0x00},
330328 + .options = 0,
330331 + .flags = 0,
330335 + .id = {0x2C, 0x88, 0x04, 0x4B, 0xA9, 0x00, 0x00, 0x00},
330342 + .options = 0,
330345 + .flags = 0,
330349 + .id = {0x2C, 0xA8, 0x05, 0xCB, 0xA9, 0x00, 0x00, 0x00},
330356 + .options = 0,
330359 + .flags = 0,
330363 + .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
330370 + .options = 0,
330373 + .flags = 0,
330377 + .id = {0x2C, 0xD3, 0x90, 0xA6, 0x64, 0x00, 0x00, 0x00},
330384 + .options = 0,
330387 + .flags = 0,
330391 + .id = {0x2C, 0xDC, 0x90, 0xA6, 0x54, 0x00, 0x00, 0x00},
330398 + .options = 0,
330401 + .flags = 0,
330405 + .id = {0x2C, 0xDA, 0x90, 0x95, 0x04, 0x00, 0x00, 0x00},
330412 + .options = 0,
330415 + .flags = 0,
330419 + .id = {0x2C, 0xDA, 0x90, 0x95, 0x06, 0x00, 0x00, 0x00},
330426 + .options = 0,
330429 + .flags = 0,
330433 + .id = {0x2C, 0x48, 0x00, 0x26, 0xA9, 0x00, 0x00, 0x00},
330440 + .options = 0,
330443 + .flags = 0,
330450 + .id = {0x98, 0xD5, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
330457 + .options = 0,
330460 + .flags = 0,
330464 + .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
330471 + .options = 0,
330474 + .flags = 0,
330478 + .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x56, 0x08, 0x00},
330485 + .options = 0,
330492 + .id = {0x98, 0xDE, 0x94, 0x82, 0x76, 0x00, 0x00, 0x00},
330499 + .options = 0,
330502 + .flags = 0,
330506 + .id = {0x98, 0xDE, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
330513 + .options = 0,
330520 + .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
330527 + .options = 0,
330534 + .id = {0x98, 0xF1, 0x80, 0x15, 0x72, 0x00, 0x00, 0x00},
330541 + .options = 0,
330549 + .flags = 0,
330553 + .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x16, 0x08, 0x00},
330560 + .options = 0,
330563 + .flags = 0,
330567 + .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x14, 0x03, 0x00},
330574 + .options = 0,
330577 + .flags = 0,
330581 + .id = {0x98, 0xD3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08},
330588 + .options = 0,
330591 + .flags = 0,
330595 + .id = {0x98, 0xD3, 0x91, 0x26, 0x76, 0x16, 0x08, 0x00},
330602 + .options = 0,
330605 + .flags = 0,
330609 + .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00},
330616 + .options = 0,
330619 + .flags = 0,
330623 + .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08},
330630 + .options = 0,
330633 + .flags = 0,
330637 + .id = {0x98, 0xDC, 0x91, 0x15, 0x76},
330644 + .options = 0,
330647 + .flags = 0,
330651 + .id = {0x98, 0xD7, 0x98, 0x92, 0x72, 0x57, 0x08, 0x10},
330658 + .options = 0,
330666 + .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x50, 0x08, 0x04},
330673 + .options = 0,
330680 + .id = {0x98, 0xDE, 0x94, 0x93, 0x76, 0x50},
330687 + .options = 0,
330695 + .id = {0xEC, 0xD7, 0xD5, 0x29, 0x38, 0x41, 0x00, 0x00},
330701 + .flags = 0,
330705 + .id = {0xEC, 0xD5, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
330711 + .flags = 0,
330715 + .id = {0xEC, 0xD7, 0xC5, 0x72, 0x54, 0x42, 0x00, 0x00},
330721 + .flags = 0,
330725 + .id = {0xEC, 0xD3, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
330731 + .flags = 0,
330735 + .id = {0xEC, 0xD5, 0x94, 0x76, 0x54, 0x43, 0x00, 0x00},
330742 + .options = 0,
330745 + .flags = 0,
330749 + .id = {0xEC, 0xD7, 0x55, 0xB6, 0x78, 0x00, 0x00, 0x00},
330756 + .options = 0,
330759 + .flags = 0,
330763 + .id = {0xEC, 0xD7, 0x94, 0x7A, 0x54, 0x43, 0x00, 0x00},
330770 + .options = 0,
330777 + .id = {0xEC, 0xD7, 0x94, 0x7E, 0x64, 0x44, 0x00, 0x00},
330784 + .options = 0,
330793 + .id = { 0xAD, 0xD5, 0x94, 0x25, 0x44, 0x41, },
330799 + .flags = 0,
330803 + .id = { 0xAD, 0xD5, 0x94, 0x9A, 0x74, 0x42, },
330809 + .flags = 0,
330813 + .id = { 0xAD, 0xD7, 0x94, 0x9A, 0x74, 0x42, },
330819 + .flags = 0,
330823 + .id = { 0xAD, 0xD7, 0x94, 0xDA, 0x74, 0xC3, },
330830 + .options = 0,
330837 + .id = { 0xAD, 0xDE, 0x94, 0xDA, 0x74, 0xC4, },
330844 + .options = 0,
330851 + .id = { 0xAD, 0xD7, 0x94, 0x91, 0x60, 0x44, },
330858 + .options = 0,
330867 + .id = { 0xC8, 0xD5, 0x14, 0x29, 0x34, 0x01, },
330874 + .options = 0,
330877 + .flags = 0,
330885 + .id = { 0xC8, 0xD3, 0x90, 0x19, 0x34, 0x01, },
330892 + .options = 0,
330895 + .flags = 0,
330899 + .id = { 0x7F, 0x7F, 0x7F, 0x7F, 0xC8, 0xDA, 0x00, 0x15, },
330906 + .options = 0,
330909 + .flags = 0,
330911 + {{0}, 0, 0, 0, 0, 0, 0, 0, 0},
330931 + hinfc_pr_msg("Nand ID: 0x%02X 0x%02X 0x%02X 0x%02X",
330932 + byte[0], byte[1], byte[2], byte[3]);
330933 + hinfc_pr_msg(" 0x%02X 0x%02X 0x%02X 0x%02X\n",
330972 + memset(nand_dev, 0, sizeof(struct nand_dev_t));
331033 @@ -0,0 +1,102 @@
331047 + while (length-- > 0) {
331058 + while (length-- > 0) {
331070 + while (length-- > 0) {
331082 + while (length-- > 0) {
331093 + while (nr_table-- > 0) {
331104 + while (nr_table-- > 0) {
331116 + while (nr_table-- > 0) {
331128 + while (nr_table-- > 0) {
331141 @@ -0,0 +1,51 @@
331168 +#define MATCH_SET_TYPE_REG(_type, _reg) {(_type), (_reg), (void *)0}
331169 +#define MATCH_SET_TYPE_DATA(_type, _data) {(_type), 0, (void *)(_data)}
331207 int oob_required = oob ? 1 : 0;
331213 ops->retlen = 0;
331215 return 0;
331221 + int busw = 0;
331222 + int ret = 0;
331282 return 0;
331305 + {0x0, "Unknown"}
331360 + from 0 address.
331379 #define FMC_CFG 0x00
331380 #define FMC_CFG_OP_MODE_MASK BIT_MASK(0)
331426 (reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT);
331450 + reg |= FMC_CFG_FLASH_SEL(0);
331514 return 0;
331559 writel(0xff, host->regbase + FMC_INT_CLR);
331569 return 0;
331615 writel(0xff, host->regbase + FMC_INT_CLR);
331621 + for (offset = 0; offset < len; offset += host->dma_len) {
331624 for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
331635 + for (offset = 0; offset < len; offset += host->dma_len) {
331638 for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) {
331738 + if (ret < 0)
331743 ret = mtd_device_register(mtd, NULL, 0);
331751 return 0;
331783 return 0;
331866 + return 0;
331883 + for (i = 0; i < host->num_chip; i++)
331900 + return 0;
331906 + for (i = 0; i < host->num_chip; i++)
331913 + return 0;
331923 + return 0;
331929 + for (i = 0; i < host->num_chip; i++)
331935 return 0;
332056 #define JEDEC_MFR(info) ((info)->id[0])
332113 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332114 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332115 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332116 + .reads[SNOR_CMD_READ_1_2_2] = SNOR_OP_READ(8, 0, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332117 + .reads[SNOR_CMD_READ_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332127 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332128 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332129 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332130 + .reads[SNOR_CMD_READ_1_2_2] = SNOR_OP_READ(8, 0, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332131 + .reads[SNOR_CMD_READ_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332145 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332146 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332147 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332148 + .reads[SNOR_CMD_READ_1_2_2] = SNOR_OP_READ(8, 0, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332149 + .reads[SNOR_CMD_READ_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332161 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332162 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332163 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332164 + .reads[SNOR_CMD_READ_1_2_2] = SNOR_OP_READ(8, 0, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332165 + .reads[SNOR_CMD_READ_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332178 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332179 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332180 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332181 + .reads[SNOR_CMD_READ_1_2_2] = SNOR_OP_READ(8, 0, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332182 + .reads[SNOR_CMD_READ_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332195 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332196 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332197 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332198 + .reads[SNOR_CMD_READ_1_2_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332199 + .reads[SNOR_CMD_READ_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332213 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332214 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332215 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332216 + .reads[SNOR_CMD_READ_1_2_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332217 + .reads[SNOR_CMD_READ_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332230 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332231 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332232 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332233 + .reads[SNOR_CMD_READ_1_2_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332234 + .reads[SNOR_CMD_READ_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332235 + .reads[SNOR_CMD_READ_1_4_4] = SNOR_OP_READ(0, 24, SPINOR_OP_READ_1_4_4,SNOR_PROTO_1_4_4),
332245 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332246 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332247 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332250 + .reads[SNOR_CMD_READ_1_4_4] = SNOR_OP_READ(0, 40, SPINOR_OP_READ_1_4_4,SNOR_PROTO_1_4_4),
332260 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332261 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332262 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332274 + .reads[SNOR_CMD_READ] = SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332275 + .reads[SNOR_CMD_READ_FAST] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332276 + .reads[SNOR_CMD_READ_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332277 + .reads[SNOR_CMD_READ_1_2_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332278 + .reads[SNOR_CMD_READ_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332279 + .reads[SNOR_CMD_READ_1_4_4] = SNOR_OP_READ(0, 24, SPINOR_OP_READ_1_4_4,SNOR_PROTO_1_4_4),
332291 + .reads[SNOR_CMD_READ]= SNOR_OP_READ(0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1),
332292 + .reads[SNOR_CMD_READ_FAST]= SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1),
332293 + .reads[SNOR_CMD_READ_1_1_2]= SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2, SNOR_PROTO_1_1_2),
332294 + .reads[SNOR_CMD_READ_1_2_2]= SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_2_2, SNOR_PROTO_1_2_2),
332295 + .reads[SNOR_CMD_READ_1_1_4]= SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4),
332296 + .reads[SNOR_CMD_READ_1_4_4]= SNOR_OP_READ(0, 24, SPINOR_OP_READ_1_4_4,SNOR_PROTO_1_4_4),
332372 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
332375 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
332376 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
332378 + { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64,
332380 + { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128,
332382 + { "en25qh64a", INFO(0x1c7017, 0, 64 * 1024, 128,
332385 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
332386 - { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
332387 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
332389 + { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
332390 { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
332391 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
332392 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
332395 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
332400 + { "gd25q16c", INFO(0xc84015, 0, 64 * 1024, 32,
332402 + { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
332404 + { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
332406 + { "gd25q128/gd25q127", INFO(0xc84018, 0, 64 * 1024, 256,
332409 + { "gd25lq16c", INFO(0xc86015, 0, 64 * 1024, 32,
332411 + { "gd25lq64", INFO(0xc86017, 0, 64 * 1024, 128,
332413 + { "gd25lq128", INFO(0xc86018, 0, 64 * 1024, 256,
332417 "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
332423 - "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
332424 + "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
332429 - "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
332430 + "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
332435 - "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
332436 + "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
332442 - "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
332443 + "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
332448 { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
332453 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
332454 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
332455 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
332456 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
332457 - { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
332458 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
332459 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
332460 - { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
332461 { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
332462 { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
332463 { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
332464 - { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
332465 - { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
332466 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
332467 - { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
332468 { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
332469 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
332470 - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_N…
332471 - { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_RE…
332472 …{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_REA…
332473 - { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
332474 + { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ)},
332479 + { "mx25l64XXfm2i-08g", INFO(0xc22017, 0, 64 * 1024, 128,
332481 + { "mx25l12835f", INFO(0xc22018, 0, 64 * 1024, 256,
332483 + { "mx25l25635f", INFO(0xc22019, 0, 64 * 1024, 512,
332485 + { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K
332487 + { "mx25v1635f", INFO(0xc22315, 0, 64 * 1024, 32 ,
332490 + { "mx25r6435f", INFO(0xc22817, 0, 64 * 1024, 128,
332493 + { "mx25u1633f", INFO(0xc22535, 0, 64 * 1024, 32,
332495 + { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128,
332497 + { "mx25u12835f/mx25u12832f", INFO(0xc22538, 0, 64 * 1024, 256,
332499 + { "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
332501 + { "mx66l51235l/mx25l51245g", INFO(0xc2201a, 0, 64 * 1024, 1024,
332503 + { "mx66u1g45gm", INFO(0xc2253b, 0, 64 * 1024, 2048,
332506 + { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
332507 + { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
332508 + { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
332509 + { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
332510 + { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
332511 + { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_RE…
332512 + { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_N…
332517 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
332518 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
332520 + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ)
332522 + { "mt25ql256a", INFO(0x20ba19, 0x1044, 64 * 1024, 512, SPI_NOR_QUAD_READ)
332525 + { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ)
332527 + { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ)
332529 + { "mt25qu128a/n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ)
332531 + { "mt25qu256a", INFO(0x20bb19, 0, 64 * 1024, 512,
332533 + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, USE_FSR | SPI_NOR_QUAD_READ)
332536 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
332537 - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
332538 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
332539 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
332540 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
332541 …{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_REA…
332542 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
332543 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
332545 + { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
332546 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
332547 …{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHI…
332548 …{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHI…
332549 …{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHI…
332553 + { "xm25qh64a", INFO(0x207017, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ)
332555 + { "xm25qh64b", INFO(0x206017, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ)
332557 + { "xm25qh128a", INFO(0x207018, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ)
332559 + { "xm25qh128b", INFO(0x206018, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ)
332564 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
332565 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
332568 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
332569 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
332571 + { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
332572 + { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512,
332575 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
332576 …{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | US…
332578 …{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | US…
332579 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
332580 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
332582 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
332583 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
332587 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
332588 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
332589 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
332591 { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
332592 { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
332593 { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
332595 + { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64,
332597 + { "w25q64fv(spi)/w25q64jv_iq", INFO(0xef4017, 0, 64 * 1024, 128,
332599 + { "w25q128(b/f)v", INFO(0xef4018, 0, 64 * 1024, 256,
332601 + { "w25q128jv_im", INFO(0xef7018, 0, 64 * 1024, 256,
332603 + { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512,
332607 + { "w25q32fw", INFO(0xef6016, 0, 64 * 1024, 64,
332610 + { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
332613 + { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
332616 + { "w25q256jw-im", INFO(0xef8019, 0, 64 * 1024, 512,
332620 + { "w25q256jw-iq", INFO(0xef6019, 0, 64 * 1024, 512,
332625 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
332627 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
332632 - "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
332636 - { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
332637 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
332639 "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
332644 - { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
332645 - { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
332646 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
332647 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
332649 + { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
332650 + { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
332651 { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
332654 + "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
332658 + { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
332664 …{ "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) …
332665 …{ "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)…
332669 + { "pn25f16s", INFO(0xe04015, 0, 64 * 1024, 32,
332671 + { "pn25f32s", INFO(0xe04016, 0, 64 * 1024, 64,
332675 + { "xt25f128b", INFO(0x0b4018, 0, 64 * 1024, 256,
332677 + { "xt25f64b", INFO(0x0b4017, 0, 64 * 1024, 128,
332679 + { "xt25f32bssigu-s", INFO(0x0b4016, 0, 64 * 1024, 64,
332681 + { "xt25f16bssigu", INFO(0x0b4015, 0, 64 * 1024, 32,
332685 + {"p25q128h", INFO(0x856018, 0, 64 * 1024, 256,
332689 + { "FM25Q64-SOB-T-G",INFO(0xa14017, 0, 64 * 1024, 128,
332691 + { "FM25Q128-SOB-T-G",INFO(0xa14018, 0, 64 * 1024, 256,
332694 + { "H25S64",INFO(0x684017, 0, 64 * 1024, 128,
332696 + { "H25S128",INFO(0x684018, 0, 64 * 1024, 256,
332698 + { "ZB25VQ64A",INFO(0x5e4017, 0, 64 * 1024, 128,
332709 + if ((id[0] == 0xff) || (id[0] == 0x00)) {
332715 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
332730 for (i = 0; i < len; ) {
332734 u8 sr_cr[2] = {0, CR_QUAD_EN_SPAN};
332737 + unsigned int regval = 0;
332741 + return 0;
332745 + sr_cr[1] = (regval & 0xff) | CR_QUAD_EN_SPAN;
332747 + sr_cr[0] = regval & 0xff;
332756 - if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
332757 + if (!(ret > 0 && ((unsigned int)ret & CR_QUAD_EN_SPAN))) {
332762 return 0;
332772 + if (val_h < 0)
332776 + return 0;
332787 + nor->cmd_buf[0] = val_l;
332795 + if (!(ret > 0 && (ret & SR_QUAD_EN_XTX))) {
332800 + return 0;
332809 + if (ret < 0) {
332817 + nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
332819 + if (ret < 0) {
332830 + if (ret < 0) {
332839 + return 0;
332844 + u8 sr_cr[2] = {0};
332845 + unsigned int regval = 0;
332851 + val = ((regval & 0xff) | CR_QUAD_EN_SPAN) << 8;
332854 + val |= (regval & 0xff);
332857 + sr_cr[0] = val & 0xff;
332861 + if (ret < 0) {
332873 + return 0;
332881 + nor->cmd_buf[0] = (regval & 0xff) | CR_QUAD_EN_SPAN;
332884 + if (ret < 0) {
332894 + if (!(regval > 0 && (regval & CR_QUAD_EN_SPAN))) {
332899 + return 0;
332909 + return 0;
332911 + val = (((unsigned int)ret & 0xff) | CR_QUAD_EN_SPAN);
332914 + nor->cmd_buf[0] = val;
332916 + if (ret < 0) {
332928 + return 0;
332939 + nor->end_addr = 0;
332997 + if (ret < 0) {
333059 + dev_info(dev, "Address range [0 => %#x] is locked.\n",
333075 + if (ret < 0) {
333082 + return 0;
333089 + if (ret < 0) {
333096 + return 0;
333107 + return 0;
333113 + int ret = 0;
333114 + unsigned char cval = 0;
333115 + unsigned char val = 0;
333119 + if (val < 0)
333124 + if(ret < 0){
333133 + nor->cmd_buf[0]=val;
333149 + return 0;
333157 return 0;
333177 + memset(dma_safe_buf, 0, len);
333186 + memset(param_headers, 0, psize);
333189 if (err < 0) {
333220 if (best_match < 0)
333225 if (cmd < 0)
333248 return 0;
333264 + set_4byte(nor, info, 0);
333322 + return 0;
333448 @@ -0,0 +1,106 @@
333514 + default "0xFFFF"
333518 + This value is 16 bit, so its value is 0x0000~0xFFFF.
333519 + The default value is 0xFFFF.
333523 + default "0xFFFF"
333529 + This value is 16 bit, so its value is 0x0000~0xFFFF.
333530 + The default value is 0xFFFF.
333560 @@ -0,0 +1,2 @@
333568 @@ -0,0 +1,162 @@
333583 + u32 link_stat = 0;
333622 + /* EEE_1us: 0x7c for 125M */
333623 + writel(0x7c, ld->gmac_iobase +
333625 + writel(0x1e0400, ld->gmac_iobase + EEE_TIMER);
333628 + v |= 0x3 << 1; /* auto EEE and ... */
333666 + pr_info("fit phy_id:0x%x, phy_name:%s, eee:%d\n",
333682 + if (lp_eee_capable < 0)
333736 @@ -0,0 +1,52 @@
333749 +#define NO_EEE 0
333762 +#define EEE_CLK 0x800
333763 +#define MASK_EEE_CLK (0x3 << 20)
333766 +#define EEE_ENABLE 0x808
333767 +#define BIT_EEE_ENABLE BIT(0)
333768 +#define EEE_TIMER 0x80C
333769 +#define EEE_LINK_STATUS 0x810
333770 +#define BIT_PHY_LINK_STATUS BIT(0)
333771 +#define EEE_TIME_CLK_CNT 0x814
333775 +#define MACR 0x0D
333776 +#define MAADR 0x0E
333777 +#define EEE_DEV 0x3
333778 +#define EEE_CAPABILITY 0x14
333779 +#define EEELPAR_DEV 0x7
333780 +#define EEELPAR 0x3D /* EEE link partner ability register */
333781 +#define EEE_ADVERTISE 0x3c
333794 @@ -0,0 +1,184 @@
333815 + for (i = 0; phy_info_table[i].name; i++) {
333830 + phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */
333840 + phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */
333847 + static int first_time = 0;
333849 + u32 eee_type = 0;
333855 + eee_lan = phy_read(phy_dev, 0x10);
333856 + if (eee_lan < 0)
333858 + eee_lan = (u32)eee_lan | 0x4;
333859 + phy_write(phy_dev, 0x10, eee_lan);
333860 + eee_lan = phy_read(phy_dev, 0x10);
333861 + if (eee_lan < 0)
333864 + eee_lan = phy_read(phy_dev, 0x0);
333865 + if (eee_lan < 0)
333867 + eee_lan = (u32)eee_lan | 0x200;
333868 + phy_write(phy_dev, 0x0, eee_lan);
333881 +#define RTL8211EG_MAC 0
333885 + static int first_time = 0;
333888 + u32 eee_type = 0;
333893 + phy_write(phy_dev, 0x1f, 0x0);
333902 + phy_write(phy_dev, 0x1f, 0x7);
333903 + phy_write(phy_dev, 0x1e, 0x20);
333904 + phy_write(phy_dev, 0x1b, 0xa03a);
333905 + phy_write(phy_dev, 0x1f, 0x0);
333921 + u32 eee_type = 0;
333936 + static int first_time_init = 0;
333938 + u32 eee_type = 0;
333952 + if (v < 0)
333971 + {"SMSC LAN8740", 0x0007c110, MAC_EEE, &smsc_lan8740_init},
333973 + {"Realtek 8211EG", 0x001cc915, MAC_EEE, &rtl8211eg_mac_init},
333975 + {"Realtek 8211EG", 0x001cc915, PHY_EEE, &rtl8211eg_init},
333984 @@ -0,0 +1,118 @@
334031 + /* write 0 to cancel reset */
334036 + /* RST_BIT, write 0 to reset phy, write 1 to cancel reset */
334045 + /* write 0 to cancel reset */
334108 @@ -0,0 +1,2645 @@
334152 +#define has_tso_cap(hw_cap) ((((hw_cap) >> 28) & 0x3) == VER_TSO)
334159 +MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
334172 + writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
334186 + writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
334193 + writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
334200 + writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
334217 + writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
334234 + writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
334251 + writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
334268 + writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
334298 + writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
334304 + u32 val = 0;
334338 + writel(0, priv->gmac_iobase + ENA_PMU_INT);
334339 + writel(~0, priv->gmac_iobase + RAW_PMU_INT);
334343 + writel(0, priv->gmac_iobase + reg);
334345 + writel(~0, priv->gmac_iobase + RSS_RAW_PMU_INT);
334361 + writel(0, priv->gmac_iobase + COL_SLOT_TIME);
334371 + writel(0x10000, priv->gmac_iobase + RX_BQ_IN_TIMEOUT_TH);
334373 + writel(0x18000, priv->gmac_iobase + TX_RQ_IN_TIMEOUT_TH);
334394 + writel(~0, ld->gmac_iobase + reg);
334405 + for (i = 0; i < ld->num_rxqs; i++)
334413 + writel(0, ld->gmac_iobase + ENA_PMU_INT);
334423 + writel(0, ld->gmac_iobase + reg);
334434 + for (i = 0; i < ld->num_rxqs; i++)
334456 + writel(0xF, ld->gmac_iobase + DESC_WR_RD_ENA);
334463 + writel(0, ld->gmac_iobase + DESC_WR_RD_ENA);
334476 + writel(0, ld->gmac_iobase + PORT_EN);
334506 + writel(0, ld->gmac_iobase + PORT_MC_ADDR_LOW);
334507 + writel(0, ld->gmac_iobase + PORT_MC_ADDR_HIGH);
334515 + d = (ha->addr[0] << 8) | (ha->addr[1]); /* shift left 8bits */
334574 + for (i = 0; i < ld->RX_FQ.count; i++) {
334601 + for (i = 0; i < ld->TX_BQ.count; i++) {
334617 + val = mac[1] | (mac[0] << 8); /* shift left 8 bits */
334619 + /* mac 2 3 4 5 shift left 24 16 8 0 bits */
334631 + for (i = 0; i < ld->RX_FQ.count; i++) {
334656 + for (i = 0; i < ld->TX_BQ.count; i++) {
334738 + (long long)time_limit >= 0))
334803 + priv->old_link = 0;
334844 + pr_info("Higmac dma_sg_phy: 0x%pK\n", (void *)(uintptr_t)ld->dma_sg_phy);
334847 + ld->sg_head = 0;
334848 + ld->sg_tail = 0;
334850 + return 0;
334923 + for (rxq_id = 0; rxq_id < ld->num_rxqs; rxq_id++) {
334941 + u32 refill_cnt = 0;
334949 + for (i = 0, dma_info.pos = dma_info.start; i < dma_info.num; i++) {
334977 + desc->data_len = 0;
334978 + desc->fl = 0;
335064 + netdev_err(dev, "desc->skb(0x%p),RX_FQ.skb[%d](0x%p)\n",
335068 + return 0;
335077 + return 0;
335102 + for (i = 0, dma_info.pos = dma_info.start; i < dma_info.num; i++) {
335145 + "TX ERR: desc1=0x%x, desc2=0x%x, desc5=0x%x\n",
335151 + for (i = 0; i < sizeof(struct sg_desc) / sizeof(int); i++)
335152 + pr_err("%s,%d: sg_desc word[%d]=0x%x\n",
335158 + return 0;
335183 + for (i = 0; i < nfrags; i++) {
335205 + if (unlikely(higmac_check_tx_err(ld, tx_rq_desc, desc_pos) < 0)) {
335243 + id_free = 0;
335244 + pkt_rec[id_free].status = 0;
335248 + return 0;
335269 + return 0;
335277 + unsigned int bytes_compl = 0;
335278 + unsigned int pkts_compl = 0;
335290 + for (i = 0, dma_info.pos = dma_info.start; i < dma_info.num; i++) {
335307 + if (higmac_xmit_reclaim_release(dev, skb, desc, dma_info.pos) < 0)
335334 + int work_done = 0;
335410 + for (i = 0; i < nfrags; i++) {
335415 + dma_addr = skb_frag_dma_map(ld->dev, frag, 0,
335451 + return 0;
335506 + return 0;
335557 + id_send = 0;
335562 + return 0;
335574 + if (gso_segs == 0 && skb_shinfo(skb)->gso_size != 0)
335642 + return 0;
335653 + return 0;
335664 + if (unlikely(higmac_check_skb_len(skb, dev) < 0))
335693 + if (unlikely(ret < 0)) {
335707 + if (unlikely(ret < 0)) {
335739 + for (i = 0; i < priv->num_rxqs; i++) {
335751 + for (i = 0; i < priv->num_rxqs; i++) {
335799 + return 0;
335820 + return 0;
335861 + return 0;
335908 + return 0;
335915 + for (i = 0; i < QUEUE_NUMS + RSS_NUM_RXQS - 1; i++) {
335973 + return 0;
335980 + dma_addr_t phys_addr = 0;
335995 + for (i = 0; i < (QUEUE_NUMS + RSS_NUM_RXQS - 1); i++) {
336000 + memset(virt_addr, 0, size);
336006 + memset(virt_addr, 0, size);
336023 + return 0;
336037 + for (i = 0; i < priv->num_rxqs; i++) {
336052 + for (i = 0; i < priv->num_rxqs; i++) {
336068 + for (i = 0; i < priv->num_rxqs; i++) {
336070 + if (ret < 0) {
336085 + return 0;
336140 + if (ret < 0) {
336144 + return 0;
336158 + if (ret < 0) {
336163 + return 0;
336177 + ndev->irq = priv->irq[0];
336200 + timer_setup(&priv->monitor, higmac_monitor_func, 0);
336230 + return 0;
336243 + &higmac_adjust_link, 0, priv->phy_mode);
336250 + if ((priv->phy->phy_id == 0) && !fixed_link) {
336256 + pr_info("attached PHY %d to driver %s, PHY_ID=0x%x\n",
336287 + return 0;
336344 + if (ret < 0) {
336350 + priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
336355 + if (ret < 0) {
336372 + return 0;
336410 + return 0;
336554 + return 0;
336562 + for (i = 0; i < priv->num_rxqs; i++)
336570 + for (i = 0; i < priv->num_rxqs; i++)
336623 + return 0;
336678 + priv->old_link = 0;
336694 + return 0;
336738 + return 0;
336759 @@ -0,0 +1,603 @@
336778 +#define STATION_ADDR_LOW 0x0000
336779 +#define STATION_ADDR_HIGH 0x0004
336780 +#define MAC_DUPLEX_HALF_CTRL 0x0008
336782 +#define PORT_MODE 0x0040
336784 +#define PORT_EN 0x0044
336788 +#define FC_TX_TIMER 0x001C
336790 +#define PAUSE_THR 0x0038
336792 +#define PAUSE_EN 0x0048
336793 +#define BIT_RX_FDFC BIT(0)
336796 +#define RX_PAUSE_EN 0x02A4
336797 +#define BIT_RX_FQ_PAUSE_EN BIT(0)
336800 +#define CRF_TX_PAUSE 0x0340
336803 +#define BITS_Q_PAUSE_TH_MASK 0xFFFF
336805 +#define REC_FILT_CONTROL 0x0064
336811 +#define BIT_UC_MATCH_EN BIT(0)
336813 +#define PORT_MC_ADDR_LOW 0x0068
336814 +#define PORT_MC_ADDR_HIGH 0x006C
336815 +#define MAC_CLEAR 0x0070
336816 +#define BIT_TX_SOFT_RESET BIT(0)
336818 +#define MODE_CHANGE_EN 0x01b4
336819 +#define BIT_MODE_CHANGE_EN BIT(0)
336821 +#define COL_SLOT_TIME 0x01c0
336823 +#define CRF_MIN_PACKET 0x0210
336827 +#define CONTROL_WORD 0x0214
336828 +#define CONTROL_WORD_CONFIG 0x640
336830 +#define TSO_COE_CTRL 0x02e8
336838 +#define RX_FQ_START_ADDR 0x0500
336839 +#define RX_FQ_DEPTH 0x0504
336843 +#define TX_DESC_HI8_MASK 0xff
336845 +#define RX_FQ_WR_ADDR 0x0508
336846 +#define BITS_RX_FQ_WR_ADDR mk_bits(0, 21)
336847 +#define RX_FQ_RD_ADDR 0x050c
336848 +#define BITS_RX_FQ_RD_ADDR mk_bits(0, 21)
336849 +#define RX_FQ_VLDDESC_CNT 0x0510
336850 +#define BITS_RX_FQ_VLDDESC_CNT mk_bits(0, 16)
336851 +#define RX_FQ_ALEMPTY_TH 0x0514
336852 +#define BITS_RX_FQ_ALEMPTY_TH mk_bits(0, 16)
336853 +#define RX_FQ_REG_EN 0x0518
336856 +#define BITS_RX_FQ_RD_ADDR_EN mk_bits(0, 1)
336857 +#define RX_FQ_ALFULL_TH 0x051c
336858 +#define BITS_RX_FQ_ALFULL_TH mk_bits(0, 16)
336860 +#define RX_BQ_START_ADDR 0x0520
336861 +#define RX_BQ_DEPTH 0x0524
336862 +#define RX_BQ_WR_ADDR 0x0528
336863 +#define RX_BQ_RD_ADDR 0x052c
336864 +#define RX_BQ_FREE_DESC_CNT 0x0530
336865 +#define BITS_RX_BQ_FREE_DESC_CNT mk_bits(0, 16)
336866 +#define RX_BQ_ALEMPTY_TH 0x0534
336867 +#define BITS_RX_BQ_ALEMPTY_TH mk_bits(0, 16)
336868 +#define RX_BQ_REG_EN 0x0538
336871 +#define BITS_RX_BQ_WR_ADDR_EN mk_bits(0, 1)
336872 +#define RX_BQ_ALFULL_TH 0x053c
336873 +#define BITS_RX_BQ_ALFULL_TH mk_bits(0, 16)
336875 +#define TX_BQ_START_ADDR 0x0580
336876 +#define TX_BQ_DEPTH 0x0584
336877 +#define TX_BQ_WR_ADDR 0x0588
336878 +#define BITS_TX_BQ_WR_ADDR mk_bits(0, 21)
336879 +#define TX_BQ_RD_ADDR 0x058c
336880 +#define BITS_TX_BQ_RD_ADDR mk_bits(0, 21)
336881 +#define TX_BQ_VLDDESC_CNT 0x0590
336882 +#define BITS_TX_BQ_VLDDESC_CNT mk_bits(0, 16)
336883 +#define TX_BQ_ALEMPTY_TH 0x0594
336884 +#define BITS_TX_BQ_ALEMPTY_TH mk_bits(0, 16)
336885 +#define TX_BQ_REG_EN 0x0598
336888 +#define BITS_TX_BQ_RD_ADDR_EN mk_bits(0, 1)
336889 +#define TX_BQ_ALFULL_TH 0x059c
336890 +#define BITS_TX_BQ_ALFULL_TH mk_bits(0, 16)
336892 +#define TX_RQ_START_ADDR 0x05a0
336893 +#define TX_RQ_DEPTH 0x05a4
336894 +#define TX_RQ_WR_ADDR 0x05a8
336895 +#define BITS_TX_RQ_WR_ADDR mk_bits(0, 21)
336896 +#define TX_RQ_RD_ADDR 0x05ac
336897 +#define BITS_TX_RQ_RD_ADDR mk_bits(0, 21)
336898 +#define TX_RQ_FREE_DESC_CNT 0x05b0
336899 +#define BITS_TX_RQ_FREE_DESC_CNT mk_bits(0, 16)
336900 +#define TX_RQ_ALEMPTY_TH 0x05b4
336901 +#define BITS_TX_RQ_ALEMPTY_TH mk_bits(0, 16)
336902 +#define TX_RQ_REG_EN 0x05b8
336905 +#define BITS_TX_RQ_WR_ADDR_EN mk_bits(0, 1)
336906 +#define TX_RQ_ALFULL_TH 0x05bc
336907 +#define BITS_TX_RQ_ALFULL_TH mk_bits(0, 16)
336909 +#define RAW_PMU_INT 0x05c0
336910 +#define ENA_PMU_INT 0x05c4
336912 +#define DESC_WR_RD_ENA 0x05CC
336914 +#define IN_QUEUE_TH 0x05d8
336917 +#define RX_BQ_IN_TIMEOUT_TH 0x05E0
336919 +#define TX_RQ_IN_TIMEOUT_TH 0x05e4
336921 +#define STOP_CMD 0x05e8
336923 +#define BITS_RX_STOP_EN BIT(0)
336926 +#define RSS_IND_TBL 0x0c0c
336929 +#define RSS_RAW_PMU_INT 0x0c10
336930 +#define RSS_QUEUE1_START_ADDR 0x0c20
336932 + ((i) - 1) * 0x10)
336933 +#define RSS_QUEUE1_DEPTH 0x0c24
336934 +#define RX_BQ_WR_ADDR_QUEUE1 0x0c28
336935 +#define RX_BQ_RD_ADDR_QUEUE1 0x0c2c
336936 +#define RSS_QUEUE1_ENA_INT 0x0c90
336937 +#define rss_ena_int_queue(i) (RSS_QUEUE1_ENA_INT + ((i) - 1) * 0x4)
336938 +#define rx_bq_depth_queue(i) (RSS_QUEUE1_DEPTH + ((i) - 1) * 0x10)
336940 + ((i) - 1) * 0x10) : RX_BQ_WR_ADDR)
336942 + ((i) - 1) * 0x10) : RX_BQ_RD_ADDR)
336944 +#define def_int_mask_queue(i) (0x3 << (2 * ((i) - 1)))
336947 +#define BURST_OUTSTANDING_REG 0x3014
336948 +#define BURST4_OUTSTANDING1 0x81ff
336951 +#define GMAC_SPEED_1000 0x05
336952 +#define GMAC_SPEED_100 0x01
336953 +#define GMAC_SPEED_10 0x00
336955 +#define IPV4_HEAD_LENGTH 0x5
336958 + ERR_NONE = 0,
336959 + ERR_DESC_CFG = (1 << 0),
337022 +#define HIGMAC_IOSIZE 0x1000
337034 +#define higmac_sync_barrier() do { isb(); smp_mb(); } while (0)
337036 +#define HISILICON_PHY_ID_FESTAV200 0x20669823
337037 +#define PHY_ID_KSZ8051MNL 0x00221550
337038 +#define PHY_ID_KSZ8081RNB 0x00221560
337039 +#define PHY_ID_UNKNOWN 0x00221513
337040 +#define DEFAULT_PHY_MASK 0xfffffff0
337041 +#define REALTEK_PHY_ID_8211E 0x001cc915
337042 +#define REALTEK_PHY_MASK 0x001fffff
337058 +#define HIGMAC_LINKED BIT(0)
337064 +#define FLOW_OFF 0
337069 +#define RX_BQ_INT_THRESHOLD 0x40
337070 +#define TX_RQ_INT_THRESHOLD 0x20
337077 +#define DESC_VLD_FREE 0
337081 +#define DESC_FL_MID 0
337106 +#define HW_CAP_TSO BIT(0)
337222 +#define SKB_MAGIC ((struct sk_buff *)0x5a)
337251 + int index; /* 0 -- mac0, 1 -- mac1 */
337275 +#define RX_FQ pool[0]
337321 +#define INIT 0 /* init gmac */
337327 + VER_NO_TSO = 0x0,
337328 + VER_BYTE_SPLICE = 0x1,
337329 + VER_SG_COE = 0x2,
337330 + VER_TSO = 0x3,
337368 @@ -0,0 +1,341 @@
337387 + int len = 0;
337389 + memset(data, 0, sizeof(data));
337391 + for (i = 0; i < N; i++) {
337392 + if (mask & 0x1)
337418 +#define PM_CLEAR 0
337424 + unsigned int cmd = 0;
337425 + unsigned int offset = 0;
337426 + unsigned short crc[FILTERS] = { 0 };
337432 + * 0 * * no use the filter
337433 + * 1 0 * all pkts can wake-up(non-exist)
337434 + * 1 1 0 all pkts can wake-up
337435 + * 1 1 !0 normal filter
337438 + for (i = 0; i < FILTERS; i++) {
337449 + * for logic, mask valid bit(bit31) must set to 0,
337450 + * 0 is enable
337460 + v &= ~(0xFFFF << (16 * i)); /* 16 bits mask */
337465 + v &= ~(0xFFFF << (16 * (i - 2))); /* filer 2 3, 16 bits mask */
337499 + v = 0;
337507 + v |= 0x3 << 5; /* set bit5 bit6, clear irq status */
337514 + return 0;
337535 + return 0;
337549 + v |= BIT(0); /* enter power down */
337551 + v |= 0x3 << 5; /* set bit5 bit6, clear irq status */
337571 + v &= ~BIT(0); /* enter power down */
337574 + v |= 0x3 << 5; /* set bit5 bit6, clear irq status */
337623 +#define POLYNOMIAL 0x8005
337624 +#define INITIAL_REMAINDER 0xFFFF
337625 +#define FINAL_XOR_VALUE 0x0000
337654 + unsigned int reversed = 0x00000000;
337658 + for (bit = 0; bit < nbits; ++bit) {
337660 + if (data & 0x01)
337676 + for (dividend = 0; dividend < CRC_TABLE_LEN; ++dividend) {
337681 + for (bit = 8; bit > 0; --bit) {
337701 + for (byte = 0; byte < nbytes; ++byte) {
337715 @@ -0,0 +1,59 @@
337757 +#define PMT_CTRL 0xa00
337758 +#define PMT_MASK0 0xa04
337759 +#define PMT_MASK1 0xa08
337760 +#define PMT_MASK2 0xa0c
337761 +#define PMT_MASK3 0xa10
337762 +#define PMT_CMD 0xa14
337763 +#define PMT_OFFSET 0xa18
337764 +#define PMT_CRC1_0 0xa1c
337765 +#define PMT_CRC3_2 0xa20
337781 @@ -0,0 +1,119 @@
337795 + return 0;
337801 + return 0;
337806 + return 0;
337845 + for (i = 0; i < ARRAY_SIZE(proc_file); i++) {
337848 + entry = proc_create(proc_file[i].name, 0, higmac_proc_root,
337859 + for (i = 0; i < ARRAY_SIZE(proc_file); i++)
337869 + int val = 0;
337899 + return 0;
337906 @@ -0,0 +1,19 @@
337931 @@ -0,0 +1,59 @@
337996 @@ -0,0 +1,975 @@
338077 + writel_relaxed(0, priv->gmac_iobase + MODE_CHANGE_EN);
338105 + return 0;
338129 + if (tx_flow_ctrl_pause_time < 0 ||
338133 + if (tx_flow_ctrl_pause_interval < 0 ||
338193 + writel(0, ld->gmac_iobase + CRF_TX_PAUSE);
338267 + return 0;
338290 + return 0;
338329 + return 0;
338340 + csum = skb_checksum(skb, offset, skb->len - offset, 0);
338345 + if (udp_csum == 0)
338386 + *coe_enable = 0;
338401 + *coe_enable = 0;
338404 + return 0;
338413 + unsigned char coe_enable = 0;
338422 + tx_bq_desc->desc1.val = 0;
338433 + if (ret < 0)
338452 + return 0;
338469 + return ld->phy->link ? HIGMAC_LINKED : 0;
338505 + pause->rx_pause = 0;
338506 + pause->tx_pause = 0;
338543 + return 0;
338587 + for (i = 0; i < rss->ind_tbl_size; i++)
338591 + return 0;
338618 + for (i = 0; !(readl(base + RSS_IND_TBL) & BIT_IND_TBL_READY); i++) {
338626 + return 0;
338637 + for (i = 0; i < rss->ind_tbl_size; i++) {
338638 + if (higmac_wait_rss_ready(priv) != 0)
338653 + for (i = 0; i < rss->ind_tbl_size; i++) {
338654 + if (higmac_wait_rss_ready(priv) != 0)
338657 + if (higmac_wait_rss_ready(priv) != 0)
338660 + rss->ind_tbl[i] = (rss_val >> 10) & 0x3; /* right shift 10 */
338676 + for (i = 0; i < rss->ind_tbl_size; i++)
338687 + return 0;
338706 + info->data = 0;
338726 + higmac_get_rss_hash(info, hash_cfg, IPV4_L3_HASH_EN, 0,
338730 + higmac_get_rss_hash(info, hash_cfg, IPV6_L3_HASH_EN, 0,
338737 + return 0;
338750 + ret = 0;
338771 + case 0: // all bits is 0
338784 + return 0;
338796 + return 0;
338851 + return 0;
338874 + return 0;
338876 + ret = phy_read(phy_dev, 0x1F);
338877 + if (ret < 0)
338881 + phy_write(phy_dev, 0x1F, v);
338883 + ret = phy_read(phy_dev, 0x16);
338884 + if (ret < 0)
338888 + phy_write(phy_dev, 0x16, v);
338890 + return 0;
338899 + return 0;
338901 + ret = phy_read(phy_dev, 0x1F);
338902 + if (ret < 0)
338906 + phy_write(phy_dev, 0x1F, v);
338908 + return 0;
338917 + return 0;
338919 + ret = phy_read(phy_dev, 0x1F);
338920 + if (ret < 0)
338924 + phy_write(phy_dev, 0x1F, v);
338926 + return 0;
338935 + phy_write(phy_dev, 0x1f, 0x7);
338937 + phy_write(phy_dev, 0x1e, 0xa4);
338940 + ret = phy_read(phy_dev, 0x1c);
338941 + if (ret < 0)
338944 + v = (v & 0xff03) | 0xfc;
338945 + phy_write(phy_dev, 0x1c, v);
338947 + /* select to page 0 */
338948 + phy_write(phy_dev, 0x1f, 0);
338950 + return 0;
338977 @@ -0,0 +1,102 @@
338993 +#define mk_bits(shift, nbits) ((((shift) & 0x1F) << 16) | ((nbits) & 0x3F))
339002 +#define FC_PAUSE_TIME_DEFAULT 0xFFFF
339003 +#define FC_PAUSE_INTERVAL_DEFAULT 0xFFFF
339004 +#define FC_PAUSE_TIME_MAX 0xFFFF
339006 +#define HW_CAP_EN 0x0c00
339007 +#define BIT_RSS_CAP BIT(0)
339009 +#define RSS_HASH_KEY 0x0c04
339010 +#define RSS_HASH_CONFIG 0x0c08
339011 +#define TCPV4_L3_HASH_EN BIT(0)
339027 +#define DEF_HASH_CFG 0x377377
339029 +#define RGMII_SPEED_1000 0x2c
339030 +#define RGMII_SPEED_100 0x2f
339031 +#define RGMII_SPEED_10 0x2d
339032 +#define MII_SPEED_100 0x0f
339033 +#define MII_SPEED_10 0x0d
339034 +#define RMII_SPEED_100 0x8f
339035 +#define RMII_SPEED_10 0x8d
339085 @@ -0,0 +1,6 @@
339097 @@ -0,0 +1,191 @@
339107 + 0x33f9, 0xbd, 0x33fa, 0x34, 0x33fb, 0x00,
339108 + 0x33fc, 0x39, 0x3400, 0x39, 0x3401, 0xCC,
339109 + 0x3402, 0x2C, 0x3403, 0x02, 0x3404, 0xFD,
339110 + 0x3405, 0xFF, 0x3406, 0xF0, 0x3407, 0xF6,
339111 + 0x3408, 0x36, 0x3409, 0x18, 0x340A, 0x26,
339112 + 0x340B, 0x05, 0x340C, 0xC6, 0x340D, 0x01,
339113 + 0x340E, 0xF7, 0x340F, 0x36, 0x3410, 0x18,
339114 + 0x3411, 0xCC, 0x3412, 0x35, 0x3413, 0x9F,
339115 + 0x3414, 0x1A, 0x3415, 0xB3, 0x3416, 0x00,
339116 + 0x3417, 0xD2, 0x3418, 0x27, 0x3419, 0x09,
339117 + 0x341A, 0xFD, 0x341B, 0x00, 0x341C, 0xD2,
339118 + 0x341D, 0x7F, 0x341E, 0x01, 0x341F, 0xBF,
339119 + 0x3420, 0x7F, 0x3421, 0x01, 0x3422, 0xB1,
339120 + 0x3423, 0x39, 0x3424, 0x3C, 0x3425, 0x3C,
339121 + 0x3426, 0x30, 0x3427, 0xF6, 0x3428, 0x30,
339122 + 0x3429, 0x55, 0x342A, 0xC0, 0x342B, 0x07,
339123 + 0x342C, 0x18, 0x342D, 0xFE, 0x342E, 0x30,
339124 + 0x342F, 0x4C, 0x3430, 0x18, 0x3431, 0x3A,
339125 + 0x3432, 0x18, 0x3433, 0xE6, 0x3434, 0x00,
339126 + 0x3435, 0x5C, 0x3436, 0xE7, 0x3437, 0x01,
339127 + 0x3438, 0xC1, 0x3439, 0x07, 0x343A, 0x23,
339128 + 0x343B, 0x04, 0x343C, 0xC6, 0x343D, 0x07,
339129 + 0x343E, 0xE7, 0x343F, 0x01, 0x3440, 0x58,
339130 + 0x3441, 0x58, 0x3442, 0x58, 0x3443, 0x58,
339131 + 0x3444, 0x58, 0x3445, 0xE7, 0x3446, 0x00,
339132 + 0x3447, 0xF6, 0x3448, 0x20, 0x3449, 0x04,
339133 + 0x344A, 0xC4, 0x344B, 0x1F, 0x344C, 0xEA,
339134 + 0x344D, 0x00, 0x344E, 0xF7, 0x344F, 0x20,
339135 + 0x3450, 0x04, 0x3451, 0x38, 0x3452, 0x38,
339136 + 0x3453, 0x39, 0x3454, 0x3C, 0x3455, 0x37,
339137 + 0x3456, 0x36, 0x3457, 0x30, 0x3458, 0x1A,
339138 + 0x3459, 0xEE, 0x345A, 0x00, 0x345B, 0x18,
339139 + 0x345C, 0xE6, 0x345D, 0x00, 0x345E, 0x26,
339140 + 0x345F, 0x1C, 0x3460, 0xF6, 0x3461, 0x00,
339141 + 0x3462, 0x5C, 0x3463, 0xC5, 0x3464, 0x04,
339142 + 0x3465, 0x27, 0x3466, 0x06, 0x3467, 0xCC,
339143 + 0x3468, 0x36, 0x3469, 0x12, 0x346A, 0xBD,
339144 + 0x346B, 0xF0, 0x346C, 0xA5, 0x346D, 0xF6,
339145 + 0x346E, 0x00, 0x346F, 0x47, 0x3470, 0xC4,
339146 + 0x3471, 0xF3, 0x3472, 0xF7, 0x3473, 0x00,
339147 + 0x3474, 0x47, 0x3475, 0xC6, 0x3476, 0x01,
339148 + 0x3477, 0x1A, 0x3478, 0xEE, 0x3479, 0x00,
339149 + 0x347A, 0x20, 0x347B, 0x10, 0x347C, 0x5A,
339150 + 0x347D, 0x26, 0x347E, 0x14, 0x347F, 0xF6,
339151 + 0x3480, 0x00, 0x3481, 0x46, 0x3482, 0x4F,
339152 + 0x3483, 0xC4, 0x3484, 0x0C, 0x3485, 0x83,
339153 + 0x3486, 0x00, 0x3487, 0x08, 0x3488, 0x26,
339154 + 0x3489, 0x05, 0x348A, 0xC6, 0x348B, 0x02,
339155 + 0x348C, 0x18, 0x348D, 0xE7, 0x348E, 0x00,
339156 + 0x348F, 0x5F, 0x3490, 0x38, 0x3491, 0x38,
339157 + 0x3492, 0x39, 0x3493, 0xF6, 0x3494, 0x00,
339158 + 0x3495, 0x5C, 0x3496, 0xC5, 0x3497, 0x04,
339159 + 0x3498, 0x27, 0x3499, 0x06, 0x349A, 0xCC,
339160 + 0x349B, 0x36, 0x349C, 0x08, 0x349D, 0xBD,
339161 + 0x349E, 0xF0, 0x349F, 0xA5, 0x34A0, 0xF6,
339162 + 0x34A1, 0x00, 0x34A2, 0x47, 0x34A3, 0xC4,
339163 + 0x34A4, 0xF3, 0x34A5, 0xCA, 0x34A6, 0x08,
339164 + 0x34A7, 0xF7, 0x34A8, 0x00, 0x34A9, 0x47,
339165 + 0x34AA, 0x18, 0x34AB, 0xFE, 0x34AC, 0x00,
339166 + 0x34AD, 0xB6, 0x34AE, 0x18, 0x34AF, 0xAD,
339167 + 0x34B0, 0x00, 0x34B1, 0xBD, 0x34B2, 0x34,
339168 + 0x34B3, 0x24, 0x34B4, 0xF6, 0x34B5, 0x1E,
339169 + 0x34B6, 0x05, 0x34B7, 0xC5, 0x34B8, 0x02,
339170 + 0x34B9, 0x27, 0x34BA, 0x0A, 0x34BB, 0xF6,
339171 + 0x34BC, 0x1E, 0x34BD, 0x07, 0x34BE, 0xC5,
339172 + 0x34BF, 0x02, 0x34C0, 0x27, 0x34C1, 0x03,
339173 + 0x34C2, 0xBD, 0x34C3, 0xC0, 0x34C4, 0x33,
339174 + 0x34C5, 0xF6, 0x34C6, 0x31, 0x34C7, 0x1F,
339175 + 0x34C8, 0x37, 0x34C9, 0xC6, 0x34CA, 0x52,
339176 + 0x34CB, 0xBD, 0x34CC, 0xDC, 0x34CD, 0x53,
339177 + 0x34CE, 0x31, 0x34CF, 0xF6, 0x34D0, 0x00,
339178 + 0x34D1, 0x41, 0x34D2, 0xC5, 0x34D3, 0x10,
339179 + 0x34D4, 0x26, 0x34D5, 0x04, 0x34D6, 0x13,
339180 + 0x34D7, 0x23, 0x34D8, 0x40, 0x34D9, 0x0D,
339181 + 0x34DA, 0xBD, 0x34DB, 0x93, 0x34DC, 0xCE,
339182 + 0x34DD, 0x1A, 0x34DE, 0xEE, 0x34DF, 0x00,
339183 + 0x34E0, 0x18, 0x34E1, 0x6F, 0x34E2, 0x00,
339184 + 0x34E3, 0xC6, 0x34E4, 0x04, 0x34E5, 0x20,
339185 + 0x34E6, 0xA9, 0x34E7, 0x1A, 0x34E8, 0xEE,
339186 + 0x34E9, 0x00, 0x34EA, 0x18, 0x34EB, 0x6F,
339187 + 0x34EC, 0x00, 0x34ED, 0xC6, 0x34EE, 0x01,
339188 + 0x34EF, 0x20, 0x34F0, 0x9F, 0x34F1, 0x3C,
339189 + 0x34F2, 0x37, 0x34F3, 0x36, 0x34F4, 0x30,
339190 + 0x34F5, 0x1A, 0x34F6, 0xEE, 0x34F7, 0x00,
339191 + 0x34F8, 0x18, 0x34F9, 0xE6, 0x34FA, 0x00,
339192 + 0x34FB, 0x26, 0x34FC, 0x49, 0x34FD, 0xF6,
339193 + 0x34FE, 0x00, 0x34FF, 0x5C, 0x3500, 0xC5,
339194 + 0x3501, 0x04, 0x3502, 0x27, 0x3503, 0x06,
339195 + 0x3504, 0xCC, 0x3505, 0x35, 0x3506, 0xFC,
339196 + 0x3507, 0xBD, 0x3508, 0xF0, 0x3509, 0xA5,
339197 + 0x350A, 0xC6, 0x350B, 0x52, 0x350C, 0xBD,
339198 + 0x350D, 0xDC, 0x350E, 0xF3, 0x350F, 0x5D,
339199 + 0x3510, 0x27, 0x3511, 0x03, 0x3512, 0xBD,
339200 + 0x3513, 0xC0, 0x3514, 0x22, 0x3515, 0xF6,
339201 + 0x3516, 0x00, 0x3517, 0x46, 0x3518, 0xC5,
339202 + 0x3519, 0x0C, 0x351A, 0x26, 0x351B, 0x0A,
339203 + 0x351C, 0x1A, 0x351D, 0xEE, 0x351E, 0x00,
339204 + 0x351F, 0x18, 0x3520, 0x6F, 0x3521, 0x00,
339205 + 0x3522, 0xC6, 0x3523, 0x07, 0x3524, 0x20,
339206 + 0x3525, 0x1D, 0x3526, 0xFC, 0x3527, 0x30,
339207 + 0x3528, 0x0C, 0x3529, 0xBD, 0x352A, 0x93,
339208 + 0x352B, 0x19, 0x352C, 0xBD, 0x352D, 0x9F,
339209 + 0x352E, 0x0B, 0x352F, 0xC6, 0x3530, 0x02,
339210 + 0x3531, 0x37, 0x3532, 0xC6, 0x3533, 0x51,
339211 + 0x3534, 0xBD, 0x3535, 0xDC, 0x3536, 0x53,
339212 + 0x3537, 0x31, 0x3538, 0x7F, 0x3539, 0x02,
339213 + 0x353A, 0x07, 0x353B, 0xC6, 0x353C, 0x02,
339214 + 0x353D, 0x1A, 0x353E, 0xEE, 0x353F, 0x00,
339215 + 0x3540, 0x18, 0x3541, 0xE7, 0x3542, 0x00,
339216 + 0x3543, 0x38, 0x3544, 0x38, 0x3545, 0x39,
339217 + 0x3546, 0xC6, 0x3547, 0x52, 0x3548, 0xBD,
339218 + 0x3549, 0xDC, 0x354A, 0xF3, 0x354B, 0x5D,
339219 + 0x354C, 0x27, 0x354D, 0x03, 0x354E, 0xBD,
339220 + 0x354F, 0xC0, 0x3550, 0x22, 0x3551, 0xF6,
339221 + 0x3552, 0x00, 0x3553, 0x46, 0x3554, 0xC5,
339222 + 0x3555, 0x0C, 0x3556, 0x26, 0x3557, 0x0A,
339223 + 0x3558, 0x1A, 0x3559, 0xEE, 0x355A, 0x00,
339224 + 0x355B, 0x18, 0x355C, 0x6F, 0x355D, 0x00,
339225 + 0x355E, 0xC6, 0x355F, 0x07, 0x3560, 0x20,
339226 + 0x3561, 0xE1, 0x3562, 0xC6, 0x3563, 0x51,
339227 + 0x3564, 0xBD, 0x3565, 0xDC, 0x3566, 0xF3,
339228 + 0x3567, 0x5D, 0x3568, 0x26, 0x3569, 0x04,
339229 + 0x356A, 0xC6, 0x356B, 0x02, 0x356C, 0x20,
339230 + 0x356D, 0xD5, 0x356E, 0xF6, 0x356F, 0x00,
339231 + 0x3570, 0x41, 0x3571, 0xC5, 0x3572, 0x10,
339232 + 0x3573, 0x26, 0x3574, 0x20, 0x3575, 0xF6,
339233 + 0x3576, 0x02, 0x3577, 0x07, 0x3578, 0xC1,
339234 + 0x3579, 0x02, 0x357A, 0x24, 0x357B, 0x19,
339235 + 0x357C, 0x18, 0x357D, 0xFE, 0x357E, 0x02,
339236 + 0x357F, 0x08, 0x3580, 0x18, 0x3581, 0xAD,
339237 + 0x3582, 0x00, 0x3583, 0xF6, 0x3584, 0x02,
339238 + 0x3585, 0x06, 0x3586, 0x27, 0x3587, 0x0D,
339239 + 0x3588, 0xC6, 0x3589, 0x02, 0x358A, 0x37,
339240 + 0x358B, 0xC6, 0x358C, 0x51, 0x358D, 0xBD,
339241 + 0x358E, 0xDC, 0x358F, 0x53, 0x3590, 0x31,
339242 + 0x3591, 0xC6, 0x3592, 0x02, 0x3593, 0x20,
339243 + 0x3594, 0xAE, 0x3595, 0x1A, 0x3596, 0xEE,
339244 + 0x3597, 0x00, 0x3598, 0x18, 0x3599, 0x6F,
339245 + 0x359A, 0x00, 0x359B, 0xC6, 0x359C, 0x03,
339246 + 0x359D, 0x20, 0x359E, 0xA4, 0x359F, 0xF6,
339247 + 0x35A0, 0x01, 0x35A1, 0xBF, 0x35A2, 0xC1,
339248 + 0x35A3, 0x08, 0x35A4, 0x24, 0x35A5, 0x55,
339249 + 0x35A6, 0xBD, 0x35A7, 0xF6, 0x35A8, 0xD3,
339250 + 0x35A9, 0x35, 0x35AA, 0xBA, 0x35AB, 0x35,
339251 + 0x35AC, 0xC2, 0x35AD, 0x35, 0x35AE, 0xCA,
339252 + 0x35AF, 0x35, 0x35B0, 0xD2, 0x35B1, 0x35,
339253 + 0x35B2, 0xDA, 0x35B3, 0x35, 0x35B4, 0xE2,
339254 + 0x35B5, 0x35, 0x35B6, 0xEA, 0x35B7, 0x35,
339255 + 0x35B8, 0xF2, 0x35B9, 0x39, 0x35BA, 0xCC,
339256 + 0x35BB, 0x01, 0x35BC, 0xB1, 0x35BD, 0xBD,
339257 + 0x35BE, 0x34, 0x35BF, 0x54, 0x35C0, 0x20,
339258 + 0x35C1, 0x36, 0x35C2, 0xCC, 0x35C3, 0x01,
339259 + 0x35C4, 0xB1, 0x35C5, 0xBD, 0x35C6, 0xC1,
339260 + 0x35C7, 0x52, 0x35C8, 0x20, 0x35C9, 0x2E,
339261 + 0x35CA, 0xCC, 0x35CB, 0x01, 0x35CC, 0xB1,
339262 + 0x35CD, 0xBD, 0x35CE, 0x34, 0x35CF, 0xF1,
339263 + 0x35D0, 0x20, 0x35D1, 0x26, 0x35D2, 0xCC,
339264 + 0x35D3, 0x01, 0x35D4, 0xB1, 0x35D5, 0xBD,
339265 + 0x35D6, 0xC3, 0x35D7, 0x9A, 0x35D8, 0x20,
339266 + 0x35D9, 0x1E, 0x35DA, 0xCC, 0x35DB, 0x01,
339267 + 0x35DC, 0xB1, 0x35DD, 0xBD, 0x35DE, 0xC4,
339268 + 0x35DF, 0x39, 0x35E0, 0x20, 0x35E1, 0x16,
339269 + 0x35E2, 0xCC, 0x35E3, 0x01, 0x35E4, 0xB1,
339270 + 0x35E5, 0xBD, 0x35E6, 0xC5, 0x35E7, 0x0B,
339271 + 0x35E8, 0x20, 0x35E9, 0x0E, 0x35EA, 0xCC,
339272 + 0x35EB, 0x01, 0x35EC, 0xB1, 0x35ED, 0xBD,
339273 + 0x35EE, 0xC6, 0x35EF, 0x3A, 0x35F0, 0x20,
339274 + 0x35F1, 0x06, 0x35F2, 0xCC, 0x35F3, 0x01,
339275 + 0x35F4, 0xB1, 0x35F5, 0xBD, 0x35F6, 0xC7,
339276 + 0x35F7, 0xC2, 0x35F8, 0xF7, 0x35F9, 0x01,
339277 + 0x35FA, 0xBF, 0x35FB, 0x39, 0x35FC, 0x43,
339278 + 0x35FD, 0x3A, 0x35FE, 0x41, 0x35FF, 0x44,
339279 + 0x3600, 0x54, 0x3601, 0x5F, 0x3602, 0x41,
339280 + 0x3603, 0x54, 0x3604, 0x4E, 0x3605, 0x0A,
339281 + 0x3606, 0x0D, 0x3607, 0x00, 0x3608, 0x43,
339282 + 0x3609, 0x3A, 0x360A, 0x45, 0x360B, 0x6E,
339283 + 0x360C, 0x5F, 0x360D, 0x53, 0x360E, 0x74,
339284 + 0x360F, 0x0A, 0x3610, 0x0D, 0x3611, 0x00,
339285 + 0x3612, 0x43, 0x3613, 0x3A, 0x3614, 0x49,
339286 + 0x3615, 0x0A, 0x3616, 0x0D, 0x3617, 0x00,
339287 + 0x3618, 0x00, 0x3400, 0x01, 0x33f8, 0x01
339295 @@ -0,0 +1,84 @@
339305 + 0x33f9, 0xbd, 0x33fa, 0x34, 0x33fb, 0x00,
339306 + 0x33fc, 0x39, 0x3400, 0x39, 0x3401, 0xCC,
339307 + 0x3402, 0x2E, 0x3403, 0x01, 0x3404, 0xFD,
339308 + 0x3405, 0xFF, 0x3406, 0xF2, 0x3407, 0x4F,
339309 + 0x3408, 0xFD, 0x3409, 0xFF, 0x340A, 0xF0,
339310 + 0x340B, 0xF6, 0x340C, 0x34, 0x340D, 0xD7,
339311 + 0x340E, 0x26, 0x340F, 0x05, 0x3410, 0xC6,
339312 + 0x3411, 0x01, 0x3412, 0xF7, 0x3413, 0x34,
339313 + 0x3414, 0xD7, 0x3415, 0xF6, 0x3416, 0x08,
339314 + 0x3417, 0x00, 0x3418, 0xF7, 0x3419, 0x34,
339315 + 0x341A, 0xD8, 0x341B, 0xC6, 0x341C, 0x01,
339316 + 0x341D, 0xF7, 0x341E, 0x08, 0x341F, 0x00,
339317 + 0x3420, 0x20, 0x3421, 0x0F, 0x3422, 0xCC,
339318 + 0x3423, 0x34, 0x3424, 0x3F, 0x3425, 0x1A,
339319 + 0x3426, 0xB3, 0x3427, 0x00, 0x3428, 0xCC,
339320 + 0x3429, 0x27, 0x342A, 0x03, 0x342B, 0xFD,
339321 + 0x342C, 0x00, 0x342D, 0xCC, 0x342E, 0x78,
339322 + 0x342F, 0x08, 0x3430, 0x00, 0x3431, 0xF6,
339323 + 0x3432, 0x08, 0x3433, 0x00, 0x3434, 0xC1,
339324 + 0x3435, 0x02, 0x3436, 0x26, 0x3437, 0xEA,
339325 + 0x3438, 0xF6, 0x3439, 0x34, 0x343A, 0xD8,
339326 + 0x343B, 0xF7, 0x343C, 0x08, 0x343D, 0x00,
339327 + 0x343E, 0x39, 0x343F, 0xBD, 0x3440, 0xF7,
339328 + 0x3441, 0xFA, 0x3442, 0x08, 0x3443, 0xCC,
339329 + 0x3444, 0x20, 0x3445, 0xA1, 0x3446, 0xED,
339330 + 0x3447, 0x05, 0x3448, 0xC6, 0x3449, 0xA4,
339331 + 0x344A, 0xED, 0x344B, 0x03, 0x344C, 0xBD,
339332 + 0x344D, 0x8B, 0x344E, 0x82, 0x344F, 0xE7,
339333 + 0x3450, 0x07, 0x3451, 0xC0, 0x3452, 0x02,
339334 + 0x3453, 0x27, 0x3454, 0x11, 0x3455, 0x5A,
339335 + 0x3456, 0x27, 0x3457, 0x0E, 0x3458, 0x5A,
339336 + 0x3459, 0x27, 0x345A, 0x39, 0x345B, 0x5A,
339337 + 0x345C, 0x27, 0x345D, 0x36, 0x345E, 0x5A,
339338 + 0x345F, 0x27, 0x3460, 0x51, 0x3461, 0x5A,
339339 + 0x3462, 0x27, 0x3463, 0x4E, 0x3464, 0x20,
339340 + 0x3465, 0x6D, 0x3466, 0x18, 0x3467, 0xFE,
339341 + 0x3468, 0x30, 0x3469, 0x1E, 0x346A, 0xF6,
339342 + 0x346B, 0x30, 0x346C, 0x22, 0x346D, 0x18,
339343 + 0x346E, 0x3A, 0x346F, 0x18, 0x3470, 0xE6,
339344 + 0x3471, 0x00, 0x3472, 0x58, 0x3473, 0x58,
339345 + 0x3474, 0xE7, 0x3475, 0x02, 0x3476, 0x1A,
339346 + 0x3477, 0xEE, 0x3478, 0x05, 0x3479, 0x18,
339347 + 0x347A, 0xE6, 0x347B, 0x00, 0x347C, 0xC4,
339348 + 0x347D, 0x03, 0x347E, 0xEA, 0x347F, 0x02,
339349 + 0x3480, 0x18, 0x3481, 0xE7, 0x3482, 0x00,
339350 + 0x3483, 0x1A, 0x3484, 0xEE, 0x3485, 0x03,
339351 + 0x3486, 0x18, 0x3487, 0xE6, 0x3488, 0x00,
339352 + 0x3489, 0xC4, 0x348A, 0x1F, 0x348B, 0xCA,
339353 + 0x348C, 0xC0, 0x348D, 0x18, 0x348E, 0xE7,
339354 + 0x348F, 0x00, 0x3490, 0xC6, 0x3491, 0x09,
339355 + 0x3492, 0x20, 0x3493, 0x3A, 0x3494, 0x1A,
339356 + 0x3495, 0xEE, 0x3496, 0x05, 0x3497, 0x18,
339357 + 0x3498, 0xE6, 0x3499, 0x00, 0x349A, 0xC4,
339358 + 0x349B, 0x03, 0x349C, 0xCA, 0x349D, 0x54,
339359 + 0x349E, 0x18, 0x349F, 0xE7, 0x34A0, 0x00,
339360 + 0x34A1, 0x1A, 0x34A2, 0xEE, 0x34A3, 0x03,
339361 + 0x34A4, 0x18, 0x34A5, 0xE6, 0x34A6, 0x00,
339362 + 0x34A7, 0xC4, 0x34A8, 0x1F, 0x34A9, 0xCA,
339363 + 0x34AA, 0x20, 0x34AB, 0x18, 0x34AC, 0xE7,
339364 + 0x34AD, 0x00, 0x34AE, 0xC6, 0x34AF, 0x74,
339365 + 0x34B0, 0x20, 0x34B1, 0x1C, 0x34B2, 0x1A,
339366 + 0x34B3, 0xEE, 0x34B4, 0x05, 0x34B5, 0x18,
339367 + 0x34B6, 0xE6, 0x34B7, 0x00, 0x34B8, 0xC4,
339368 + 0x34B9, 0x03, 0x34BA, 0xCA, 0x34BB, 0x48,
339369 + 0x34BC, 0x18, 0x34BD, 0xE7, 0x34BE, 0x00,
339370 + 0x34BF, 0x1A, 0x34C0, 0xEE, 0x34C1, 0x03,
339371 + 0x34C2, 0x18, 0x34C3, 0xE6, 0x34C4, 0x00,
339372 + 0x34C5, 0xC4, 0x34C6, 0x1F, 0x34C7, 0xCA,
339373 + 0x34C8, 0x20, 0x34C9, 0x18, 0x34CA, 0xE7,
339374 + 0x34CB, 0x00, 0x34CC, 0xC6, 0x34CD, 0x52,
339375 + 0x34CE, 0x18, 0x34CF, 0x08, 0x34D0, 0x18,
339376 + 0x34D1, 0xE7, 0x34D2, 0x00, 0x34D3, 0xAE,
339377 + 0x34D4, 0x00, 0x34D5, 0x38, 0x34D6, 0x39,
339378 + 0x34D7, 0x00, 0x3400, 0x01, 0x33f8, 0x01
339385 @@ -0,0 +1,44 @@
339395 + 0x33f9, 0xbd, 0x33fa, 0x34, 0x33fb, 0x00,
339396 + 0x33fc, 0x39, 0x3400, 0x39, 0x3401, 0xCC,
339397 + 0x3402, 0x27, 0x3403, 0x23, 0x3404, 0xFD,
339398 + 0x3405, 0xFF, 0x3406, 0xF0, 0x3407, 0x20,
339399 + 0x3408, 0x00, 0x3409, 0x3C, 0x340A, 0x3C,
339400 + 0x340B, 0x30, 0x340C, 0xF6, 0x340D, 0x00,
339401 + 0x340E, 0x4A, 0x340F, 0xC4, 0x3410, 0x7F,
339402 + 0x3411, 0xE7, 0x3412, 0x01, 0x3413, 0xF6,
339403 + 0x3414, 0x01, 0x3415, 0xBE, 0x3416, 0xC1,
339404 + 0x3417, 0x02, 0x3418, 0x27, 0x3419, 0x0E,
339405 + 0x341A, 0xE6, 0x341B, 0x01, 0x341C, 0xC1,
339406 + 0x341D, 0x14, 0x341E, 0x27, 0x341F, 0x08,
339407 + 0x3420, 0xC1, 0x3421, 0x18, 0x3422, 0x25,
339408 + 0x3423, 0x09, 0x3424, 0xC1, 0x3425, 0x1B,
339409 + 0x3426, 0x22, 0x3427, 0x05, 0x3428, 0xC6,
339410 + 0x3429, 0x5C, 0x342A, 0xF7, 0x342B, 0x20,
339411 + 0x342C, 0xA1, 0x342D, 0xF6, 0x342E, 0x01,
339412 + 0x342F, 0xBF, 0x3430, 0xC1, 0x3431, 0x01,
339413 + 0x3432, 0x26, 0x3433, 0x29, 0x3434, 0xF6,
339414 + 0x3435, 0x30, 0x3436, 0x55, 0x3437, 0xC0,
339415 + 0x3438, 0x05, 0x3439, 0xE7, 0x343A, 0x01,
339416 + 0x343B, 0xC1, 0x343C, 0x13, 0x343D, 0x23,
339417 + 0x343E, 0x04, 0x343F, 0xC6, 0x3440, 0x13,
339418 + 0x3441, 0xE7, 0x3442, 0x01, 0x3443, 0x18,
339419 + 0x3444, 0xFE, 0x3445, 0x30, 0x3446, 0x4C,
339420 + 0x3447, 0x18, 0x3448, 0x3A, 0x3449, 0x18,
339421 + 0x344A, 0xE6, 0x344B, 0x00, 0x344C, 0x58,
339422 + 0x344D, 0x58, 0x344E, 0x58, 0x344F, 0x58,
339423 + 0x3450, 0x58, 0x3451, 0xE7, 0x3452, 0x00,
339424 + 0x3453, 0xF6, 0x3454, 0x20, 0x3455, 0x04,
339425 + 0x3456, 0xC4, 0x3457, 0x1F, 0x3458, 0xEA,
339426 + 0x3459, 0x00, 0x345A, 0xF7, 0x345B, 0x20,
339427 + 0x345C, 0x04, 0x345D, 0x38, 0x345E, 0x38,
339428 + 0x345F, 0x39, 0x3400, 0x01, 0x33f8, 0x01
339436 @@ -0,0 +1,1581 @@
339478 +static u32 highflag = 0;
339479 +static u32 lowflag = 0;
339484 + int table[32] = {0x11, 0x10, 0x10, 0xf, 0xe, 0xd, 0xd, 0xc,
339485 + 0xb, 0xa, 0xa, 0x9, 0x8, 0x7, 0x7, 0x6,
339486 + 0x5, 0x5, 0x4, 0x3, 0x2, 0x2, 0x1, 0x0,
339487 + 0x3f, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a
339492 + val &= 0x1f;
339496 + val = (val1 << 2) | (val & 0x3); /* shift left 2 bits */
339516 + if ((temp > HIGH_TEMP) && (highflag == 0)) {
339518 + if ((val & 0x1f) > 1)
339519 + val = (val & 0xe0) | ((val & 0x1f) - 1);
339525 + highflag = 0;
339526 + if ((val & 0x1f) < 0x1f)
339527 + val = (val & 0xe0) | ((val & 0x1f) + 1);
339532 + if ((temp > NORMAL_TEMP2) && (lowflag == 0)) {
339534 + if ((val & 0x1f) > 1)
339535 + val = (val & 0xe0) | ((val & 0x1f) - 1);
339541 + lowflag = 0;
339542 + if ((val & 0x1f) < 0x1f)
339543 + val = (val & 0xe0) | ((val & 0x1f) + 1);
339565 + sys_reg_addr = (void __iomem *)ioremap_nocache(SYS_REG_ADDR, 0x100);
339571 + if ((val >> 30) != 0x3) { /* bit[30 31] */
339607 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
339632 + unsigned int bytes_compl = 0;
339633 + unsigned int pkts_compl = 0;
339678 + WARN(1, "tx err=0x%x, tx_info=0x%x, addr=0x%x\n",
339684 + for (i = 0; i < sizeof(struct tx_desc) / sizeof(int); i++)
339685 + pr_err("%s,%d: sg_desc word[%d]=0x%x\n",
339759 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
339763 + addr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE);
339772 + return 0;
339779 + u32 status = 0;
339935 + u32 rx_pkts_num = 0;
339986 + return 0;
339995 + u32 rx_pkts_num = 0;
340026 + if (hisi_femac_recv_queue(dev, skb, rx_pkt_info) < 0)
340052 + int work_done = 0;
340113 + return 0;
340138 + queue->head = 0;
340139 + queue->tail = 0;
340141 + return 0;
340158 + priv->tx_fifo_used_cnt = 0;
340160 + return 0;
340205 + priv->tx_fifo_used_cnt = 0;
340213 + reg = mac[1] | (mac[0] << 8); /* mac0 is high 8 bits */
340215 + /* addr2 [24 31] addr3 [16 23] addr4 [8 15] addr5 [0 7] */
340219 + return 0;
340235 + return 0;
340255 + priv->link_status = 0;
340263 + return 0;
340294 + return 0;
340404 + return 0;
340429 + /* addr2 [24 31] addr3 [16 23] addr4 [8 15] addr5 [0 7] */
340435 + val |= ((addr[0] << 8) | addr[1]); /* addr0 is high 8 bits */
340491 + int reg = 0;
340653 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
340679 + return 0;
340704 + return 0;
340732 + if (*ret < 0) {
340740 + phy = of_phy_connect(priv->ndev, of_node_get(node), &hisi_femac_adjust_link, 0,
340758 + phy_attached_print(phy, "phy_id=0x%.8lx, phy_mode=%s\n",
340823 + return 0;
340833 + ndev->irq = platform_get_irq(pdev, 0);
340834 + if (ndev->irq <= 0) {
340852 + return 0;
340931 + return 0;
340949 + return 0;
340968 + return 0;
341023 @@ -0,0 +1,269 @@
341035 +#define MAC_PORTSEL 0x0200
341036 +#define MAC_PORTSEL_STAT_CPU BIT(0)
341038 +#define MAC_PORTSET 0x0208
341039 +#define MAC_PORTSET_DUPLEX_FULL BIT(0)
341042 +#define MAC_SET 0x0210
341044 +#define MAX_FRAME_SIZE_MASK GENMASK(10, 0)
341046 +#define RX_COALESCE_SET 0x0340
341049 +#define RX_COALESCED_TIMER 0x74
341050 +#define QLEN_SET 0x0344
341055 +#define FC_LEVEL 0x0348
341057 +#define FC_DEACTIVE_THR_MASK GENMASK(5, 0)
341060 +#define IQFRM_DES 0x0354
341061 +#define RX_FRAME_LEN_MASK GENMASK(11, 0)
341063 +#define BITS_PAYLOAD_ERR_MASK 0x1
341065 +#define BITS_HEADER_ERR_MASK 0x1
341067 +#define BITS_PAYLOAD_DONE_MASK 0x1
341069 +#define BITS_HEADER_DONE_MASK 0x1
341070 +#define IQ_ADDR 0x0358
341071 +#define EQ_ADDR 0x0360
341072 +#define EQFRM_LEN 0x0364
341073 +#define ADDRQ_STAT 0x036C
341074 +#define TX_CNT_INUSE_MASK GENMASK(5, 0)
341077 +#define RX_COE_CTRL 0x0380
341084 +#define TSO_DBG_EN 0x03A4
341086 +#define TSO_DBG_STATE 0x03A8
341087 +#define TSO_DBG_ADDR 0x03AC
341088 +#define TSO_DBG_TX_INFO 0x03B0
341089 +#define TSO_DBG_TX_ERR 0x03B4
341091 +#define GLB_HOSTMAC_L32 0x0000
341092 +#define GLB_HOSTMAC_H16 0x0004
341093 +#define GLB_SOFT_RESET 0x0008
341094 +#define SOFT_RESET_ALL BIT(0)
341095 +#define GLB_FWCTRL 0x0010
341096 +#define FWCTRL_VLAN_ENABLE BIT(0)
341099 +#define GLB_MACTCTRL 0x0014
341104 +#define GLB_IRQ_STAT 0x0030
341105 +#define GLB_IRQ_ENA 0x0034
341106 +#define IRQ_ENA_PORT0_MASK GENMASK(7, 0)
341109 +#define GLB_IRQ_RAW 0x0038
341110 +#define IRQ_INT_RX_RDY BIT(0)
341118 +#define GLB_MAC_L32_BASE 0x0100
341119 +#define GLB_MAC_H16_BASE 0x0104
341120 +#define MACFLT_HI16_MASK GENMASK(15, 0)
341123 +#define glb_mac_h16(reg) (GLB_MAC_H16_BASE + ((reg) * 0x8))
341124 +#define glb_mac_l32(reg) (GLB_MAC_L32_BASE + ((reg) * 0x8))
341132 +#define HW_CAP_TSO BIT(0)
341188 +#define SYS_REG_ADDR 0x12028000
341189 +#define FEPHY_TRIM_CACHE 0x3022
341190 +#define FEPHY_TRIM_VALUE 0x20a1
341193 +#define LINK_STATUS 0x4
341194 +#define IS_LINK 0X4
341195 +#define SPEED_STATUS 0x18
341196 +#define SPEED_100M 0x8
341197 +#define LINK_AN_SR 0x11
341198 +#define MISC_CTRL45 0x00B4
341199 +#define MISC_CTRL47 0x00BC
341200 +#define MISC_CTRL48 0x00C0
341201 +#define TSENSOR_RESULT0 0x3ff
341202 +#define TSENSOR_RESULT1 0x3ff0000
341203 +#define TSENSOR_RESULT2 0x3ff
341204 +#define TSENSOR_RESULT3 0x3ff0000
341205 +#define TSENSOR_EN 0xc3200000
341210 +#define TSENSOR_LIMIT 0xfffff
341298 @@ -0,0 +1,109 @@
341332 + for (i = 0; i < count; i += 2) { /* Process 2 data at a time. */
341343 + return 0;
341355 + return 0;
341367 + return 0;
341379 + return 0;
341413 @@ -0,0 +1,22 @@
341424 +#define HISILICON_PHY_ID_FESTAV272 0x20669901
341425 +#define HISILICON_PHY_ID_FESTAV115 0x20669903
341426 +#define HISILICON_PHY_ID_FESTAV202 0x20669906
341427 +#define HISILICON_PHY_MASK 0xffffffff
341429 +#define MII_EXPMD 0x1d
341430 +#define MII_EXPMA 0x1e
341441 @@ -0,0 +1,318 @@
341464 + csum = skb_checksum(skb, offset, skb->len - offset, 0);
341470 + if (udp_csum == 0)
341516 + return 0;
341534 + return 0;
341540 + u32 pkt_info = 0;
341577 + u32 pkt_info = 0;
341580 + return 0;
341694 + int ret = 0;
341696 + if (dev == NULL || pause == NULL || pause->rx_pause == 0) {
341758 + return 0;
341765 @@ -0,0 +1,25 @@
341825 return 0;
341837 return 0;
341851 return 0;
341863 + memset(data + i, 0, ee->len - i);
341864 return 0;
341867 if (ret < 0) {
341869 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
341871 - return 0;
341915 @@ -1,166 +0,0 @@
341943 -#define MDIO_RWCTRL 0x00
341944 -#define MDIO_RO_DATA 0x04
341979 - return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
342018 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
342041 - return 0;
342059 - return 0;
342087 @@ -0,0 +1,280 @@
342116 +#define PHY_ADDR_MDCK0 0x0102F0048
342117 +#define PHY_ADDR_MDIO0 0x0102F004C
342119 +#define PHY_ADDR_MDCK1 0x017C701E0
342120 +#define PHY_ADDR_MDIO1 0x017C70200
342123 +#define PHY_ADDR_EPHY0_CLK 0x0102F0050
342124 +#define PHY_ADDR_EPHY0_RSTN 0x0102F0054
342126 +#define PHY_ADDR_EPHY1_CLK 0x017C701F0
342127 +#define PHY_ADDR_EPHY1_RSTN 0x017C701DC
342130 +#define PHY_ADDR_RGMII0_TXCKOUT 0x0102F0084
342131 +#define PHY_ADDR_RGMII0_TXD0 0x0102F0080
342132 +#define PHY_ADDR_RGMII0_TXD1 0x0102F007C
342133 +#define PHY_ADDR_RGMII0_TXD2 0x0102F0078
342134 +#define PHY_ADDR_RGMII0_TXD3 0x0102F0074
342135 +#define PHY_ADDR_RGMII0_TXEN 0x0102F0070
342136 +#define PHY_ADDR_RGMII0_RXCK 0x0102F006C
342137 +#define PHY_ADDR_RGMII0_RXD0 0x0102F0068
342138 +#define PHY_ADDR_RGMII0_RXD1 0x0102F0064
342139 +#define PHY_ADDR_RGMII0_RXD2 0x0102F0060
342140 +#define PHY_ADDR_RGMII0_RXD3 0x0102F005C
342141 +#define PHY_ADDR_RGMII0_RXDV 0x0102F0058
342144 +#define PHY_ADDR_RGMII1_TXCKOUT 0x017C70218
342145 +#define PHY_ADDR_RGMII1_TXD0 0x017C7020C
342146 +#define PHY_ADDR_RGMII1_TXD1 0x017C70214
342147 +#define PHY_ADDR_RGMII1_TXD2 0x017C701F4
342148 +#define PHY_ADDR_RGMII1_TXD3 0x017C70208
342149 +#define PHY_ADDR_RGMII1_TXEN 0x017C70210
342150 +#define PHY_ADDR_RGMII1_RXCK 0x017C701EC
342151 +#define PHY_ADDR_RGMII1_RXD0 0x017C701E4
342152 +#define PHY_ADDR_RGMII1_RXD1 0x017C70204
342153 +#define PHY_ADDR_RGMII1_RXD2 0x017C701FC
342154 +#define PHY_ADDR_RGMII1_RXD3 0x017C701F8
342155 +#define PHY_ADDR_RGMII1_RXDV 0x017C701E8
342158 +#define PHY_ADDR_RMII0_CLK 0x0102F0084
342159 +#define PHY_ADDR_RMII0_TXD0 0x0102F0080
342160 +#define PHY_ADDR_RMII0_TXD1 0x0102F007C
342161 +#define PHY_ADDR_RMII0_TXEN 0x0102F0070
342162 +#define PHY_ADDR_RMII0_RXD0 0x0102F0068
342163 +#define PHY_ADDR_RMII0_RXD1 0x0102F0064
342164 +#define PHY_ADDR_RMII0_RXDV 0x0102F0058
342167 +#define PHY_ADDR_RMII1_CLK 0x017C70218
342168 +#define PHY_ADDR_RMII1_TXD0 0x017C7020C
342169 +#define PHY_ADDR_RMII1_TXD1 0x017C70214
342170 +#define PHY_ADDR_RMII1_TXEN 0x017C70210
342171 +#define PHY_ADDR_RMII1_RXD0 0x017C701E4
342172 +#define PHY_ADDR_RMII1_RXD1 0x017C70204
342173 +#define PHY_ADDR_RMII1_RXDV 0x017C701E8
342176 +#define VALUE_MDCK0 0x1821
342177 +#define VALUE_MDIO0 0x1031
342179 +#define VALUE_MDCK1 0x1822
342180 +#define VALUE_MDIO1 0x1032
342183 +#define VALUE_EPHY0_CLK 0x1801
342184 +#define VALUE_EPHY0_RSTN 0x1031
342186 +#define VALUE_EPHY1_CLK 0x1802
342187 +#define VALUE_EPHY1_RSTN 0x1032
342190 +#define VALUE_RGMII0_TXCKOUT 0x1041
342191 +#define VALUE_RGMII0_TXD0 0x1051
342192 +#define VALUE_RGMII0_TXD1 0x1051
342193 +#define VALUE_RGMII0_TXD2 0x1051
342194 +#define VALUE_RGMII0_TXD3 0x1051
342195 +#define VALUE_RGMII0_TXEN 0x1051
342196 +#define VALUE_RGMII0_RXCK 0x1031
342197 +#define VALUE_RGMII0_RXD0 0x1031
342198 +#define VALUE_RGMII0_RXD1 0x1031
342199 +#define VALUE_RGMII0_RXD2 0x1031
342200 +#define VALUE_RGMII0_RXD3 0x1031
342201 +#define VALUE_RGMII0_RXDV 0x1031
342204 +#define VALUE_RGMII1_TXCKOUT 0x1042
342205 +#define VALUE_RGMII1_TXD0 0x1052
342206 +#define VALUE_RGMII1_TXD1 0x1052
342207 +#define VALUE_RGMII1_TXD2 0x1052
342208 +#define VALUE_RGMII1_TXD3 0x1052
342209 +#define VALUE_RGMII1_TXEN 0x1052
342210 +#define VALUE_RGMII1_RXCK 0x1032
342211 +#define VALUE_RGMII1_RXD0 0x1032
342212 +#define VALUE_RGMII1_RXD1 0x1032
342213 +#define VALUE_RGMII1_RXD2 0x1032
342214 +#define VALUE_RGMII1_RXD3 0x1032
342215 +#define VALUE_RGMII1_RXDV 0x1032
342218 +#define VALUE_RMII0_CLK 0x1052
342219 +#define VALUE_RMII0_TXD0 0x1051
342220 +#define VALUE_RMII0_TXD1 0x1051
342221 +#define VALUE_RMII0_TXEN 0x1051
342222 +#define VALUE_RMII0_RXD0 0x1031
342223 +#define VALUE_RMII0_RXD1 0x1031
342224 +#define VALUE_RMII0_RXDV 0x1031
342227 +#define VALUE_RMII1_CLK 0x1053
342228 +#define VALUE_RMII1_TXD0 0x1052
342229 +#define VALUE_RMII1_TXD1 0x1052
342230 +#define VALUE_RMII1_TXEN 0x1052
342231 +#define VALUE_RMII1_RXD0 0x1032
342232 +#define VALUE_RMII1_RXD1 0x1032
342233 +#define VALUE_RMII1_RXDV 0x1032
342250 + return 0;
342351 + return 0;
342373 @@ -0,0 +1,280 @@
342402 +#define PHY_ADDR_MDCK0 0x017C70138
342403 +#define PHY_ADDR_MDIO0 0x017C7013C
342405 +#define PHY_ADDR_MDCK1 0x017C701E0
342406 +#define PHY_ADDR_MDIO1 0x017C70200
342409 +#define PHY_ADDR_EPHY0_CLK 0x017C7011C
342410 +#define PHY_ADDR_EPHY0_RSTN 0x017C7014C
342412 +#define PHY_ADDR_EPHY1_CLK 0x017C701F0
342413 +#define PHY_ADDR_EPHY1_RSTN 0x017C701DC
342416 +#define PHY_ADDR_RGMII0_TXCKOUT 0x017C7012C
342417 +#define PHY_ADDR_RGMII0_TXD0 0x017C70114
342418 +#define PHY_ADDR_RGMII0_TXD1 0x017C70118
342419 +#define PHY_ADDR_RGMII0_TXD2 0x017C70120
342420 +#define PHY_ADDR_RGMII0_TXD3 0x017C70124
342421 +#define PHY_ADDR_RGMII0_TXEN 0x017C70128
342422 +#define PHY_ADDR_RGMII0_RXCK 0x017C70154
342423 +#define PHY_ADDR_RGMII0_RXD0 0x017C70144
342424 +#define PHY_ADDR_RGMII0_RXD1 0x017C70140
342425 +#define PHY_ADDR_RGMII0_RXD2 0x017C70134
342426 +#define PHY_ADDR_RGMII0_RXD3 0x017C70130
342427 +#define PHY_ADDR_RGMII0_RXDV 0x017C70150
342430 +#define PHY_ADDR_RGMII1_TXCKOUT 0x017C70218
342431 +#define PHY_ADDR_RGMII1_TXD0 0x017C7020C
342432 +#define PHY_ADDR_RGMII1_TXD1 0x017C70214
342433 +#define PHY_ADDR_RGMII1_TXD2 0x017C701F4
342434 +#define PHY_ADDR_RGMII1_TXD3 0x017C70208
342435 +#define PHY_ADDR_RGMII1_TXEN 0x017C70210
342436 +#define PHY_ADDR_RGMII1_RXCK 0x017C701EC
342437 +#define PHY_ADDR_RGMII1_RXD0 0x017C701E4
342438 +#define PHY_ADDR_RGMII1_RXD1 0x017C70204
342439 +#define PHY_ADDR_RGMII1_RXD2 0x017C701FC
342440 +#define PHY_ADDR_RGMII1_RXD3 0x017C701F8
342441 +#define PHY_ADDR_RGMII1_RXDV 0x017C701E8
342444 +#define PHY_ADDR_RMII0_CLK 0x017C7012C
342445 +#define PHY_ADDR_RMII0_TXD0 0x017C70114
342446 +#define PHY_ADDR_RMII0_TXD1 0x017C70118
342447 +#define PHY_ADDR_RMII0_TXEN 0x017C70128
342448 +#define PHY_ADDR_RMII0_RXD0 0x017C70144
342449 +#define PHY_ADDR_RMII0_RXD1 0x017C70140
342450 +#define PHY_ADDR_RMII0_RXDV 0x017C70150
342453 +#define PHY_ADDR_RMII1_CLK 0x017C70218
342454 +#define PHY_ADDR_RMII1_TXD0 0x017C7020C
342455 +#define PHY_ADDR_RMII1_TXD1 0x017C70214
342456 +#define PHY_ADDR_RMII1_TXEN 0x017C70210
342457 +#define PHY_ADDR_RMII1_RXD0 0x017C701E4
342458 +#define PHY_ADDR_RMII1_RXD1 0x017C70204
342459 +#define PHY_ADDR_RMII1_RXDV 0x017C701E8
342462 +#define VALUE_MDCK0 0x1002
342463 +#define VALUE_MDIO0 0x1002
342465 +#define VALUE_MDCK1 0x1022
342466 +#define VALUE_MDIO1 0x1032
342469 +#define VALUE_EPHY0_CLK 0x1012
342470 +#define VALUE_EPHY0_RSTN 0x1002
342472 +#define VALUE_EPHY1_CLK 0x1002
342473 +#define VALUE_EPHY1_RSTN 0x1002
342476 +#define VALUE_RGMII0_TXCKOUT 0x1042
342477 +#define VALUE_RGMII0_TXD0 0x1052
342478 +#define VALUE_RGMII0_TXD1 0x1052
342479 +#define VALUE_RGMII0_TXD2 0x1052
342480 +#define VALUE_RGMII0_TXD3 0x1052
342481 +#define VALUE_RGMII0_TXEN 0x1052
342482 +#define VALUE_RGMII0_RXCK 0x1002
342483 +#define VALUE_RGMII0_RXD0 0x1002
342484 +#define VALUE_RGMII0_RXD1 0x1002
342485 +#define VALUE_RGMII0_RXD2 0x1002
342486 +#define VALUE_RGMII0_RXD3 0x1002
342487 +#define VALUE_RGMII0_RXDV 0x1002
342490 +#define VALUE_RGMII1_TXCKOUT 0x1042
342491 +#define VALUE_RGMII1_TXD0 0x1052
342492 +#define VALUE_RGMII1_TXD1 0x1052
342493 +#define VALUE_RGMII1_TXD2 0x1052
342494 +#define VALUE_RGMII1_TXD3 0x1052
342495 +#define VALUE_RGMII1_TXEN 0x1052
342496 +#define VALUE_RGMII1_RXCK 0x1032
342497 +#define VALUE_RGMII1_RXD0 0x1032
342498 +#define VALUE_RGMII1_RXD1 0x1032
342499 +#define VALUE_RGMII1_RXD2 0x1032
342500 +#define VALUE_RGMII1_RXD3 0x1032
342501 +#define VALUE_RGMII1_RXDV 0x1032
342504 +#define VALUE_RMII0_CLK 0x1053
342505 +#define VALUE_RMII0_TXD0 0x1052
342506 +#define VALUE_RMII0_TXD1 0x1052
342507 +#define VALUE_RMII0_TXEN 0x1052
342508 +#define VALUE_RMII0_RXD0 0x1032
342509 +#define VALUE_RMII0_RXD1 0x1032
342510 +#define VALUE_RMII0_RXDV 0x1032
342513 +#define VALUE_RMII1_CLK 0x1053
342514 +#define VALUE_RMII1_TXD0 0x1052
342515 +#define VALUE_RMII1_TXD1 0x1052
342516 +#define VALUE_RMII1_TXEN 0x1052
342517 +#define VALUE_RMII1_RXD0 0x1032
342518 +#define VALUE_RMII1_RXD1 0x1032
342519 +#define VALUE_RMII1_RXDV 0x1032
342536 + return 0;
342637 + return 0;
342659 @@ -0,0 +1,489 @@
342688 +#define MDIO_RWCTRL 0x00
342689 +#define MDIO_RO_DATA 0x04
342695 +#define BIT_MASK_FEPHY_ADDR GENMASK(4, 0)
342699 +#define BIT_OFFSET_LD_SET 0
342705 +#define BIT_OFFSET_R_TUNING 0
342706 +#define DEF_LD_AM 0x9
342707 +#define DEF_LDO_AM 0x3
342708 +#define DEF_R_TUNING 0x16
342714 +#define MII_EXPMD 0x1d
342715 +#define MII_EXPMA 0x1e
342717 +#define REG_LD_AM 0x3050
342718 +#define BIT_MASK_LD_SET GENMASK(4, 0)
342719 +#define REG_LDO_AM 0x3051
342720 +#define BIT_MASK_LDO_SET GENMASK(2, 0)
342721 +#define REG_R_TUNING 0x3052
342722 +#define BIT_MASK_R_TUNING GENMASK(5, 0)
342723 +#define REG_WR_DONE 0x3053
342724 +#define BIT_CFG_DONE BIT(0)
342726 +#define REG_DEF_ATE 0x3057
342727 +#define BIT_AUTOTRIM_DONE BIT(0)
342775 + return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
342841 + if (addr < 0) {
342974 + pr_err("festa PHY 0x3053 bit CFG_ACK value: 1\n");
342984 + pr_err("festa PHY 0x3053 wait bit CFG_ACK timeout!\n");
342988 + pr_info("FEPHY:addr=%d, la_am=0x%x, ldo_am=0x%x, r_tuning=0x%x\n",
343034 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343107 + return 0;
343126 + return 0;
343154 @@ -0,0 +1,256 @@
343194 +#define MDIO_SINGLE_CMD 0x00
343195 +#define MDIO_SINGLE_DATA 0x04
343196 +#define MDIO_RDATA_STATUS 0x10
343235 + /* if read data is invalid, we just return 0 instead of -EAGAIN.
343239 + return 0;
343265 + /* write 0 to cancel reset */
343270 + /* RST_BIT, write 0 to reset phy, write 1 to cancel reset */
343278 + /* write 0 to cancel reset */
343285 +#define GPIO_BASE_ETH_PHY_RESET 0x20140000
343293 + val = readl(gpio_base + 0x400);
343295 + writel(val, gpio_base + 0x400);
343298 + writel(0xFF, gpio_base + (4 << GPIO_BIT_ETH_PHY_RESET));
343301 + /* Set to 0 to reset, then sleep 200ms */
343302 + writel(0x0, gpio_base + (4 << GPIO_BIT_ETH_PHY_RESET));
343306 + writel(0xFF, gpio_base + (4 << GPIO_BIT_ETH_PHY_RESET));
343337 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343370 + return 0;
343388 + return 0;
343416 @@ -0,0 +1,32 @@
343444 + return 0;
343476 + return 0;
343488 #define RTL8211F_INSR 0x1d
343498 #define RTL8201F_ISR 0x1e
343500 if (ret < 0)
343520 /* alternative VLAN for IP session 0 if not untagged */
343559 @@ -0,0 +1,27 @@
343592 @@ -0,0 +1,8 @@
343606 @@ -0,0 +1,96 @@
343708 @@ -0,0 +1,985 @@
343762 + } while (0)
343773 + } while (0)
343778 +#define __256MB__ 0x10000000
343779 +#define __128MB__ 0x8000000
343780 +#define __4KB__ 0x1000
343781 +#define __8KB__ 0x2000
343782 +#define __16KB__ 0x4000
343806 + pcie_controller_0 = 0,
343855 +#define msi_contrl_interrupt 0x830
343856 +#define MSI_CTRL_UPPER_ADDR_OFF 0x824
343857 +#define MSI_CTRL_ADDR_OFF 0x820
343858 +#define MSI_CTRL_INT_EN_OFF0 0x828
343859 +#define MSI_CTRL_INT_EN_OFF1 0x834
343860 +#define MSI_CTRL_INT_EN_OFF2 0x840
343861 +#define MSI_CTRL_INT_EN_OFF3 0x84c
343862 +#define MSI_CTRL_INT_EN_OFF4 0x858
343863 +#define MSI_CTRL_INT_EN_OFF5 0x864
343864 +#define MSI_CTRL_INT_EN_OFF6 0x870
343865 +#define MSI_CTRL_INT_EN_OFF7 0x87c
343867 +#define PCIE0_MODE_SEL (1 << 0)
343885 + for (; i >= 0; i--) {
343895 +#define PCIE_CFG_BUS(busnr) ((busnr & 0xff) << 20)
343896 +#define PCIE_CFG_DEV(devfn) ((devfn & 0xff) << 12)
343897 +#define PCIE_CFG_REG(reg) (reg & 0xffc) /* set dword align */
343903 + unsigned long address = 0;
343921 + for (i = 0; i < 10000; i++) {
343936 + int i = 0;
343953 + i = 0;
343960 + pcie_errorvalue = 0;
343961 + val = 0xffffffff;
343965 + *value = ((val >> (((unsigned int)where & 0x3) << 3)) & 0xff);
343967 + *value = ((val >> (((unsigned int)where & 0x3) << 3)) & 0xffff);
343986 + if (devfn > 0)
343990 + ((unsigned int)where & (~0x3))));
343993 + *value = (val >> (((unsigned int)where & 0x3) << 3)) & 0xff;
343995 + *value = (val >> (((unsigned int)where & 0x3) << 3)) & 0xffff;
344024 + "bus %d, devfn %d, where 0x%x, size 0x%x, value 0x%x",
344025 + bus->number & 0xff, devfn, where, size, *value);
344057 + org &= (~(0xff << (((unsigned int)where & 0x3) << 3)));
344058 + org |= (value << (((unsigned int)where & 0x3) << 3));
344060 + org &= (~(0xffff << (((unsigned int)where & 0x3) << 3)));
344061 + org |= (value << (((unsigned int)where & 0x3) << 3));
344085 + pcie_error("Cannot read from dbi! 0x%x:0x%x:0x%x!",
344086 + 0, devfn, (unsigned int)where);
344091 + org &= (~(0xff << (((unsigned int)where & 0x3) << 3)));
344092 + org |= (value << (((unsigned int)where & 0x3) << 3));
344094 + org &= (~(0xffff << (((unsigned int)where & 0x3) << 3)));
344095 + org |= (value << (((unsigned int)where & 0x3) << 3));
344103 + ((unsigned int)where & (~0x3))));
344116 + "bus %d, devfn %d, where 0x%x, size 0x%x, value 0x%x",
344117 + bus->number & 0xff, devfn, where, size, value);
344141 + unsigned short dev_contrl_reg_val = 0;
344142 + unsigned int max_rd_req_size = 0;
344150 + max_rd_req_size = (dev_contrl_reg_val >> 12) & 0x7;
344151 + if (max_rd_req_size > 0x0) {
344173 + if (msi_irq < 0) {
344201 + if (pcie_contrl == 0)
344202 + bus_start = 0;
344204 + bus_start = 0x2;
344206 + ret = devm_of_pci_get_host_bridge_resources(&pdev->dev, bus_start, 0xff, &res,
344235 + return 0;
344257 + if (pcie_contrl == 0)
344258 + bus_start = 0;
344262 + ret = devm_of_pci_get_host_bridge_resources(&pdev->dev, bus_start, 0xff, &res, &io_addr);
344292 + return 0;
344339 + unsigned int processed = 0;
344343 + for (i = 0; i < 8; i++) {
344344 + unsigned long reg = readl(dbi_base + 0x830 + i * 0xc);
344352 + writel(1 << offset, dbi_base + msi_contrl_interrupt + i * 0xc);
344369 + reg = readl(dbi_base + msi_contrl_interrupt + i * 0xc);
344373 + return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
344384 + if (pdev->bus->number == pcie_info[0].root_bus_nr ||
344386 + return 0;
344389 + if (hwirq < 0)
344400 + desc->msi_attrib.multiple = 0x5;
344408 + return 0;
344416 + irq_hw_number_t hwirq = 0;
344439 + return 0;
344476 + if (err < 0) {
344485 + if (err < 0) {
344491 + msi->pages = __get_free_pages(GFP_KERNEL, 0);
344498 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF0);
344499 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF1);
344500 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF2);
344501 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF3);
344502 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF4);
344503 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF5);
344504 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF6);
344505 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF7);
344507 + return 0;
344522 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF0);
344523 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF1);
344524 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF2);
344525 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF3);
344526 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF4);
344527 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF5);
344528 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF6);
344529 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF7);
344531 + free_pages(msi->pages, 0);
344533 + if (msi->irq > 0)
344536 + for (i = 0; i < HISI_PCI_MSI_NR; i++) {
344538 + if (irq > 0)
344544 + return 0;
344602 + if (err < 0) {
344618 + return 0;
344636 + return 0;
344644 + return 0;
344648 + return 0;
344655 + return 0;
344699 @@ -0,0 +1,281 @@
344727 + .viewport = 0,
344728 + .region_ctrl_1 = 0x00000004,
344729 + .region_ctrl_2 = 0x90000000,
344731 + .ubar = 0x0,
344733 + .ltar = 0x01000000,
344734 + .utar = 0x00000000,
344738 + .region_ctrl_1 = 0x00000005,
344739 + .region_ctrl_2 = 0x90000000,
344741 + .ubar = 0x0,
344743 + .ltar = 0x02000000,
344744 + .utar = 0x00000000,
344756 + for (i = 0; i < table_size; i++) {
344757 + writel((ptable + i)->viewport, config_base + 0x900);
344758 + writel((ptable + i)->lbar, config_base + 0x90c);
344759 + writel((ptable + i)->ubar, config_base + 0x910);
344760 + writel((ptable + i)->lar, config_base + 0x914);
344761 + writel((ptable + i)->ltar, config_base + 0x918);
344762 + writel((ptable + i)->utar, config_base + 0x91c);
344763 + writel((ptable + i)->region_ctrl_1, config_base + 0x904);
344764 + writel((ptable + i)->region_ctrl_2, config_base + 0x908);
344774 + && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
344819 + "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
344849 + return 0;
344897 + val &= (~(0xf << PCIE_DEVICE_TYPE));
344917 + val &= ~(0xffffff00);
344918 + val |= (0x60400 << 8);
344936 + writel(0x1, dbi_base + 0x8BC);
344937 + val = readl(dbi_base + 0x7C);
344938 + val = ((val >> 4) << 4) | 0x1;
344939 + writel(val, dbi_base + 0x7C);
344944 + return 0;
344986 @@ -0,0 +1,64 @@
345007 +#define MISC_CTRL_BASE 0x04528000
345008 +#define PCIE_MEM_BASE 0x18000000
345009 +#define PCIE_EP_CONF_BASE 0x10000000
345010 +#define PCIE_DBI_BASE 0x0EFF0000
345011 +#define PERI_CRG_BASE 0x04510000
345013 +#define PERI_CRG99 0x18C
345020 +#define PCIE_PAD_OE_MASK (0x7 << 8)
345022 +#define PCIE_SYS_CTRL0 0xC00
345024 +#define PCIE_WM_EP 0x0
345025 +#define PCIE_WM_LEGACY 0x1
345026 +#define PCIE_WM_RC 0x4
345028 +#define PCIE_SYS_CTRL7 0xC1C
345032 +#define PCIE_SYS_STATE0 0xF00
345056 @@ -0,0 +1,611 @@
345083 + .viewport = 0, /* iAtu Vierport Register */
345084 + .region_ctrl_1 = 0x00000004, /* Region Control 1 Register */
345085 + .region_ctrl_2 = 0x90000000, /* Region Control 2 Register */
345087 + .ubar = 0x0, /* Upper Base Address Register */
345089 + .ltar = 0x01000000, /* Lower Target Address Register */
345090 + .utar = 0x00000000, /* Upper Target Address Register */
345094 + .region_ctrl_1 = 0x00000005, /* Region Control 1 Register */
345095 + .region_ctrl_2 = 0x90000000, /* Region Control 2 Register */
345097 + .ubar = 0x0, /* Upper Base Address Register */
345099 + .ltar = 0x02000000, /* Lower Target Address Register */
345100 + .utar = 0x00000000, /* Upper Target Address Register */
345106 + .viewport = 0, /* iAtu Vierport Register */
345107 + .region_ctrl_1 = 0x00000004, /* Region Control 1 Register */
345108 + .region_ctrl_2 = 0x90000000, /* Region Control 2 Register */
345110 + .ubar = 0x0, /* Upper Base Address Register */
345112 + .ltar = 0x01000000, /* Lower Target Address Register */
345113 + .utar = 0x00000000, /* Upper Target Address Register */
345117 + .region_ctrl_1 = 0x00000005, /* Region Control 1 Register */
345118 + .region_ctrl_2 = 0x90000000, /* Region Control 2 Register */
345120 + .ubar = 0x0, /* Upper Base Address Register */
345122 + .ltar = 0x02000000, /* Lower Target Address Register */
345123 + .utar = 0x00000000, /* Upper Target Address Register */
345149 + for (i = 0; i < table_size; i++) {
345167 + && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
345174 + unsigned int sys_ctrl_base = 0;
345183 + return 0;
345201 + case 0x2:
345202 + case 0x4:
345206 + case 0x0:
345207 + case 0x1:
345208 + case 0x3:
345213 + port_nr = 0;
345225 + unsigned int pcie_mem_size = 0;
345226 + unsigned int pcie_cfg_size = 0;
345228 + unsigned int pcie_ep_conf_base = 0;
345229 + unsigned int pcie_contrl = 0;
345230 + int nr = 0;
345231 + int err = 0;
345250 + pr_err("Pcie port number: 0\n");
345251 + *controllers_nr = 0;
345255 + if ((nr == 1) && pcie_controllers_nr == 0) {
345256 + pr_err("Pcie controler 0 is disabled by comphy config!\n");
345276 + "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
345307 + return 0;
345325 +#define PCIE0_CLK_SRST_CTRL 0x3A40
345326 +#define PCIE1_CLK_SRST_CTRL 0x3A60
345333 + reg_val |= (0x1 << PCIE_TST_SRST_REQ_SEL);
345342 + reg_val |= (0x1 << PCIE_TST_SRST_REQ_SEL);
345346 +#define PHY1_PORTA_CLK_SRST_CTRL 0x3B70
345347 +#define PHY1_PORTB_CLK_SRST_CTRL 0x3B90
345348 +#define PHY2_PORTA_CLK_SRST_CTRL 0x3BB0
345349 +#define PHY2_PORTB_CLK_SRST_CTRL 0x3BD0
345356 + reg_val &= ~(0x1 << PHY_TST_SRST_REQ);
345365 + reg_val &= ~(0x1 << PHY_TST_SRST_REQ);
345374 + reg_val &= ~(0x1 << PHY_TST_SRST_REQ);
345383 + reg_val &= ~(0x1 << PHY_TST_SRST_REQ);
345387 +#define PHY1_PARA_SET_REG 0x1cc
345388 +#define PHY2_PARA_SET_REG 0x1d0
345391 + writel(0x11100, misc_base + PHY1_PARA_SET_REG);
345393 + writel(0x11101, misc_base + PHY1_PARA_SET_REG);
345395 + writel(0x11100, misc_base + PHY1_PARA_SET_REG);
345396 + writel(0x0, misc_base + PHY1_PARA_SET_REG);
345401 + writel(0x19100, misc_base + PHY1_PARA_SET_REG);
345403 + writel(0x19101, misc_base + PHY1_PARA_SET_REG);
345405 + writel(0x19100, misc_base + PHY1_PARA_SET_REG);
345406 + writel(0x0, misc_base + PHY1_PARA_SET_REG);
345411 + writel(0x11100, misc_base + PHY2_PARA_SET_REG);
345413 + writel(0x11101, misc_base + PHY2_PARA_SET_REG);
345415 + writel(0x11100, misc_base + PHY2_PARA_SET_REG);
345416 + writel(0x0, misc_base + PHY2_PARA_SET_REG);
345421 + writel(0x19100, misc_base + PHY2_PARA_SET_REG);
345423 + writel(0x19101, misc_base + PHY2_PARA_SET_REG);
345425 + writel(0x19100, misc_base + PHY2_PARA_SET_REG);
345426 + writel(0x0, misc_base + PHY2_PARA_SET_REG);
345429 +#define MISC_REG_BASE 0x11024000
345435 + misc_base_addr = ioremap(MISC_REG_BASE, 0x200);
345444 + case 0:
345504 + unsigned int pcie_clk_rst_reg = 0;
345554 + val &= (~(0xf << PCIE_DEVICE_TYPE));
345582 + val &= ~(0xffffff00);
345583 + val |= (0x60400 << 8);
345616 + return 0;
345621 + unsigned int val = 0;
345622 + unsigned int pcie_clk_rst_reg = 0;
345673 @@ -0,0 +1,69 @@
345693 +#define PCIE_EP_CONF_BASE 0x20000000
345694 +#define PCIE_EP1_CONF_BASE 0x30000000
345696 +#define PERI_CRG_BASE 0x11010000
345704 +#define PCIE_PAD_OE_MASK (0x7 << 8)
345706 +#define PCIE_SYS_CTRL0 0xc00
345708 +#define PCIE_WM_EP 0x0
345709 +#define PCIE_WM_LEGACY 0x1
345710 +#define PCIE_WM_RC 0x4
345712 +#define PCIE_SYS_CTRL7 0xc1C
345715 +#define PCIE_SYS_CTRL32 0xc80
345718 +#define PCIE_SYS_STATE0 0xf00
345727 +#define REG_SC_STAT 0x0018
345728 +#define PCI_CARD 0x44
345731 +#define PCIE_MODE_MASK 0x7
345733 +#define ATU_VIEWPORT_REG 0x900
345734 +#define ATU_REGION_CTRL1_REG 0x904
345735 +#define ATU_REGION_CTRL2_REG 0x908
345736 +#define ATU_BASE_LOW_REG 0x90c
345737 +#define ATU_BASE_HIGH_REG 0x910
345738 +#define ATU_LIMIT_REG 0x914
345739 +#define ATU_TARGET_LOW_REG 0x918
345740 +#define ATU_ATRGET_HIGH_REG 0x91c
345748 @@ -0,0 +1,479 @@
345775 + .viewport = 0, /* iAtu Vierport Register */
345776 + .region_ctrl_1 = 0x00000004, /* Region Control 1 Register */
345777 + .region_ctrl_2 = 0x90000000, /* Region Control 2 Register */
345779 + .ubar = 0x0, /* Upper Base Address Register */
345781 + .ltar = 0x01000000, /* Lower Target Address Register */
345782 + .utar = 0x00000000, /* Upper Target Address Register */
345786 + .region_ctrl_1 = 0x00000005, /* Region Control 1 Register */
345787 + .region_ctrl_2 = 0x90000000, /* Region Control 2 Register */
345789 + .ubar = 0x0, /* Upper Base Address Register */
345791 + .ltar = 0x02000000, /* Lower Target Address Register */
345792 + .utar = 0x00000000, /* Upper Target Address Register */
345805 + for (i = 0; i < table_size; i++) {
345823 + && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
345830 + unsigned int sys_ctrl_base = 0;
345839 + return 0;
345857 + case 0x0:
345858 + case 0x1:
345863 + port_nr = 0;
345875 + unsigned int pcie_mem_size = 0;
345876 + unsigned int pcie_cfg_size = 0;
345878 + unsigned int pcie_ep_conf_base = 0;
345879 + unsigned int pcie_contrl = 0;
345880 + int nr = 0;
345881 + int err = 0;
345900 + pr_err("Pcie port number: 0\n");
345901 + *controllers_nr = 0;
345921 + "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
345952 + return 0;
345970 +#define PCIE0_CLK_SRST_CTRL 0x3A40
345977 + reg_val |= (0x1 << PCIE_TST_SRST_REQ_SEL);
345981 +#define PHY1_PORTA_CLK_SRST_CTRL 0x3B70
345982 +#define PHY1_PORTB_CLK_SRST_CTRL 0x3B90
345989 + reg_val &= ~(0x1 << PHY_TST_SRST_REQ);
345998 + reg_val &= ~(0x1 << PHY_TST_SRST_REQ);
346002 +#define PHY1_PARA_SET_REG 0x1cc
346005 + writel(0x11100, misc_base + PHY1_PARA_SET_REG);
346007 + writel(0x11101, misc_base + PHY1_PARA_SET_REG);
346009 + writel(0x11100, misc_base + PHY1_PARA_SET_REG);
346010 + writel(0x0, misc_base + PHY1_PARA_SET_REG);
346015 + writel(0x19100, misc_base + PHY1_PARA_SET_REG);
346017 + writel(0x19101, misc_base + PHY1_PARA_SET_REG);
346019 + writel(0x19100, misc_base + PHY1_PARA_SET_REG);
346020 + writel(0x0, misc_base + PHY1_PARA_SET_REG);
346023 +#define MISC_REG_BASE 0x11024000
346029 + misc_base_addr = ioremap(MISC_REG_BASE, 0x200);
346038 + case 0:
346064 + unsigned int pcie_clk_rst_reg = 0;
346114 + val &= (~(0xf << PCIE_DEVICE_TYPE));
346142 + val &= ~(0xffffff00);
346143 + val |= (0x60400 << 8);
346176 + return 0;
346181 + unsigned int val = 0;
346182 + unsigned int pcie_clk_rst_reg = 0;
346233 @@ -0,0 +1,389 @@
346264 + .viewport = 0,
346265 + .region_ctrl_1 = 0x00000004,
346266 + .region_ctrl_2 = 0x90000000,
346268 + .ubar = 0x0,
346270 + .ltar = 0x01000000,
346271 + .utar = 0x00000000,
346275 + .region_ctrl_1 = 0x00000005,
346276 + .region_ctrl_2 = 0x90000000,
346278 + .ubar = 0x0,
346280 + .ltar = 0x02000000,
346281 + .utar = 0x00000000,
346293 + for (i = 0; i < table_size; i++) {
346294 + writel((ptable + i)->viewport, config_base + 0x900);
346295 + writel((ptable + i)->lbar, config_base + 0x90c);
346296 + writel((ptable + i)->ubar, config_base + 0x910);
346297 + writel((ptable + i)->lar, config_base + 0x914);
346298 + writel((ptable + i)->ltar, config_base + 0x918);
346299 + writel((ptable + i)->utar, config_base + 0x91c);
346300 + writel((ptable + i)->region_ctrl_1, config_base + 0x904);
346301 + writel((ptable + i)->region_ctrl_2, config_base + 0x908);
346311 + && (val & (1 << PCIE_RDLH_LINK_UP))) ? 1 : 0;
346327 + return 0;
346331 + mode = (val >> 12) & 0x3;
346333 + case 0x1:
346337 + case 0x0:
346342 + nr = 0;
346368 + pr_err("Pcie port number: 0\n");
346369 + *controllers_nr = 0;
346375 + "Invalid parameter: pcie mem size[0x%x], pcie cfg size[0x%x]!",
346380 + info->controller = 0;
346399 + return 0;
346446 + if ((val & (0x3 << PCIE_MODE)) == 0) {
346449 + val |= (0x1 << phy1_srs_req_sel) | (0x1 << phy0_srs_req_sel);
346455 + val |= ((0x1 << phy1_srs_req) | (0x1 << phy0_srs_req));
346461 + val &= ((~(0x1 << phy1_srs_req)) & (~(0x1 << phy0_srs_req)));
346467 + writel(0x90f, misc_base + MISC_CTRL5);
346468 + writel(0x94f, misc_base + MISC_CTRL5);
346469 + writel(0x90f, misc_base + MISC_CTRL5);
346470 + writel(0x0, misc_base + MISC_CTRL5);
346471 + writel(0x92f, misc_base + MISC_CTRL5);
346472 + writel(0x96f, misc_base + MISC_CTRL5);
346473 + writel(0x92f, misc_base + MISC_CTRL5);
346474 + writel(0x0, misc_base + MISC_CTRL5);
346480 + writel(0xd11, misc_base + MISC_CTRL5);
346481 + writel(0xd51, misc_base + MISC_CTRL5);
346482 + writel(0xd11, misc_base + MISC_CTRL5);
346483 + writel(0x0, misc_base + MISC_CTRL5);
346484 + writel(0xd31, misc_base + MISC_CTRL5);
346485 + writel(0xd71, misc_base + MISC_CTRL5);
346486 + writel(0xd31, misc_base + MISC_CTRL5);
346487 + writel(0x0, misc_base + MISC_CTRL5);
346492 + val |= (0x1 << phy0_srs_req_sel);
346498 + val |= (0x1 << phy0_srs_req);
346504 + val &= ~(0x1 << phy0_srs_req);
346510 + writel(0x90f, misc_base + MISC_CTRL5);
346511 + writel(0x94f, misc_base + MISC_CTRL5);
346512 + writel(0x90f, misc_base + MISC_CTRL5);
346513 + writel(0x0, misc_base + MISC_CTRL5);
346519 + writel(0xd11, misc_base + MISC_CTRL5);
346520 + writel(0xd51, misc_base + MISC_CTRL5);
346521 + writel(0xd11, misc_base + MISC_CTRL5);
346522 + writel(0x0, misc_base + MISC_CTRL5);
346530 + val &= (~(0xf << PCIE_DEVICE_TYPE));
346558 + val &= ~(0xffffff00);
346559 + val |= (0x60400 << 8);
346577 + writel(0x1, dbi_base + 0x8BC);
346578 + val = readl(dbi_base + 0x7C);
346579 + val = ((val >> 4) << 4) | 0x1;
346580 + writel(val, dbi_base + 0x7C);
346585 + return 0;
346628 @@ -0,0 +1,79 @@
346649 +#define SYS_CTRL_BASE 0x12020000
346650 +#define MISC_CTRL_BASE 0x12030000
346651 +#define PCIE_MEM_BASE 0x30000000
346652 +#define PCIE_EP_CONF_BASE 0x20000000
346653 +#define PCIE_DBI_BASE 0x12200000
346654 +#define PERI_CRG_BASE 0x12010000
346656 +#define SYS_SATA 0x8c
346659 +#define PERI_CRG98 0x188
346660 +#define phy0_srs_req 0
346665 +#define PERI_CRG99 0x18c
346672 +#define PCIE_PAD_OE_MASK (0x7 << 8)
346674 +#define PCIE_SYS_CTRL0 0xc00
346676 +#define PCIE_WM_EP 0x0
346677 +#define PCIE_WM_LEGACY 0x1
346678 +#define PCIE_WM_RC 0x4
346680 +#define PCIE_SYS_CTRL7 0xc1C
346683 +#define PCIE_SYS_STATE0 0xf00
346700 +#define MISC_CTRL33 0x128
346701 +#define COM_PHY_TEST_VAL1 ((0x1 << 11) | (0x1))
346702 +#define COM_PHY_TEST_VAL2 ((0x1 << 6) | (0x1 << 11) | (0x1))
346704 +#define REG_SC_STAT 0x008c
346705 +#define PCI_CARD 0x44
346706 +#define MISC_CTRL5 0x14
346725 + dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
346727 return 0;
346758 @@ -0,0 +1,23 @@
346769 + int "Hisi sata interworking speed mode(1.5G:0/3G:1/6G:2)"
346787 @@ -0,0 +1,5 @@
346798 @@ -0,0 +1,681 @@
346821 +#define HISI_SATA_PHY0_CTLL 0xA0
346822 +#define HISI_SATA_PHY0_CTLH 0xA4
346823 +#define HISI_SATA_PHY1_CTLL 0xAC
346824 +#define HISI_SATA_PHY1_CTLH 0xB0
346826 +#define HISI_SATA_PORT_FIFOTH 0x44
346827 +#define HISI_SATA_PORT_PHYCTL1 0x70
346828 +#define HISI_SATA_PORT_PHYCTL2 0x74
346829 +#define HISI_SATA_PORT_PHYCTL3 0x78
346831 +#define HISI_SYS_CTRL_REG_BASE 0x11020000
346832 +#define HISI_SYS_STAT_REG 0x0018
346833 +#define HISI_SYS_CTRL_REG_MAP_SIZE 0x1000
346834 +#define GET_UPS_MODE_VAL(reg_val) (((reg_val) >> 16) & 0x7)
346836 +#define SATA_PHY_CTRL0 0x140
346837 +#define SATA_PHY_CTRL1 0x144
346845 +#define HISI_MISC_REG_BASE 0x11024000
346846 +#define HISI_MISC_REG_MAP_SIZE 0x1000
346848 +#define HISI_COMB_PHY1_TEST_CTRL 0x1c8
346850 +#define HISI_CRG_REG_BASE 0x11010000
346852 +#define SATA_CLK_RST_CTRL_1_REG 0x3B40
346853 +#define SATA_CLK_RST_CTRL_2_REG 0x3B48
346855 +#define HISI_SATA_CKO_ALIVE_SRST_REQ BIT(0)
346857 +#define HISI_SATA_BUS_SRST_REQ BIT(0)
346860 +#define SATA_PHY0_CLK_RST_REG 0x3B60
346861 +#define SATA_PHY1_CLK_RST_REG 0x3B80
346863 +#define SATA_CTRL_RXn_RST BIT(0)
346868 +#define COMB_PHY1_PORT_A_REG 0x3B70
346869 +#define COMB_PHY1_PORT_B_REG 0x3B90
346871 +#define COMB_PHY_REST BIT(0)
346877 +#define SATA_CRG_MAP_SIZE 0x100
346880 + FIFOTH_VALUE = 0xdffeffff,
346881 + FIFOTH_VALUE2 = 0x92000047,
346882 + PHY_VALUE = 0x4900003d,
346883 + PHYCTL2_VALUE = 0x60555,
346885 + PORT_BIGENDINE = 0x82e5cb8,
346887 + PX_TX_AMPLITUDE = 0x36089,
346888 + PX_TX_DEEMPH = 0x489186,
346890 + PHY_SG_1_5G = 0xe000030,
346891 + PHY_SG_3G = 0xe200030,
346892 + PHY_SG_6G = 0xe400030,
346907 + reg_val = readl(crg_base + 0x20);
346909 + writel(reg_val, crg_base + 0x20);
346916 + reg_val = readl(crg_base + 0x20);
346918 + writel(reg_val, crg_base + 0x20);
346925 + reg_val = readl(crg_base + 0x40);
346927 + writel(reg_val, crg_base + 0x40);
346934 + reg_val = readl(crg_base + 0x40);
346936 + writel(reg_val, crg_base + 0x40);
346961 + case 0:
346962 + reg_val = readl(crg_base + 0x20);
346964 + writel(reg_val, crg_base + 0x20);
346971 + reg_val = readl(crg_base + 0x40);
346973 + writel(reg_val, crg_base + 0x40);
346975 + reg_val = readl(comb_phy_crg_base + 0x20);
346977 + writel(reg_val, comb_phy_crg_base + 0x20);
347008 + case 0:
347009 + reg_val = readl(crg_base + 0x20);
347011 + writel(reg_val, crg_base + 0x20);
347018 + reg_val = readl(crg_base + 0x40);
347020 + writel(reg_val, crg_base + 0x40);
347022 + reg_val = readl(comb_phy_crg_base + 0x20);
347024 + writel(reg_val, comb_phy_crg_base + 0x20);
347053 + reg_val = readl(crg_base + 0x8);
347055 + writel(reg_val, crg_base + 0x8);
347095 + reg_val = readl(crg_base + 0x8);
347097 + writel(reg_val, crg_base + 0x8);
347106 + reg_val = readl(crg_base + 0x20);
347108 + writel(reg_val, crg_base + 0x20);
347115 + reg_val = readl(crg_base + 0x20);
347117 + writel(reg_val, crg_base + 0x20);
347197 + reg_val = readl(crg_base + 0x20);
347199 + writel(reg_val, crg_base + 0x20);
347206 + reg_val = readl(crg_base + 0x40);
347208 + writel(reg_val, crg_base + 0x40);
347237 + reg_val = readl(crg_base + 0x8);
347239 + writel(reg_val, crg_base + 0x8);
347258 + reg_val = readl(crg_base + 0x20);
347261 + writel(reg_val, crg_base + 0x20);
347305 + for (port_idx = 0; port_idx < ports_num; port_idx++) {
347306 + writel(FIFOTH_VALUE, (mmio + 0x100 + port_idx * 0x80 + PORT_FIFOTH));
347307 + writel(FIFOTH_VALUE2, (mmio + 0x100 + port_idx * 0x80 + PORT_FIFOTH2));
347315 + writel(0x88200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347316 + writel(0x88201, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347317 + writel(0x88200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347318 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347320 + writel(0x48700, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347321 + writel(0x48701, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347322 + writel(0x48700, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347323 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347325 + writel(0x58300, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347326 + writel(0x58301, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347327 + writel(0x58300, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347328 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347330 + writel(0x19100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347331 + writel(0x19101, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347332 + writel(0x19100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347333 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347335 + writel(0xC08C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347336 + writel(0xC08C01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347337 + writel(0xC08C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347338 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347340 + writel(0xd88d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347341 + writel(0xd88d01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347342 + writel(0xd88d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347343 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347348 + writel(0x80200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347349 + writel(0x80201, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347350 + writel(0x80200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347351 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347353 + writel(0x40700, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347354 + writel(0x40701, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347355 + writel(0x40700, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347356 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347358 + writel(0x50300, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347359 + writel(0x50301, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347360 + writel(0x50300, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347361 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347363 + writel(0x11100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347364 + writel(0x11101, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347365 + writel(0x11100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347366 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347368 + writel(0xC00C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347369 + writel(0xC00C01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347370 + writel(0xC00C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347371 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347373 + writel(0xd80d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347374 + writel(0xd80d01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347375 + writel(0xd80d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347376 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
347404 +#define IOCONFIG1_REG_BASE 0x10ff0000
347405 +#define IOCONFIG1_REG_MAP_SIZE 0x200
347419 + for (port_idx = 0; port_idx < ports_num; port_idx++) {
347420 + if (port_idx == 0) {
347421 + writel(0x1201, reg_addr + 0xFC);
347423 + writel(0x1201, reg_addr + 0x100);
347444 + for (port_idx = 0; port_idx < ports_num; port_idx++) {
347445 + writel(PX_TX_DEEMPH, (mmio + 0x100 + port_idx * 0x80 + HISI_SATA_PORT_PHYCTL2));
347446 + writel(PX_TX_AMPLITUDE, (mmio + 0x100 + port_idx * 0x80 +
347448 + writel(phy_config, (mmio + 0x100 + port_idx * 0x80 + HISI_SATA_PORT_PHYCTL3));
347473 + unsigned int sata_port_num = 0;
347476 + sata_port_map = 0x3;
347485 @@ -0,0 +1,1081 @@
347508 +#define HISI_SATA_PHY0_CTLL 0xA0
347509 +#define HISI_SATA_PHY0_CTLH 0xA4
347510 +#define HISI_SATA_PHY1_CTLL 0xAC
347511 +#define HISI_SATA_PHY1_CTLH 0xB0
347513 +#define HISI_SATA_PORT_FIFOTH 0x44
347514 +#define HISI_SATA_PORT_PHYCTL1 0x70
347515 +#define HISI_SATA_PORT_PHYCTL2 0x74
347516 +#define HISI_SATA_PORT_PHYCTL3 0x78
347518 +#define HISI_SYS_CTRL_REG_BASE 0x11020000
347519 +#define HISI_SYS_STAT_REG 0x0018
347520 +#define HISI_SYS_CTRL_REG_MAP_SIZE 0x1000
347521 +#define GET_UPS_MODE_VAL(reg_val) (((reg_val) >> 16) & 0x7)
347523 +#define SATA_PHY_CTRL0 0x140
347524 +#define SATA_PHY_CTRL1 0x144
347532 +#define HISI_MISC_REG_BASE 0x11024000
347533 +#define HISI_MISC_REG_MAP_SIZE 0x1000
347535 +#define HISI_COMB_PHY1_TEST_CTRL 0x1cc
347536 +#define HISI_COMB_PHY2_TEST_CTRL 0x1d0
347538 +#define HISI_CRG_REG_BASE 0x11010000
347540 +#define SATA_CLK_RST_CTRL_1_REG 0x3B40
347541 +#define SATA_CLK_RST_CTRL_2_REG 0x3B48
347543 +#define HISI_SATA_CKO_ALIVE_SRST_REQ BIT(0)
347545 +#define HISI_SATA_BUS_SRST_REQ BIT(0)
347548 +#define SATA_PHY0_CLK_RST_REG 0x3B60
347549 +#define SATA_PHY1_CLK_RST_REG 0x3B80
347550 +#define SATA_PHY2_CLK_RST_REG 0x3BA0
347551 +#define SATA_PHY3_CLK_RST_REG 0x3BC0
347553 +#define SATA_CTRL_RXn_RST BIT(0)
347558 +#define COMB_PHY1_PORT_A_REG 0x3B70
347559 +#define COMB_PHY1_PORT_B_REG 0x3B90
347560 +#define COMB_PHY2_PORT_A_REG 0x3BB0
347561 +#define COMB_PHY2_PORT_B_REG 0x3BD0
347563 +#define COMB_PHY_REST BIT(0)
347569 +#define SATA_CRG_MAP_SIZE 0x100
347572 + FIFOTH_VALUE = 0xdffeffff,
347573 + PHY_VALUE = 0x4900003d,
347574 + PHYCTL2_VALUE = 0x60555,
347576 + PORT_BIGENDINE = 0x82e5cb8,
347578 + PX_TX_AMPLITUDE = 0x36089,
347579 + PX_TX_PREEMPH = 0x486186,
347581 + PHY_SG_1_5G = 0xe000030,
347582 + PHY_SG_3G = 0xe200030,
347583 + PHY_SG_6G = 0xe400030,
347598 + reg_val = readl(crg_base + 0x20);
347600 + writel(reg_val, crg_base + 0x20);
347607 + reg_val = readl(crg_base + 0x20);
347609 + writel(reg_val, crg_base + 0x20);
347616 + reg_val = readl(crg_base + 0x40);
347618 + writel(reg_val, crg_base + 0x40);
347625 + reg_val = readl(crg_base + 0x40);
347627 + writel(reg_val, crg_base + 0x40);
347634 + reg_val = readl(crg_base + 0x60);
347636 + writel(reg_val, crg_base + 0x60);
347643 + reg_val = readl(crg_base + 0x60);
347645 + writel(reg_val, crg_base + 0x60);
347652 + reg_val = readl(crg_base + 0x80);
347654 + writel(reg_val, crg_base + 0x80);
347661 + reg_val = readl(crg_base + 0x80);
347663 + writel(reg_val, crg_base + 0x80);
347742 + case 0:
347743 + reg_val = readl(crg_base + 0x20);
347745 + writel(reg_val, crg_base + 0x20);
347747 + reg_val = readl(comb_phy_crg_base + 0x20);
347749 + writel(reg_val, comb_phy_crg_base + 0x20);
347752 + reg_val = readl(crg_base + 0x40);
347754 + writel(reg_val, crg_base + 0x40);
347761 + reg_val = readl(crg_base + 0x60);
347763 + writel(reg_val, crg_base + 0x60);
347765 + reg_val = readl(comb_phy_crg_base + 0x60);
347767 + writel(reg_val, comb_phy_crg_base + 0x60);
347771 + reg_val = readl(crg_base + 0x80);
347773 + writel(reg_val, crg_base + 0x80);
347775 + reg_val = readl(comb_phy_crg_base + 0x40);
347777 + writel(reg_val, comb_phy_crg_base + 0x40);
347812 + case 0:
347813 + reg_val = readl(crg_base + 0x20);
347815 + writel(reg_val, crg_base + 0x20);
347817 + reg_val = readl(comb_phy_crg_base + 0x20);
347819 + writel(reg_val, comb_phy_crg_base + 0x20);
347822 + reg_val = readl(crg_base + 0x40);
347824 + writel(reg_val, crg_base + 0x40);
347831 + reg_val = readl(crg_base + 0x60);
347833 + writel(reg_val, crg_base + 0x60);
347835 + reg_val = readl(comb_phy_crg_base + 0x60);
347837 + writel(reg_val, comb_phy_crg_base + 0x60);
347840 + reg_val = readl(crg_base + 0x80);
347842 + writel(reg_val, crg_base + 0x80);
347844 + reg_val = readl(comb_phy_crg_base + 0x40);
347846 + writel(reg_val, comb_phy_crg_base + 0x40);
347874 + reg_val = readl(crg_base + 0x8);
347876 + writel(reg_val, crg_base + 0x8);
347902 + reg_val = readl(crg_base + 0x8);
347904 + writel(reg_val, crg_base + 0x8);
347913 + reg_val = readl(crg_base + 0x20);
347915 + writel(reg_val, crg_base + 0x20);
347922 + reg_val = readl(crg_base + 0x20);
347924 + writel(reg_val, crg_base + 0x20);
347949 + reg_val = readl(crg_base + 0x60);
347951 + writel(reg_val, crg_base + 0x60);
347958 + reg_val = readl(crg_base + 0x60);
347960 + writel(reg_val, crg_base + 0x60);
347967 + reg_val = readl(crg_base + 0x40);
347969 + writel(reg_val, crg_base + 0x40);
347976 + reg_val = readl(crg_base + 0x40);
347978 + writel(reg_val, crg_base + 0x40);
348095 + reg_val = readl(crg_base + 0x20);
348097 + writel(reg_val, crg_base + 0x20);
348104 + reg_val = readl(crg_base + 0x40);
348106 + writel(reg_val, crg_base + 0x40);
348113 + reg_val = readl(crg_base + 0x60);
348115 + writel(reg_val, crg_base + 0x60);
348122 + reg_val = readl(crg_base + 0x80);
348124 + writel(reg_val, crg_base + 0x80);
348167 + reg_val = readl(crg_base + 0x8);
348169 + writel(reg_val, crg_base + 0x8);
348186 + reg_val = readl(crg_base + 0x20);
348189 + writel(reg_val, crg_base + 0x20);
348206 + reg_val = readl(crg_base + 0x60);
348209 + writel(reg_val, crg_base + 0x60);
348216 + reg_val = readl(crg_base + 0x40);
348219 + writel(reg_val, crg_base + 0x40);
348280 + for (port_idx = 0; port_idx < ports_num; port_idx++) {
348281 + writel(FIFOTH_VALUE, (mmio + 0x100 + port_idx * 0x80 + PORT_FIFOTH));
348288 + writel(0x88200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348289 + writel(0x88201, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348290 + writel(0x88200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348291 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348293 + writel(0x19100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348294 + writel(0x19101, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348295 + writel(0x19100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348296 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348298 + writel(0xC08C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348299 + writel(0xC08C01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348300 + writel(0xC08C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348301 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348303 + writel(0xd88d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348304 + writel(0xd88d01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348305 + writel(0xd88d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348306 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348311 + writel(0x80200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348312 + writel(0x80201, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348313 + writel(0x80200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348314 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348316 + writel(0x11100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348317 + writel(0x11101, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348318 + writel(0x11100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348319 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348321 + writel(0xC00C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348322 + writel(0xC00C01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348323 + writel(0xC00C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348324 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348326 + writel(0xd80d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348327 + writel(0xd80d01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348328 + writel(0xd80d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348329 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
348334 + writel(0x88200, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348335 + writel(0x88201, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348336 + writel(0x88200, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348337 + writel(0x0, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348339 + writel(0x19100, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348340 + writel(0x19101, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348341 + writel(0x19100, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348342 + writel(0x0, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348344 + writel(0xC08C00, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348345 + writel(0xC08C01, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348346 + writel(0xC08C00, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348347 + writel(0x0, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348349 + writel(0xd88d00, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348350 + writel(0xd88d01, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348351 + writel(0xd88d00, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348352 + writel(0x0, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348357 + writel(0x80200, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348358 + writel(0x80201, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348359 + writel(0x80200, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348360 + writel(0x0, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348362 + writel(0x11100, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348363 + writel(0x11101, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348364 + writel(0x11100, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348365 + writel(0x0, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348367 + writel(0xC00C00, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348368 + writel(0xC00C01, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348369 + writel(0xC00C00, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348370 + writel(0x0, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348372 + writel(0xd80d00, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348373 + writel(0xd80d01, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348374 + writel(0xd80d00, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348375 + writel(0x0, misc_base + HISI_COMB_PHY2_TEST_CTRL);
348430 +#define IOCONFIG1_REG_BASE 0x10ff0000
348431 +#define IOCONFIG1_REG_MAP_SIZE 0x80
348445 + for (port_idx = 0; port_idx < ports_num; port_idx++) {
348446 + if (port_idx == 0) {
348447 + writel(0x1201, reg_addr + 0x48);
348449 + writel(0x1201, reg_addr + 0x4c);
348451 + writel(0x1201, reg_addr + 0x50);
348453 + writel(0x1201, reg_addr + 0x54);
348474 + for (port_idx = 0; port_idx < ports_num; port_idx++) {
348475 + writel(PX_TX_PREEMPH, (mmio + 0x100 + port_idx * 0x80 +
348477 + writel(PX_TX_AMPLITUDE, (mmio + 0x100 + port_idx * 0x80 +
348479 + writel(phy_config, (mmio + 0x100 + port_idx * 0x80 + HISI_SATA_PORT_PHYCTL3));
348527 + unsigned int ups_mode = 0;
348528 + unsigned int reg_val = 0;
348529 + unsigned int sata_port_num = 0;
348536 + return 0;
348544 + sata_port_map = 0x1;
348549 + sata_port_map = 0x3;
348553 + sata_port_map = 0x7;
348557 + sata_port_map = 0xf;
348560 + sata_port_num = 0;
348561 + sata_port_map = 0;
348572 @@ -0,0 +1,730 @@
348595 +#define HISI_SATA_PHY0_CTLL 0xA0
348596 +#define HISI_SATA_PHY0_CTLH 0xA4
348597 +#define HISI_SATA_PHY1_CTLL 0xAC
348598 +#define HISI_SATA_PHY1_CTLH 0xB0
348600 +#define HISI_SATA_PORT_FIFOTH 0x44
348601 +#define HISI_SATA_PORT_PHYCTL1 0x70
348602 +#define HISI_SATA_PORT_PHYCTL2 0x74
348603 +#define HISI_SATA_PORT_PHYCTL3 0x78
348605 +#define HISI_SYS_CTRL_REG_BASE 0x11020000
348606 +#define HISI_SYS_STAT_REG 0x0018
348607 +#define HISI_SYS_CTRL_REG_MAP_SIZE 0x1000
348608 +#define GET_UPS_MODE_VAL(reg_val) (((reg_val) >> 16) & 0x7)
348610 +#define SATA_PHY_CTRL0 0x140
348611 +#define SATA_PHY_CTRL1 0x144
348619 +#define HISI_MISC_REG_BASE 0x11024000
348620 +#define HISI_MISC_REG_MAP_SIZE 0x1000
348622 +#define HISI_COMB_PHY1_TEST_CTRL 0x1cc
348623 +#define HISI_COMB_PHY2_TEST_CTRL 0x1d0
348625 +#define HISI_CRG_REG_BASE 0x11010000
348627 +#define SATA_CLK_RST_CTRL_1_REG 0x3B40
348628 +#define SATA_CLK_RST_CTRL_2_REG 0x3B48
348630 +#define HISI_SATA_CKO_ALIVE_SRST_REQ BIT(0)
348632 +#define HISI_SATA_BUS_SRST_REQ BIT(0)
348635 +#define SATA_PHY0_CLK_RST_REG 0x3B60
348636 +#define SATA_PHY1_CLK_RST_REG 0x3B80
348637 +#define SATA_PHY2_CLK_RST_REG 0x3BA0
348638 +#define SATA_PHY3_CLK_RST_REG 0x3BC0
348640 +#define SATA_CTRL_RXn_RST BIT(0)
348645 +#define COMB_PHY1_PORT_A_REG 0x3B70
348646 +#define COMB_PHY1_PORT_B_REG 0x3B90
348647 +#define COMB_PHY2_PORT_A_REG 0x3BB0
348648 +#define COMB_PHY2_PORT_B_REG 0x3BD0
348650 +#define COMB_PHY_REST BIT(0)
348656 +#define SATA_CRG_MAP_SIZE 0x100
348659 + FIFOTH_VALUE = 0xdffeffff,
348660 + PHY_VALUE = 0x4900003d,
348661 + PHYCTL2_VALUE = 0x60555,
348663 + PORT_BIGENDINE = 0x82e5cb8,
348665 + PX_TX_AMPLITUDE = 0x36089,
348666 + PX_TX_PREEMPH = 0x486186,
348668 + PHY_SG_1_5G = 0xe000030,
348669 + PHY_SG_3G = 0xe200030,
348670 + PHY_SG_6G = 0xe400030,
348685 + reg_val = readl(crg_base + 0x20);
348687 + writel(reg_val, crg_base + 0x20);
348694 + reg_val = readl(crg_base + 0x20);
348696 + writel(reg_val, crg_base + 0x20);
348703 + reg_val = readl(crg_base + 0x40);
348705 + writel(reg_val, crg_base + 0x40);
348712 + reg_val = readl(crg_base + 0x40);
348714 + writel(reg_val, crg_base + 0x40);
348771 + case 0:
348772 + reg_val = readl(crg_base + 0x20);
348774 + writel(reg_val, crg_base + 0x20);
348776 + reg_val = readl(comb_phy_crg_base + 0x20);
348778 + writel(reg_val, comb_phy_crg_base + 0x20);
348781 + reg_val = readl(crg_base + 0x40);
348783 + writel(reg_val, crg_base + 0x40);
348822 + case 0:
348823 + reg_val = readl(crg_base + 0x20);
348825 + writel(reg_val, crg_base + 0x20);
348827 + reg_val = readl(comb_phy_crg_base + 0x20);
348829 + writel(reg_val, comb_phy_crg_base + 0x20);
348832 + reg_val = readl(crg_base + 0x40);
348834 + writel(reg_val, crg_base + 0x40);
348866 + reg_val = readl(crg_base + 0x8);
348868 + writel(reg_val, crg_base + 0x8);
348894 + reg_val = readl(crg_base + 0x8);
348896 + writel(reg_val, crg_base + 0x8);
348905 + reg_val = readl(crg_base + 0x20);
348907 + writel(reg_val, crg_base + 0x20);
348914 + reg_val = readl(crg_base + 0x20);
348916 + writel(reg_val, crg_base + 0x20);
349003 + reg_val = readl(crg_base + 0x20);
349005 + writel(reg_val, crg_base + 0x20);
349012 + reg_val = readl(crg_base + 0x40);
349014 + writel(reg_val, crg_base + 0x40);
349046 + reg_val = readl(crg_base + 0x8);
349048 + writel(reg_val, crg_base + 0x8);
349065 + reg_val = readl(crg_base + 0x20);
349068 + writel(reg_val, crg_base + 0x20);
349116 + for (port_idx = 0; port_idx < ports_num; port_idx++) {
349117 + writel(FIFOTH_VALUE, (mmio + 0x100 + port_idx * 0x80 + PORT_FIFOTH));
349124 + writel(0x88200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349125 + writel(0x88201, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349126 + writel(0x88200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349127 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349129 + writel(0x19100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349130 + writel(0x19101, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349131 + writel(0x19100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349132 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349134 + writel(0xC08C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349135 + writel(0xC08C01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349136 + writel(0xC08C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349137 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349139 + writel(0xd88d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349140 + writel(0xd88d01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349141 + writel(0xd88d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349142 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349147 + writel(0x80200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349148 + writel(0x80201, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349149 + writel(0x80200, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349150 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349152 + writel(0x11100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349153 + writel(0x11101, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349154 + writel(0x11100, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349155 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349157 + writel(0xC00C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349158 + writel(0xC00C01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349159 + writel(0xC00C00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349160 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349162 + writel(0xd80d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349163 + writel(0xd80d01, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349164 + writel(0xd80d00, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349165 + writel(0x0, misc_base + HISI_COMB_PHY1_TEST_CTRL);
349197 +#define IOCONFIG1_REG_BASE 0x10ff0000
349198 +#define IOCONFIG1_REG_MAP_SIZE 0x80
349212 + for (port_idx = 0; port_idx < ports_num; port_idx++) {
349213 + if (port_idx == 0) {
349214 + writel(0x1201, reg_addr + 0x48);
349216 + writel(0x1201, reg_addr + 0x4c);
349237 + for (port_idx = 0; port_idx < ports_num; port_idx++) {
349238 + writel(PX_TX_PREEMPH, (mmio + 0x100 + port_idx * 0x80 +
349240 + writel(PX_TX_AMPLITUDE, (mmio + 0x100 + port_idx * 0x80 +
349242 + writel(phy_config, (mmio + 0x100 + port_idx * 0x80 + HISI_SATA_PORT_PHYCTL3));
349272 + unsigned int ups_mode = 0;
349273 + unsigned int reg_val = 0;
349274 + unsigned int sata_port_num = 0;
349281 + return 0;
349289 + sata_port_map = 0x1;
349293 + sata_port_map = 0x3;
349296 + sata_port_num = 0;
349297 + sata_port_map = 0;
349308 @@ -0,0 +1,175 @@
349340 +MODULE_PARM_DESC(phy_mode, "sata phy mode (0:1.5G;1:3G(default);2:6G)");
349361 + unsigned int sata_port_num = 0;
349383 + return 0;
349398 + return 0;
349415 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
349439 + return 0;
349450 + return 0;
349460 + return 0;
349489 @@ -0,0 +1,39 @@
349510 + PHY_CTL0 = 0xA0,
349511 + PHY_CTL1 = 0xA4,
349512 + PHY_RST_BACK_MASK = 0xAC,
349513 + PHY_CTL2 = 0xB0,
349515 +#define PHY_DATA_INVERT (0x1 << 3)
349516 +#define PHY0_RST_MASK (0x1 << 4)
349517 +#define PHY_RST_MASK_ALL (0xF << 4)
349520 + PORT_FIFOTH = 0x44,
349521 + PORT_FIFOTH2 = 0x7C,
349522 + PORT_PHYCTL1 = 0x48,
349523 + PORT_PHYCTL = 0x74,
349525 +#define PHY_MODE_1_5G 0
349534 @@ -0,0 +1,85 @@
349557 + USB3.0 and Compatible with USB2.0. It suppots one
349625 @@ -0,0 +1,17 @@
349648 @@ -0,0 +1,310 @@
349677 +#define CRG_BASE_REG 0x140
349678 +#define USB2_UTMI_PCTRL (0x1 << 15)
349679 +#define USB2_PHY_TEST_SRST_REQ (0x1 << 14)
349680 +#define USB2_UTMI_CKSEL (0x1 << 13)
349681 +#define USB2_UTMI_CKEN (0x1 << 12)
349682 +#define USB2_REF_CKEN (0x1 << 9)
349683 +#define USB2_BUS_CKEN (0x1 << 8)
349684 +#define USB2_VCC_SRST_REQ (0x1 << 3)
349685 +#define USB2_PHY_CKEN (0x1 << 2)
349686 +#define USB2_PHY_PORT_TREQ (0x1 << 1)
349687 +#define USB2_PHY_REQ (0x1 << 0)
349689 +#define CTRL_BASE_REG 0x100e0000
349691 +#define REG_GUSB3PIPECTL0 0xc2c0
349692 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
349693 +#define PORT_DISABLE_SUSPEND (0x1 << 17)
349695 +#define REG_GCTL 0xc110
349696 +#define PORT_CAP_DIR (0x3 << 12)
349697 +#define PORT_SET_HOST (0x1 << 12)
349699 +#define GTXTHRCFG 0xc108
349700 +#define USB2_G_TXTHRCFG 0x23100000
349702 +#define GRXTHRCFG 0xc10c
349703 +#define USB2_G_RXTHRCFG 0x23100000
349705 +#define REG_GUCTL1 0xc11c
349706 +#define PARKMODE_DISABLE_FSLS (0x1 << 15)
349707 +#define PARKMODE_DISABLE_HS (0x1 << 16)
349708 +#define PARKMODE_DISABLE_SS (0x1 << 17)
349710 +#define USB2_INNO_PHY_BASE_REG 0x10110000
349711 +#define USB2_PHY_CLK_OUTPUT_REG 0x18
349712 +#define USB2_PHY_CLK_OUTPUT_VAL 0x0c
349713 +#define USB2_INNO_TRIM_OFFSET 0x0c
349715 +#define USB2_VBUS_IO_BASE_REG 0x10ff0000
349716 +#define USB2_VBUS_IO_OFFSET 0x40
349717 +#define USB2_VBUS_IO_VAL 0x431
349719 +#define USB_TRIM_BASE_REG 0x100a0000
349720 +#define USB_TRIM_OFFSET 0x38
349721 +#define USB_INNO_TRIM_MASK 0x7c
349723 +#define USB_TRIM_VAL_MASK 0x1f
349724 +#define USB_TRIM_VAL_MIN 0xf
349725 +#define USB_TRIM_VAL_MAX 0x1c
349727 +#define HS_HIGH_HEIGHT_TUNING_OFFSET 0x8
349728 +#define HS_HIGH_HEIGHT_TUNING_MASK (0x7 << 4)
349729 +#define HS_HIGH_HEIGHT_TUNING_VAL 0x5 << 4
349731 +#define PRE_EMPHASIS_TUNING_OFFSET 0x0
349732 +#define PRE_EMPHASIS_TUNING_MASK (0x7 << 0)
349733 +#define PRE_EMPHASIS_TUNING_VAL 0x7 << 0
349735 +#define PRE_EMPHASIS_STRENGTH_OFFSET 0x14
349736 +#define PRE_EMPHASIS_STRENGTH_MASK (0x7 << 2)
349737 +#define PRE_EMPHASIS_STRENGTH_VAL 0x3 << 2
349739 +#define HS_SLEW_RATE_TUNING_OFFSET 0x74
349740 +#define HS_SLEW_RATE_TUNING_MASK (0x7 << 1)
349741 +#define HS_SLEW_RATE_TUNING_VAL 0x7 << 1
349743 +#define DISCONNECT_TRIGGER_OFFSET 0x10
349744 +#define DISCONNECT_TRIGGER_MASK (0xf << 4)
349745 +#define DISCONNECT_TRIGGER_VAL 0xd << 4
349964 @@ -0,0 +1,310 @@
349993 +#define CRG_BASE_REG 0x140
349994 +#define USB2_UTMI_PCTRL (0x1 << 15)
349995 +#define USB2_PHY_TEST_SRST_REQ (0x1 << 14)
349996 +#define USB2_UTMI_CKSEL (0x1 << 13)
349997 +#define USB2_UTMI_CKEN (0x1 << 12)
349998 +#define USB2_REF_CKEN (0x1 << 9)
349999 +#define USB2_BUS_CKEN (0x1 << 8)
350000 +#define USB2_VCC_SRST_REQ (0x1 << 3)
350001 +#define USB2_PHY_CKEN (0x1 << 2)
350002 +#define USB2_PHY_PORT_TREQ (0x1 << 1)
350003 +#define USB2_PHY_REQ (0x1 << 0)
350005 +#define CTRL_BASE_REG 0x100e0000
350007 +#define REG_GUSB3PIPECTL0 0xc2c0
350008 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
350009 +#define PORT_DISABLE_SUSPEND (0x1 << 17)
350011 +#define REG_GCTL 0xc110
350012 +#define PORT_CAP_DIR (0x3 << 12)
350013 +#define PORT_SET_HOST (0x1 << 12)
350015 +#define GTXTHRCFG 0xc108
350016 +#define USB2_G_TXTHRCFG 0x23100000
350018 +#define GRXTHRCFG 0xc10c
350019 +#define USB2_G_RXTHRCFG 0x23100000
350021 +#define REG_GUCTL1 0xc11c
350022 +#define PARKMODE_DISABLE_FSLS (0x1 << 15)
350023 +#define PARKMODE_DISABLE_HS (0x1 << 16)
350024 +#define PARKMODE_DISABLE_SS (0x1 << 17)
350026 +#define USB2_INNO_PHY_BASE_REG 0x10110000
350027 +#define USB2_PHY_CLK_OUTPUT_REG 0x18
350028 +#define USB2_PHY_CLK_OUTPUT_VAL 0x0c
350029 +#define USB2_INNO_TRIM_OFFSET 0x0c
350031 +#define USB2_VBUS_IO_BASE_REG 0x10ff0000
350032 +#define USB2_VBUS_IO_OFFSET 0x40
350033 +#define USB2_VBUS_IO_VAL 0x431
350035 +#define USB_TRIM_BASE_REG 0x100a0000
350036 +#define USB_TRIM_OFFSET 0x38
350037 +#define USB_INNO_TRIM_MASK 0x7c
350039 +#define USB_TRIM_VAL_MASK 0x1f
350040 +#define USB_TRIM_VAL_MIN 0xf
350041 +#define USB_TRIM_VAL_MAX 0x1c
350043 +#define HS_HIGH_HEIGHT_TUNING_OFFSET 0x8
350044 +#define HS_HIGH_HEIGHT_TUNING_MASK (0x7 << 4)
350045 +#define HS_HIGH_HEIGHT_TUNING_VAL 0x5 << 4
350047 +#define PRE_EMPHASIS_TUNING_OFFSET 0x0
350048 +#define PRE_EMPHASIS_TUNING_MASK (0x7 << 0)
350049 +#define PRE_EMPHASIS_TUNING_VAL 0x7 << 0
350051 +#define PRE_EMPHASIS_STRENGTH_OFFSET 0x14
350052 +#define PRE_EMPHASIS_STRENGTH_MASK (0x7 << 2)
350053 +#define PRE_EMPHASIS_STRENGTH_VAL 0x3 << 2
350055 +#define HS_SLEW_RATE_TUNING_OFFSET 0x74
350056 +#define HS_SLEW_RATE_TUNING_MASK (0x7 << 1)
350057 +#define HS_SLEW_RATE_TUNING_VAL 0x7 << 1
350059 +#define DISCONNECT_TRIGGER_OFFSET 0x10
350060 +#define DISCONNECT_TRIGGER_MASK (0xf << 4)
350061 +#define DISCONNECT_TRIGGER_VAL 0xd << 4
350280 @@ -0,0 +1,431 @@
350309 +#define USB3_CTRL_REGBASE 0x04110000
350310 +#define USB2_CTRL_REGBASE 0x04120000
350311 +#define PORT_CAP_DIR (0x3 << 12)
350312 +#define DEFAULT_HOST_MOD (0x1 << 12)
350314 +#define USB2_PHY 0x184
350315 +#define USB2_PHY0_CKEN (0x1 << 5)
350316 +#define USB2_PHY1_CKEN (0x1 << 4)
350317 +#define USB2_PHY0_PORT_TREQ (0x1 << 3)
350318 +#define USB2_PHY1_PORT_TREQ (0x1 << 2)
350319 +#define USB2_PHY0_REQ (0x1 << 1)
350320 +#define USB2_PHY1_REQ (0x1 << 0)
350322 +#define USB3_COMBPHY 0x188
350323 +#define COMBPHY0_REF_CKEN (0x1 << 8)
350324 +#define COMBPHY_SRST_REQ (0x1 << 0)
350326 +#define USB3_CTRL 0x190
350327 +#define USB3_PCLK_OCC_SEL (0x1 << 30)
350328 +#define USB3_UTMI_CKSEL (0x1 << 29)
350329 +#define USB3_VCC_SRST_REQ (0x1 << 16)
350330 +#define USB2_UTMI_CKSEL (0x1 << 13)
350331 +#define USB2_VCC_SRST_REQ (0x1 << 0)
350333 +#define GTXTHRCFG 0xc108
350334 +#define GRXTHRCFG 0xc10c
350335 +#define REG_GCTL 0xc110
350337 +#define REG_GUCTL1 0xc11c
350338 +#define PARKMODE_DISABLE_FSLS (0x1 << 15)
350339 +#define PARKMODE_DISABLE_HS (0x1 << 16)
350340 +#define PARKMODE_DISABLE_SS (0x1 << 17)
350342 +#define PERI_USB3_GTXTHRCFG 0x2310000
350344 +#define REG_GUSB3PIPECTL0 0xc2c0
350345 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
350346 +#define SUSPEND_USB3_SS_PHY (0x1 << 17)
350347 +#define USB3_TX_MARGIN (0x7 << 3)
350348 +#define USB3_TX_MARGIN_VAL (0x2 << 3)
350350 +#define PORT0_CTRL 0x38
350351 +#define U3_ENABLE (0x1 << 3)
350353 +#define USB2_PHY0 0x24
350354 +#define USB2_PHY0_TXVREFTUNE (0xf << 4)
350355 +#define USB2_PHY0_VREF_VAL (0x5 << 4)
350356 +#define USB2_PHY0_TXPRE (0x3 << 12)
350357 +#define USB2_PHY0_PRE_VAL (0x1 << 12)
350359 +#define USB2_PHY1 0x30
350360 +#define USB2_PHY1_TXVREFTUNE (0xf << 4)
350361 +#define USB2_PHY1_VREF_VAL (0x5 << 4)
350362 +#define USB2_PHY1_TXPRE (0x3 << 12)
350363 +#define USB2_PHY1_PRE_VAL (0x1 << 12)
350365 +#define USB3_PCIE_COMBO_PHY 0x14
350366 +#define TX_SWING_COMP_CFG 0x913
350367 +#define TX_SWING_COMP_RCFG 0x953
350368 +#define TX_SWING_COMP_CFG_VAL 0x913
350370 +#define SYSCTRL_REGBASE 0x04520000
350371 +#define SYSSTAT 0x8c
350372 +#define PCIE_USB3_MASK (0x3 << 12)
350374 +#define USB3 0x1
350375 +#define PCIE_X1 0x0
350377 +#define HPM_INFO_OFFSET 0x158
350378 +#define HPM_INFO_MASK 0x1ff
350380 +#define KEEP_DEFAULT_FLAG 0x18e
350382 +#define USB3_DEF_CRG 0x1f010000
350383 +#define USB3_DEF_CFG_MASK 0xffff0000
350384 +#define USB2_DEF_CRG 0x00001301
350385 +#define USB2_DEF_CFG_MASK 0x0000ffff
350387 +#define COMBPHY_IN_USE 0x1
350388 +#define COMBPHY_NO_IN_USE 0x0
350469 + /* port0 phy high-spped DC adjust: 0% --> 4% */
350470 + /* port0 pre elec adjust: 0 --> 1x */
350479 + /* port1 phy high-spped DC adjust: 0% --> 4% */
350480 + /* port1 pre elec adjust: 0 --> 1x */
350636 + * adjust 0x1000 --> 0x1001.
350647 + /* usb3 Tx margin adjust: 0 --> 900mv */
350717 @@ -0,0 +1,446 @@
350745 +#define PERI_CRG3632 0x0
350746 +#define DEF_VAL_3632 0x10331
350747 +#define USB2_0_SRST_REQ (0x1 << 0)
350748 +#define USB2_0_BUS_CKEN (0x1 << 4)
350749 +#define USB2_0_REF_CKEN (0x1 << 5)
350750 +#define USB2_0_UTMI_CKEN (0x1 << 8)
350751 +#define USB2_2_UTMI_CKEN (0x1 << 9)
350752 +#define USB2_0_FREECLK_CKSEL (0x1 << 16)
350754 +#define PERI_CRG3636 0x10
350755 +#define DEF_VAL_3636 0x153
350756 +#define USB2_PHY0_REQ (0x1 << 0)
350757 +#define USB2_PHY0_TREQ (0x1 << 1)
350758 +#define USB2_PHY0_APB_SRST_REQ (0x1 << 2)
350759 +#define USB2_PHY0_XTAL_CKEN (0x1 << 4)
350761 +#define PERI_CRG3640 0x20
350762 +#define DEF_VAL_3640 0x10131
350763 +#define USB2_1_SRST_REQ (0x1 << 0)
350764 +#define USB2_1_BUS_CKEN (0x1 << 4)
350765 +#define USB2_1_REF_CKEN (0x1 << 5)
350766 +#define USB2_1_UTMI_CKEN (0x1 << 8)
350768 +#define PERI_CRG3644 0x30
350769 +#define DEF_VAL_3644 0x153
350770 +#define USB2_PHY1_REQ (0x1 << 0)
350771 +#define USB2_PHY1_TREQ (0x1 << 1)
350772 +#define USB2_PHY1_APB_SRST_REQ (0x1 << 2)
350773 +#define USB2_PHY1_XTAL_CKEN (0x1 << 4)
350775 +#define PERI_CRG3672 0xa0
350776 +#define DEF_VAL_3672 0x153
350777 +#define USB2_PHY2_REQ (0x1 << 0)
350778 +#define USB2_PHY2_TREQ (0x1 << 1)
350779 +#define USB2_PHY2_APB_SRST_REQ (0x1 << 2)
350780 +#define USB2_PHY2_XTAL_CKEN (0x1 << 4)
350782 +#define USB_CTRL_BASE 0x10300000
350783 +#define USB2_PHY2_BASE 0x10310000
350784 +#define USB2_PHY1_BASE 0x10350000
350785 +#define USB2_PHY0_BASE 0x10330000
350787 +#define GUSB2PHYCFG 0xc204
350788 +#define U2_FREECLK_EXISTS (0x1 << 30)
350790 +#define PHY_PLL_ENABLE (0x3 << 0)
350791 +#define PHY_PLL_OFFSET 0x14
350793 +#define RG_HSTX_MBIAS 0x0
350794 +#define RG_HSTX_MBIAS_MASK (0xf << 0)
350795 +#define RG_HSTX_MBIAS_VAL (0xb << 0)
350797 +#define TX_TEST_BIT 0x8
350798 +#define TX_TEST_BIT_VAL (0x1 << 20)
350800 +#define DISC_REF_VOL_SEL 0x8
350801 +#define DISC_REF_VOL_SEL_MASK (0x7 << 16)
350802 +#define DISC_REF_VOL_SEL_VAL (0x5 << 16)
350804 +#define SLEW_RATE_OPTION 0xc
350805 +#define SLEW_RATE_OPTION_MASK (0x3 << 20)
350806 +#define SLEW_RATE_OPTION_VAL (0x1 << 20)
350808 +#define TX_REF_VOL_SEL 0x10
350809 +#define TX_REF_VOL_SEL_MASK (0x7 << 4)
350810 +#define TX_REF_VOL_SEL_VAL (0x6 << 4)
350812 +#define RG_FL_EDGE_MODE 0x10
350813 +#define RG_FL_EDGE_MODE_VAL (0x1 << 13)
350815 +#define U2_TRIM_VAL_MIN 0x09
350816 +#define U2_TRIM_VAL_MAX 0x1d
350817 +#define RT_TRIM_VAL_MASK 0x1f
350820 +#define usb2_0_trim_val(p) (((p) >> 0) & RT_TRIM_VAL_MASK)
350822 +#define U2_ANA_CFG2 0x8
351169 @@ -0,0 +1,526 @@
351197 +#define PERI_CRG3632 0x0
351198 +#define USB2_0_UTMI_CKEN (0x1 << 8)
351200 +#define PERI_CRG3636 0x10
351201 +#define USB2_PHY0_REQ (0x1 << 0)
351202 +#define USB2_PHY0_TREQ (0x1 << 1)
351203 +#define USB2_PHY0_APB_SRST_REQ (0x1 << 2)
351204 +#define USB2_PHY0_XTAL_CKEN (0x1 << 4)
351206 +#define PERI_CRG3640 0x20
351207 +#define USB2_1_SRST_REQ (0x1 << 0)
351208 +#define USB2_1_BUS_CKEN (0x1 << 4)
351209 +#define USB2_1_REF_CKEN (0x1 << 5)
351210 +#define USB2_1_UTMI_CKEN (0x1 << 8)
351212 +#define PERI_CRG3644 0x30
351213 +#define USB2_PHY1_REQ (0x1 << 0)
351214 +#define USB2_PHY1_TREQ (0x1 << 1)
351215 +#define USB2_PHY1_APB_SRST_REQ (0x1 << 2)
351216 +#define USB2_PHY1_XTAL_CKEN (0x1 << 4)
351218 +#define PERI_CRG3664 0x80
351219 +#define USB3_SRST_REQ (0x1 << 0)
351220 +#define USB3_BUS_CKEN (0x1 << 4)
351221 +#define USB3_REF_CKEN (0x1 << 5)
351222 +#define USB3_SUSPEND_CKEN (0x1 << 6)
351223 +#define USB3_UTMI_CKEN (0x1 << 8)
351224 +#define USB3_PIPE_CKEN (0x1 << 12)
351226 +#define PERI_CRG3672 0xa0
351227 +#define USB2_PHY2_REQ (0x1 << 0)
351228 +#define USB2_PHY2_TREQ (0x1 << 1)
351229 +#define USB2_PHY2_APB_SRST_REQ (0x1 << 2)
351230 +#define USB2_PHY2_XTAL_CKEN (0x1 << 4)
351232 +#define PERI_CRG3676 0xb0
351233 +#define COMBPHY0_SRST_REQ (0x1 << 0)
351234 +#define COMBPHY0_TEST_SRST_REQ (0x1 << 1)
351235 +#define COMBPHY0_REF_CKEN (0x1 << 4)
351237 +#define USB_CTRL6 0xc
351238 +#define U3_PORT_DISABLE (0x1 << 12)
351240 +#define USB2_PHY2_BASE 0x10310000
351241 +#define USB2_PHY1_BASE 0x10350000
351242 +#define USB2_PHY0_BASE 0x10330000
351244 +#define U2_ANA_CFG0 0x0
351245 +#define HSTX_MBIAS_MASK (0xf << 0)
351247 +#define U2_2_HSTX_MBIAS (0x3 << 0)
351248 +#define U2_1_HSTX_MBIAS (0xb << 0)
351249 +#define U2_0_HSTX_MBIAS (0xb << 0)
351251 +#define U2_ANA_CFG2 0x8
351252 +#define VDISCREF_SEL_MASK (0x7 << 16)
351254 +#define U2_2_VDISCREF_SEL (0x2 << 16)
351255 +#define U2_1_VDISCREF_SEL (0x5 << 16)
351256 +#define U2_0_VDISCREF_SEL (0x5 << 16)
351257 +#define U2_TEST_TX (0x1 << 20)
351259 +#define U2_TRIM_VAL_MIN 0x09
351260 +#define U2_TRIM_VAL_MAX 0x1d
351261 +#define RT_TRIM_VAL_MASK 0x1f
351264 +#define usb2_0_trim_val(p) (((p) >> 0) & RT_TRIM_VAL_MASK)
351269 +#define U2_ANA_CFG3 0xc
351270 +#define SLEW_RATE_OPT_MASK (0x3 << 20)
351272 +#define U2_2_SLEW_RATE_OPT (0x1 << 20)
351273 +#define U2_1_SLEW_RATE_OPT (0x1 << 20)
351274 +#define U2_0_SLEW_RATE_OPT (0x1 << 20)
351276 +#define U2_ANA_CFG4 0x10
351277 +#define VTXREF_SEL_MASK (0x7 << 4)
351279 +#define U2_VTXREF_SEL (0x5 << 4)
351280 +#define U2_FLS_EDGE_MODE (0x1 << 13)
351281 +#define U2_VTXREF_SEL_U3P (0x6 << 4)
351283 +#define COMBPHY_CTRL0 0x40
351284 +#define PI_CURRENT_TRIM_ENABLE 0x11100
351285 +#define PI_CURRENT_TRIM_VAL 0x11101
351286 +#define TX_SWING_COMP_ENABLE 0xc1200
351287 +#define TX_SWING_COMP_VAL 0xc1201
351289 +#define PHY_PLL_ENABLE (0x3 << 0)
351290 +#define PHY_PLL_OFFSET 0x14
351701 @@ -0,0 +1,429 @@
351730 +#define USB3_CTRL_REGBASE 0x04110000
351731 +#define USB2_CTRL_REGBASE 0x04120000
351732 +#define PORT_CAP_DIR (0x3 << 12)
351733 +#define DEFAULT_HOST_MOD (0x1 << 12)
351735 +#define USB2_PHY 0x184
351736 +#define USB2_PHY0_CKEN (0x1 << 5)
351737 +#define USB2_PHY1_CKEN (0x1 << 4)
351738 +#define USB2_PHY0_PORT_TREQ (0x1 << 3)
351739 +#define USB2_PHY1_PORT_TREQ (0x1 << 2)
351740 +#define USB2_PHY0_REQ (0x1 << 1)
351741 +#define USB2_PHY1_REQ (0x1 << 0)
351743 +#define USB3_COMBPHY 0x188
351744 +#define COMBPHY0_REF_CKEN (0x1 << 8)
351745 +#define COMBPHY_SRST_REQ (0x1 << 0)
351747 +#define USB3_CTRL 0x190
351748 +#define USB3_PCLK_OCC_SEL (0x1 << 30)
351749 +#define USB3_UTMI_CKSEL (0x1 << 29)
351750 +#define USB3_VCC_SRST_REQ (0x1 << 16)
351751 +#define USB2_UTMI_CKSEL (0x1 << 13)
351752 +#define USB2_VCC_SRST_REQ (0x1 << 0)
351754 +#define GTXTHRCFG 0xc108
351755 +#define GRXTHRCFG 0xc10c
351756 +#define REG_GCTL 0xc110
351758 +#define REG_GUCTL1 0xc11c
351759 +#define PARKMODE_DISABLE_FSLS (0x1 << 15)
351760 +#define PARKMODE_DISABLE_HS (0x1 << 16)
351761 +#define PARKMODE_DISABLE_SS (0x1 << 17)
351763 +#define PERI_USB3_GTXTHRCFG 0x2310000
351765 +#define REG_GUSB3PIPECTL0 0xc2c0
351766 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
351767 +#define SUSPEND_USB3_SS_PHY (0x1 << 17)
351768 +#define USB3_TX_MARGIN (0x7 << 3)
351769 +#define USB3_TX_MARGIN_VAL (0x2 << 3)
351771 +#define PORT0_CTRL 0x38
351772 +#define U3_ENABLE (0x1 << 3)
351774 +#define USB2_PHY0 0x24
351775 +#define USB2_PHY0_TXVREFTUNE (0xf << 4)
351776 +#define USB2_PHY0_VREF_VAL (0x5 << 4)
351777 +#define USB2_PHY0_TXPRE (0x3 << 12)
351778 +#define USB2_PHY0_PRE_VAL (0x1 << 12)
351780 +#define USB2_PHY1 0x30
351781 +#define USB2_PHY1_TXVREFTUNE (0xf << 4)
351782 +#define USB2_PHY1_VREF_VAL (0x5 << 4)
351783 +#define USB2_PHY1_TXPRE (0x3 << 12)
351784 +#define USB2_PHY1_PRE_VAL (0x1 << 12)
351786 +#define USB3_PCIE_COMBO_PHY 0x14
351787 +#define TX_SWING_COMP_CFG 0x913
351788 +#define TX_SWING_COMP_RCFG 0x953
351789 +#define TX_SWING_COMP_CFG_VAL 0x913
351791 +#define SYSCTRL_REGBASE 0x04520000
351792 +#define SYSSTAT 0x8c
351793 +#define PCIE_USB3_MASK (0x3 << 12)
351795 +#define USB3 0x1
351796 +#define PCIE_X1 0x0
351798 +#define HPM_INFO_OFFSET 0x158
351799 +#define HPM_INFO_MASK 0x1ff
351801 +#define KEEP_DEFAULT_FLAG 0x156
351803 +#define USB3_DEF_CRG 0x1f010000
351804 +#define USB3_DEF_CFG_MASK 0xffff0000
351805 +#define USB2_DEF_CRG 0x00001301
351806 +#define USB2_DEF_CFG_MASK 0x0000ffff
351808 +#define COMBPHY_IN_USE 0x1
351809 +#define COMBPHY_NO_IN_USE 0x0
351890 + /* port0 phy high-spped DC adjust: 0% --> 4% */
351891 + /* port0 pre elec adjust: 0 --> 1x */
351900 + /* port1 phy high-spped DC adjust: 0% --> 4% */
351901 + /* port1 pre elec adjust: 0 --> 1x */
352057 + * adjust 0x1000 --> 0x1001.
352067 + /* usb3 Tx margin adjust: 0 --> 900mv */
352136 @@ -0,0 +1,310 @@
352165 +#define CRG_BASE_REG 0x140
352166 +#define USB2_UTMI_PCTRL (0x1 << 15)
352167 +#define USB2_PHY_TEST_SRST_REQ (0x1 << 14)
352168 +#define USB2_UTMI_CKSEL (0x1 << 13)
352169 +#define USB2_UTMI_CKEN (0x1 << 12)
352170 +#define USB2_REF_CKEN (0x1 << 9)
352171 +#define USB2_BUS_CKEN (0x1 << 8)
352172 +#define USB2_VCC_SRST_REQ (0x1 << 3)
352173 +#define USB2_PHY_CKEN (0x1 << 2)
352174 +#define USB2_PHY_PORT_TREQ (0x1 << 1)
352175 +#define USB2_PHY_REQ (0x1 << 0)
352177 +#define CTRL_BASE_REG 0x100e0000
352179 +#define REG_GUSB3PIPECTL0 0xc2c0
352180 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
352181 +#define PORT_DISABLE_SUSPEND (0x1 << 17)
352183 +#define REG_GCTL 0xc110
352184 +#define PORT_CAP_DIR (0x3 << 12)
352185 +#define PORT_SET_HOST (0x1 << 12)
352187 +#define GTXTHRCFG 0xc108
352188 +#define USB2_G_TXTHRCFG 0x23100000
352190 +#define GRXTHRCFG 0xc10c
352191 +#define USB2_G_RXTHRCFG 0x23100000
352193 +#define REG_GUCTL1 0xc11c
352194 +#define PARKMODE_DISABLE_FSLS (0x1 << 15)
352195 +#define PARKMODE_DISABLE_HS (0x1 << 16)
352196 +#define PARKMODE_DISABLE_SS (0x1 << 17)
352198 +#define USB2_INNO_PHY_BASE_REG 0x10110000
352199 +#define USB2_PHY_CLK_OUTPUT_REG 0x18
352200 +#define USB2_PHY_CLK_OUTPUT_VAL 0x0c
352201 +#define USB2_INNO_TRIM_OFFSET 0x0c
352203 +#define USB2_VBUS_IO_BASE_REG 0x10ff0000
352204 +#define USB2_VBUS_IO_OFFSET 0x40
352205 +#define USB2_VBUS_IO_VAL 0x431
352207 +#define USB_TRIM_BASE_REG 0x100a0000
352208 +#define USB_TRIM_OFFSET 0x38
352209 +#define USB_INNO_TRIM_MASK 0x7c
352211 +#define USB_TRIM_VAL_MASK 0x1f
352212 +#define USB_TRIM_VAL_MIN 0xf
352213 +#define USB_TRIM_VAL_MAX 0x1c
352215 +#define HS_HIGH_HEIGHT_TUNING_OFFSET 0x8
352216 +#define HS_HIGH_HEIGHT_TUNING_MASK (0x7 << 4)
352217 +#define HS_HIGH_HEIGHT_TUNING_VAL 0x5 << 4
352219 +#define PRE_EMPHASIS_TUNING_OFFSET 0x0
352220 +#define PRE_EMPHASIS_TUNING_MASK (0x7 << 0)
352221 +#define PRE_EMPHASIS_TUNING_VAL 0x7 << 0
352223 +#define PRE_EMPHASIS_STRENGTH_OFFSET 0x14
352224 +#define PRE_EMPHASIS_STRENGTH_MASK (0x7 << 2)
352225 +#define PRE_EMPHASIS_STRENGTH_VAL 0x3 << 2
352227 +#define HS_SLEW_RATE_TUNING_OFFSET 0x74
352228 +#define HS_SLEW_RATE_TUNING_MASK (0x7 << 1)
352229 +#define HS_SLEW_RATE_TUNING_VAL 0x7 << 1
352231 +#define DISCONNECT_TRIGGER_OFFSET 0x10
352232 +#define DISCONNECT_TRIGGER_MASK (0xf << 4)
352233 +#define DISCONNECT_TRIGGER_VAL 0xd << 4
352452 @@ -0,0 +1,372 @@
352481 +#define USB2_PHY 0x184
352482 +#define USB2_PHY_CKEN (0x1 << 5)
352483 +#define USB2_PHY_PORT_TREQ (0x1 << 3)
352484 +#define USB2_PHY_REQ (0x1 << 1)
352486 +#define USB3_COMBPHY 0x188
352487 +#define COMBPHY_REF_CKEN1 (0x1 << 24)
352488 +#define COMBPHY_SRST_REQ1 (0x1 << 16)
352489 +#define COMBPHY_REF_CKEN (0x1 << 8)
352490 +#define COMBPHY_SRST_REQ (0x1 << 0)
352492 +#define USB3_CTRL 0x190
352493 +#define USB3_1_PCLK_OCC_SEL (0x1 << 14)
352494 +#define USB3_VCC_SRST_REQ (0x1 << 16)
352495 +#define USB3_UTMI_CKSEL (0x1 << 29)
352496 +#define USB3_0_PCLK_OCC_SEL (0x1 << 30)
352498 +#define REG_GUCTL1 0xc11c
352499 +#define PARKMODE_DISABLE_FSLS (0x1 << 15)
352500 +#define PARKMODE_DISABLE_HS (0x1 << 16)
352501 +#define PARKMODE_DISABLE_SS (0x1 << 17)
352503 +#define GTXTHRCFG 0xc108
352504 +#define GRXTHRCFG 0xc10c
352505 +#define REG_GCTL 0xc110
352507 +#define PORT_CAP_DIR (0x3 << 12)
352508 +#define DEFAULT_HOST_MOD (0x1 << 12)
352510 +#define USB_TXPKT_CNT_SEL (0x1 << 29)
352511 +#define USB_TXPKT_CNT (0x11 << 24)
352512 +#define USB_MAXTX_BURST_SIZE (0x1 << 20)
352513 +#define CLEAN_USB3_GTXTHRCFG 0x0
352515 +#define REG_GUSB3PIPECTL0 0xc2c0
352516 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
352517 +#define SUSPEND_USB3_SS_PHY (0x1 << 17)
352518 +#define USB3_TX_MARGIN_VAL 0x10c0012
352520 +#define USB3_COMB_PHY 0x14
352521 +#define P0_TX_SWING_COMP_CFG 0x913
352522 +#define P0_TX_SWING_COMP_RCFG 0x953
352523 +#define P0_TX_SWING_COMP_VAL 0x913
352524 +#define P1_TX_SWING_COMP_CFG 0x933
352525 +#define P1_TX_SWING_COMP_RCFG 0x973
352526 +#define P1_TX_SWING_COMP_VAL 0x933
352528 +#define OTP_CPU_REGBASE 0x10250000
352529 +#define HPM_CORE_OFFSET 0x28
352530 +#define KEEP_DEFAULT_FLAG 0x174
352532 +#define USB2_PHY0_CTRL 0x24
352533 +#define USB2_PHY1_CTRL 0x30
352534 +#define USB2_PHY_VREF_MASK (0xf << 4)
352535 +#define USB2_PHY_VREF (0x5 << 4)
352536 +#define USB2_PHY_PRE (0x3 << 12)
352538 +#define USB_PORT0 0x38
352539 +#define P0_U3_PORT_DISABLE (0x1 << 3)
352540 +#define USB_PORT1 0x3c
352541 +#define P1_U3_PORT_DISABLE (0x1 << 3)
352543 +#define PCIE_X2_MODE (0x0 << 12)
352544 +#define PCIE_X1_MODE (0x1 << 12)
352545 +#define USB3_MODE (0x2 << 12)
352546 +#define COMBPHY_MODE_MASK (0x3 << 12)
352547 +#define SYSSTAT 0x8c
352549 +#define USB3_PORT1_CLK (0x1 << 14)
352551 +#define COMBPHY_IN_USE 0x1
352552 +#define COMBPHY_NO_IN_USE 0x0
352756 + * adjust 0x1000 --> 0x1001.
352781 + unsigned int u2 = 0;
352782 + unsigned int u3 = 0;
352803 + unsigned int usb3_offset = 0;
352830 @@ -0,0 +1,310 @@
352859 +#define CRG_BASE_REG 0x140
352860 +#define USB2_UTMI_PCTRL (0x1 << 15)
352861 +#define USB2_PHY_TEST_SRST_REQ (0x1 << 14)
352862 +#define USB2_UTMI_CKSEL (0x1 << 13)
352863 +#define USB2_UTMI_CKEN (0x1 << 12)
352864 +#define USB2_REF_CKEN (0x1 << 9)
352865 +#define USB2_BUS_CKEN (0x1 << 8)
352866 +#define USB2_VCC_SRST_REQ (0x1 << 3)
352867 +#define USB2_PHY_CKEN (0x1 << 2)
352868 +#define USB2_PHY_PORT_TREQ (0x1 << 1)
352869 +#define USB2_PHY_REQ (0x1 << 0)
352871 +#define CTRL_BASE_REG 0x100e0000
352873 +#define REG_GUSB3PIPECTL0 0xc2c0
352874 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
352875 +#define PORT_DISABLE_SUSPEND (0x1 << 17)
352877 +#define REG_GCTL 0xc110
352878 +#define PORT_CAP_DIR (0x3 << 12)
352879 +#define PORT_SET_HOST (0x1 << 12)
352881 +#define GTXTHRCFG 0xc108
352882 +#define USB2_G_TXTHRCFG 0x23100000
352884 +#define GRXTHRCFG 0xc10c
352885 +#define USB2_G_RXTHRCFG 0x23100000
352887 +#define REG_GUCTL1 0xc11c
352888 +#define PARKMODE_DISABLE_FSLS (0x1 << 15)
352889 +#define PARKMODE_DISABLE_HS (0x1 << 16)
352890 +#define PARKMODE_DISABLE_SS (0x1 << 17)
352892 +#define USB2_INNO_PHY_BASE_REG 0x10110000
352893 +#define USB2_PHY_CLK_OUTPUT_REG 0x18
352894 +#define USB2_PHY_CLK_OUTPUT_VAL 0x0c
352895 +#define USB2_INNO_TRIM_OFFSET 0x0c
352897 +#define USB2_VBUS_IO_BASE_REG 0x10ff0000
352898 +#define USB2_VBUS_IO_OFFSET 0x40
352899 +#define USB2_VBUS_IO_VAL 0x431
352901 +#define USB_TRIM_BASE_REG 0x100a0000
352902 +#define USB_TRIM_OFFSET 0x38
352903 +#define USB_INNO_TRIM_MASK 0x7c
352905 +#define USB_TRIM_VAL_MASK 0x1f
352906 +#define USB_TRIM_VAL_MIN 0xf
352907 +#define USB_TRIM_VAL_MAX 0x1c
352909 +#define HS_HIGH_HEIGHT_TUNING_OFFSET 0x8
352910 +#define HS_HIGH_HEIGHT_TUNING_MASK (0x7 << 4)
352911 +#define HS_HIGH_HEIGHT_TUNING_VAL 0x5 << 4
352913 +#define PRE_EMPHASIS_TUNING_OFFSET 0x0
352914 +#define PRE_EMPHASIS_TUNING_MASK (0x7 << 0)
352915 +#define PRE_EMPHASIS_TUNING_VAL 0x7 << 0
352917 +#define PRE_EMPHASIS_STRENGTH_OFFSET 0x14
352918 +#define PRE_EMPHASIS_STRENGTH_MASK (0x7 << 2)
352919 +#define PRE_EMPHASIS_STRENGTH_VAL 0x3 << 2
352921 +#define HS_SLEW_RATE_TUNING_OFFSET 0x74
352922 +#define HS_SLEW_RATE_TUNING_MASK (0x7 << 1)
352923 +#define HS_SLEW_RATE_TUNING_VAL 0x7 << 1
352925 +#define DISCONNECT_TRIGGER_OFFSET 0x10
352926 +#define DISCONNECT_TRIGGER_MASK (0xf << 4)
352927 +#define DISCONNECT_TRIGGER_VAL 0xd << 4
353146 @@ -0,0 +1,149 @@
353227 + return 0;
353245 + return 0;
353266 + return 0;
353278 + return 0;
353301 @@ -0,0 +1,72 @@
353340 + PCIE_X2 = 0,
353362 +#define __1K__ 0x400
353363 +#define __2K__ 0x800
353364 +#define __4K__ 0x1000
353365 +#define __8K__ 0x2000
353366 +#define __64K__ 0x10000
353368 +#define CRG_NODE_IDX 0
353379 @@ -0,0 +1,803 @@
353413 +#define HIXVP_PHY_TRIM_OFFSET 0x0008
353414 +#define HIXVP_PHY_TRIM_MASK 0x1f00
353417 +#define HIXVP_PHY_SVB_OFFSET 0x0000
353418 +#define HIXVP_PHY_SVB_MASK 0x0f000000
353525 + priv->ana_cfg_0_flag = 0;
353530 + priv->ana_cfg_0_flag = 0;
353535 + priv->ana_cfg_2_flag = 0;
353540 + priv->ana_cfg_2_flag = 0;
353545 + priv->ana_cfg_4_flag = 0;
353550 + priv->ana_cfg_4_flag = 0;
353583 + priv->trim_flag = 0;
353588 + priv->trim_flag = 0;
353593 + priv->trim_flag = 0;
353597 + priv->trim_flag = 0;
353601 + priv->trim_flag = 0;
353647 + priv->svb_flag = 0;
353652 + priv->svb_predev5_flag = 0;
353657 + priv->svb_predev5_flag = 0;
353662 + priv->svb_predev5_flag = 0;
353667 + priv->svb_predev4_flag = 0;
353672 + priv->svb_predev4_flag = 0;
353677 + priv->svb_predev4_flag = 0;
353694 + priv->svb_predev3_flag = 0;
353699 + priv->svb_predev3_flag = 0;
353704 + priv->svb_predev3_flag = 0;
353709 + priv->svb_predev2_flag = 0;
353714 + priv->svb_predev2_flag = 0;
353719 + priv->svb_predev2_flag = 0;
353773 + priv->vbus_flag = 0;
353777 + priv->vbus_flag = 0;
353782 + priv->pwren_flag = 0;
353786 + priv->pwren_flag = 0;
353830 + return 0;
353872 + return 0;
353896 + return 0;
353908 + return 0;
353915 + for (i = 0; i < priv->num_clocks; i++) {
353920 + while (--i >= 0)
353930 + return 0;
353958 + return 0;
353967 + priv->phy_base = of_iomap(np, 0);
353984 + return 0;
353993 + for (i = 0; i < priv->num_clocks; i++) {
353995 + if (ret < 0) {
353996 + while (--i >= 0) {
354030 + return 0;
354038 + for (i = 0; i < priv->num_clocks; i++)
354049 + return 0;
354109 + return 0;
354127 + for (i = 0; i < priv->num_clocks; i++)
354137 + return 0;
354148 + return 0;
354158 + return 0;
354184 index 6533aa560..0b14869c8 100644
354197 index 4c3c67d13..0e94b4284 100644
354248 @@ -0,0 +1,663 @@
354284 + unsigned int spi_wdata : 8; /* [7:0] */
354303 +#define SPI_CLK_DIV 0x000
354304 +#define SPI_RW 0x004
354306 +#define SPI_WRITE 0
354313 +#define RTC_10MS_COUN 0x00
354314 +#define RTC_S_COUNT 0x04
354315 +#define RTC_M_COUNT 0x08
354316 +#define RTC_H_COUNT 0x0C
354317 +#define RTC_D_COUNT_L 0x10
354318 +#define RTC_D_COUNT_H 0x14
354320 +#define RTC_MR_10MS 0x18
354321 +#define RTC_MR_S 0x1C
354322 +#define RTC_MR_M 0x20
354323 +#define RTC_MR_H 0x24
354324 +#define RTC_MR_D_L 0x28
354325 +#define RTC_MR_D_H 0x2C
354327 +#define RTC_LR_10MS 0x30
354328 +#define RTC_LR_S 0x34
354329 +#define RTC_LR_M 0x38
354330 +#define RTC_LR_H 0x3C
354331 +#define RTC_LR_D_L 0x40
354332 +#define RTC_LR_D_H 0x44
354334 +#define RTC_LORD 0x48
354336 +#define RTC_IMSC 0x4C
354337 +#define RTC_INT_CLR 0x50
354338 +#define RTC_INT 0x54
354339 +#define RTC_INT_RAW 0x58
354341 +#define RTC_CLK 0x5C
354342 +#define RTC_POR_N 0x60
354343 +#define RTC_SAR_CTRL 0x68
354344 +#define RTC_CLK_CFG 0x6C
354346 +#define RTC_FREQ_H 0x144
354347 +#define RTC_FREQ_L 0x148
354349 +#define RTC_REG_LOCK1 0x190
354350 +#define RTC_REG_LOCK2 0x194
354351 +#define RTC_REG_LOCK3 0x198
354352 +#define RTC_REG_LOCK4 0x19C
354367 +#define RTC_10MS_COUN 0x00
354368 +#define RTC_S_COUNT 0x01
354369 +#define RTC_M_COUNT 0x02
354370 +#define RTC_H_COUNT 0x03
354371 +#define RTC_D_COUNT_L 0x04
354372 +#define RTC_D_COUNT_H 0x05
354374 +#define RTC_MR_10MS 0x06
354375 +#define RTC_MR_S 0x07
354376 +#define RTC_MR_M 0x08
354377 +#define RTC_MR_H 0x09
354378 +#define RTC_MR_D_L 0x0A
354379 +#define RTC_MR_D_H 0x0B
354381 +#define RTC_LR_10MS 0x0C
354382 +#define RTC_LR_S 0x0D
354383 +#define RTC_LR_M 0x0E
354384 +#define RTC_LR_H 0x0F
354385 +#define RTC_LR_D_L 0x10
354386 +#define RTC_LR_D_H 0x11
354388 +#define RTC_LORD 0x12
354390 +#define RTC_IMSC 0x13
354391 +#define RTC_INT_CLR 0x14
354392 +#define RTC_INT 0x15
354393 +#define RTC_INT_RAW 0x16
354395 +#define RTC_CLK 0x17
354396 +#define RTC_POR_N 0x18
354397 +#define RTC_SAR_CTRL 0x1A
354398 +#define RTC_CLK_CFG 0x1B
354400 +#define RTC_FREQ_H 0x51
354401 +#define RTC_FREQ_L 0x52
354403 +#define RTC_REG_LOCK1 0x64
354404 +#define RTC_REG_LOCK2 0x65
354405 +#define RTC_REG_LOCK3 0x66
354406 +#define RTC_REG_LOCK4 0x67
354411 +#define PWR_REG_ADDR 0x180C0000
354412 +#define PWR_REG_LENGTH 0x100
354414 +#define FREQ_H_DEFAULT 0x8
354415 +#define FREQ_L_DEFAULT 0x1B
354417 +#define LV_CTL_DEFAULT 0x20
354418 +#define CLK_DIV_DEFAULT 0x4
354419 +#define INT_RST_DEFAULT 0x0
354420 +#define INT_MSK_DEFAULT 0x4
354422 +#define AIE_INT_MASK BIT(0)
354424 +#define REG_LOAD_STAT BIT(0)
354450 + r_data.u32 = 0;
354451 + w_data.u32 = 0;
354456 + w_data.bits.spi_start = 0x1;
354467 + return 0;
354476 + r_data.u32 = 0;
354477 + w_data.u32 = 0;
354480 + w_data.bits.spi_start = 0x1;
354493 + return 0;
354500 + return 0;
354507 + return 0;
354535 + struct hibvt_time_str time_str = {0};
354536 + unsigned long seconds = 0;
354538 + unsigned char raw_value = 0;
354582 + unsigned long seconds = 0;
354584 + unsigned char raw_value = 0;
354590 + hibvt_rtc_write(rtc->regs, RTC_LR_10MS, 0);
354594 + hibvt_rtc_write(rtc->regs, RTC_LR_D_L, (days & 0xFF));
354608 + return 0;
354615 + struct hibvt_time_str time_str = {0};
354616 + unsigned long seconds = 0;
354618 + unsigned char int_state = 0;
354620 + memset(alrm, 0, sizeof(struct rtc_wkalrm));
354638 + return 0;
354645 + unsigned long seconds = 0;
354646 + unsigned char val = 0;
354652 + hibvt_rtc_write(rtc->regs, RTC_MR_10MS, 0);
354656 + hibvt_rtc_write(rtc->regs, RTC_MR_D_L, (days & 0xFF));
354665 + return 0;
354672 + unsigned char val = 0;
354680 + return 0;
354690 + unsigned char val = 0;
354712 + struct rtc_pll_info pll_info = {0};
354727 + /* & 0xff Obtains the lower eight bits of data. */
354728 + freq_l = (char)(pll_info.pll_value & 0xff);
354729 + /* pll_info.pll_value >> 8 & 0xf Obtains the last four bits of the higher eight bits. */
354730 + freq_h = (char)((pll_info.pll_value >> 8) & 0xf);
354735 + return 0;
354738 + char freq_l = 0;
354739 + char freq_h = 0;
354740 + struct rtc_pll_info pll_info = {0};
354750 + /* freq_h & 0xf << 8 :Shifts leftwards by 8 bits and obtains the lower 4 bits. */
354751 + pll_info.pll_value = (((unsigned)freq_h & 0xf) << 8) + freq_l;
354762 + return 0;
354781 + unsigned char val = 0;
354788 + * apb clk = 100MHz, spi_clk = 10MHz,so value= 0x4
354801 + writel(0x5A5AABCD, pwr_reg+0x58);
354805 + hibvt_rtc_write(spi_reg, RTC_REG_LOCK4, 0x5A); /* 0x5A:ctl order */
354806 + hibvt_rtc_write(spi_reg, RTC_REG_LOCK3, 0x5A); /* 0x5A:ctl order */
354807 + hibvt_rtc_write(spi_reg, RTC_REG_LOCK2, 0xAB); /* 0xAB:ctl order */
354808 + hibvt_rtc_write(spi_reg, RTC_REG_LOCK1, 0xCD); /* 0xCD:ctl order */
354818 + hibvt_rtc_write(spi_reg, RTC_CLK_CFG, 0x02);
354823 + hibvt_rtc_write(spi_reg, RTC_CLK_CFG, 0x03);
354826 + hibvt_rtc_write(spi_reg, RTC_CLK_CFG, 0x01);
354839 + return 0;
354852 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
354859 + rtc->rtc_irq = platform_get_irq(pdev, 0);
354861 + hibvt_rtc_alm_interrupt, 0, pdev->name, rtc);
354882 + return 0;
354887 + return 0;
354943 @@ -0,0 +1,659 @@
354974 +#define UFS_AHIT_AH8ITV_MASK 0x3FF
354975 +#define UFS_AHIT_AUTOH8_TIMER 0x0c01
354977 +#define UFS_AHIT_OFF 0x18
354978 +#define UFS_UTRLRSR_OFF 0x60
354979 +#define UFS_UTMRLRSR_OFF 0x80
354980 +#define UFS_BUSTHRTL_OFF 0xC0
354989 +#define TX_SLEEP_CONTROL 0x00c80000
354990 +#define RX_SLEEP_CONTROL 0x00c60000
354992 +#define RG_PLL_PRE_DIV 0x00c20000
354993 +#define RG_PLL_SWC_EN 0x00c90000
354994 +#define RG_PLL_FBK_S 0x00c40000
354995 +#define RG_PLL_FBK_P 0x00c30000
354996 +#define RG_PLL_TXHSGR 0x00cf0000
354997 +#define RG_PLL_RXHSGR 0x00cd0000
354998 +#define RG_PLL_TXLSGR 0x00d00000
354999 +#define RG_PLL_RXLSGR 0x00ce0000
355008 + {0x007e0000, {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}},
355009 + {0x007e0001, {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}},
355010 + {0x00fc0004, {0x1f, 0x1f, 0x1b, 0x1b, 0x1b, 0x1b, 0x00}},
355011 + {0x00fc0005, {0x1f, 0x1f, 0x1b, 0x1b, 0x1b, 0x1b, 0x00}},
355012 + {0x00fd0004, {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}},
355013 + {0x00fd0005, {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}},
355014 + {0x007f0000, {0x24, 0x22, 0x21, 0x21, 0x13, 0x13, 0x00}},
355015 + {0x007f0001, {0x24, 0x22, 0x21, 0x21, 0x13, 0x13, 0x00}},
355016 + {0x007d0000, {0x24, 0x22, 0x21, 0x21, 0x13, 0x13, 0x00}},
355017 + {0x007d0001, {0x24, 0x22, 0x21, 0x21, 0x13, 0x13, 0x00}},
355018 + {0x00370000, {0x26, 0x26, 0x23, 0x23, 0x20, 0x20, 0x00}},
355019 + {0x00370001, {0x26, 0x26, 0x23, 0x23, 0x20, 0x20, 0x00}},
355020 + {0x007b0000, {0x26, 0x26, 0x23, 0x23, 0x20, 0x20, 0x00}},
355021 + {0x007b0001, {0x26, 0x26, 0x23, 0x23, 0x20, 0x20, 0x00}}
355037 + for (i = 0; i < sizeof(reglist_pmc) / sizeof(reglist_pmc[0]); i++)
355038 + ufshcd_dme_set_attr(hba, reglist_pmc[i].addr, 0x0,
355055 + ufshcd_dme_get(hba, 0xD0100000, &value);
355062 + ufshcd_dme_set_attr(hba, 0xd0000000, 0x00, 0x01, DME_LOCAL);
355124 + ufshcd_dme_set_attr(hba, attr_mrx0(SKP_DET_SEL), 0x00, SKP_DET_SEL_EN,
355127 + ufshcd_dme_set_attr(hba, attr_mrx1(SKP_DET_SEL), 0x00, SKP_DET_SEL_EN,
355131 + ufshcd_dme_set_attr(hba, 0xdf0000, 0x00, (VCO_AUTO_CHG_EN | VCO_FORCE_ON_EN),
355135 + ufshcd_dme_set_attr(hba, attr_mrx0(RX_SQ_VREF), 0x00, RX_SQ_VREF_175,
355138 + ufshcd_dme_set_attr(hba, attr_mrx1(RX_SQ_VREF), 0x00, RX_SQ_VREF_175,
355142 + ufshcd_dme_set_attr(hba, attr_mrx0(0xeb), 0x00, 0x60, DME_LOCAL);
355144 + ufshcd_dme_set_attr(hba, attr_mrx1(0xeb), 0x00, 0x60, DME_LOCAL);
355147 + ufshcd_dme_set_attr(hba, attr_mrx0(0x0e), 0x00, 0x64, DME_LOCAL);
355149 + ufshcd_dme_set_attr(hba, attr_mrx1(0x0e), 0x00, 0x64, DME_LOCAL);
355151 + ufshcd_dme_set_attr(hba, attr_mrx0(0xef), 0x00, 0xfa, DME_LOCAL);
355153 + ufshcd_dme_set_attr(hba, attr_mrx1(0xef), 0x00, 0xfa, DME_LOCAL);
355156 + ufshcd_dme_set_attr(hba, attr_mrx0(AD_DIF_P_LS_TIMEOUT_VAL), 0x00,
355159 + ufshcd_dme_set_attr(hba, attr_mrx1(AD_DIF_P_LS_TIMEOUT_VAL), 0x00,
355162 + ufshcd_dme_set_attr(hba, 0x00F40004, 0x00, 0x1, DME_LOCAL);
355164 + ufshcd_dme_set_attr(hba, 0x00F40005, 0x00, 0x1, DME_LOCAL);
355167 + ufshcd_dme_set_attr(hba, 0x00F20004, 0x00, 0x3, DME_LOCAL);
355169 + ufshcd_dme_set_attr(hba, 0x00F20005, 0x00, 0x3, DME_LOCAL);
355172 + ufshcd_dme_set_attr(hba, 0x00FB0004, 0x00, 0x3, DME_LOCAL);
355174 + ufshcd_dme_set_attr(hba, 0x00FB0005, 0x00, 0x3, DME_LOCAL);
355177 + ufshcd_dme_set_attr(hba, 0x00f60004, 0x00, 0x2, DME_LOCAL);
355179 + ufshcd_dme_set_attr(hba, 0x00f60005, 0x00, 0x2, DME_LOCAL);
355182 + ufshcd_dme_set_attr(hba, 0x000a0004, 0x00, 0x1e, DME_LOCAL);
355184 + ufshcd_dme_set_attr(hba, 0x000a0005, 0x00, 0x1e, DME_LOCAL);
355187 + ufshcd_dme_set_attr(hba, 0x00d40000, 0x00, 0x31, DME_LOCAL);
355189 + ufshcd_dme_set_attr(hba, 0x00730000, 0x00, 0x00000004,
355191 + ufshcd_dme_set_attr(hba, 0x00730001, 0x00, 0x00000004,
355204 + ufshcd_dme_set_attr(hba, attr_mrx0(MRX_EN), 0x00, MRX_ENABLE, DME_LOCAL);
355206 + ufshcd_dme_set_attr(hba, attr_mrx1(MRX_EN), 0x00, MRX_ENABLE, DME_LOCAL);
355211 + ufshcd_dme_set_attr(hba, 0x00cf0004, 0x00, 0x02, DME_LOCAL); /* RX_STALL */
355212 + ufshcd_dme_set_attr(hba, 0x00cf0005, 0x00, 0x02, DME_LOCAL);
355213 + ufshcd_dme_set_attr(hba, 0x00d00004, 0x00, 0x02, DME_LOCAL); /* RX_SLEEP */
355214 + ufshcd_dme_set_attr(hba, 0x00d00005, 0x00, 0x02, DME_LOCAL);
355215 + ufshcd_dme_set_attr(hba, 0x00cc0004, 0x00, 0x03, DME_LOCAL); /* RX_HS_CLK_EN */
355216 + ufshcd_dme_set_attr(hba, 0x00cc0005, 0x00, 0x03, DME_LOCAL);
355217 + ufshcd_dme_set_attr(hba, 0x00cd0004, 0x00, 0x03, DME_LOCAL); /* RX_LS_CLK_EN */
355218 + ufshcd_dme_set_attr(hba, 0x00cd0005, 0x00, 0x03, DME_LOCAL);
355222 + ufshcd_dme_set_attr(hba, 0x00E90004, 0x00, 0x00,
355224 + ufshcd_dme_set_attr(hba, 0x00E90005, 0x00, 0x00, DME_LOCAL);
355225 + ufshcd_dme_set_attr(hba, 0x00EA0004, 0x00, 0x10,
355227 + ufshcd_dme_set_attr(hba, 0x00EA0005, 0x00, 0x10, DME_LOCAL);
355233 + ufshcd_dme_set_attr(hba, 0x15520000, 0x00, 0x4F, DME_LOCAL);
355235 + ufshcd_dme_set_attr(hba, 0x15540000, 0x00, 0x4F, DME_LOCAL);
355237 + ufshcd_dme_set_attr(hba, 0x15560000, 0x00, 0x4F, DME_LOCAL);
355240 + ufshcd_dme_set_attr(hba, 0x00ca0000, 0x0, 0x0, DME_LOCAL);
355242 + ufshcd_dme_set_attr(hba, 0xD0850000, 0x0, 0x1, DME_LOCAL);
355246 + ufshcd_dme_set_attr(hba, 0x155E0000, 0x0, 0x0, DME_LOCAL);
355248 + ufshcd_dme_set_attr(hba, 0xD0AB0000, 0x0, 0x0, DME_LOCAL);
355250 + ufshcd_dme_get(hba, 0xD0AB0000, &val);
355251 + if (val != 0)
355263 + return 0;
355274 + ufshcd_dme_set_attr(hba, 0x20440000, 0, 0x0, DME_LOCAL);
355276 + ufshcd_dme_set_attr(hba, 0x20450000, 0, 0x0, DME_LOCAL);
355278 + ufshcd_dme_set_attr(hba, 0x20400000, 0, 0x9, DME_LOCAL);
355281 + ufshcd_dme_set_attr(hba, 0x15a70000, 0x00, 0x80, DME_LOCAL);
355283 + ufshcd_dme_set_attr(hba, 0xd0ab0000, 0, 0x0, DME_LOCAL);
355284 + ufshcd_dme_set_attr(hba, 0xd0a00000, 0, 0xc, DME_LOCAL);
355300 + return 0;
355319 + return 0;
355327 + ufshcd_dme_set_attr(hba, 0x155c0000, 0x0, 0x0, DME_LOCAL);
355329 + ufshcd_dme_set_attr(hba, 0x15680000, 0x0, pwr_mode->gear_tx, DME_LOCAL);
355331 + ufshcd_dme_set_attr(hba, 0x15830000, 0x0, pwr_mode->gear_rx, DME_LOCAL);
355335 + ufshcd_dme_set_attr(hba, 0x156a0000, 0x0, pwr_mode->hs_rate, DME_LOCAL);
355337 + ufshcd_dme_set_attr(hba, 0x15690000, 0x0, 0x1, DME_LOCAL);
355339 + ufshcd_dme_set_attr(hba, 0x15840000, 0x0, 0x1, DME_LOCAL);
355341 + ufshcd_dme_set_attr(hba, 0x15850000, 0x0, 0x1, DME_LOCAL);
355343 + ufshcd_dme_set_attr(hba, 0x15690000, 0x0, 0x0, DME_LOCAL);
355344 + ufshcd_dme_set_attr(hba, 0x15840000, 0x0, 0x0, DME_LOCAL);
355345 + ufshcd_dme_set_attr(hba, 0x15850000, 0x0, 0x0, DME_LOCAL);
355349 + ufshcd_dme_set_attr(hba, 0x15600000, 0x0, pwr_mode->lane_tx, DME_LOCAL);
355351 + ufshcd_dme_set_attr(hba, 0x15800000, 0x0, pwr_mode->lane_rx, DME_LOCAL);
355353 + ufshcd_dme_set_attr(hba, 0x15b00000, 0x0, 0x1FFF,
355355 + ufshcd_dme_set_attr(hba, 0x15b10000, 0x0, 0xFFFF,
355357 + ufshcd_dme_set_attr(hba, 0x15b20000, 0x0, 0x7FFF,
355359 + ufshcd_dme_set_attr(hba, 0xd0410000, 0x0, 0x1FFF,
355361 + ufshcd_dme_set_attr(hba, 0xd0420000, 0x0, 0xFFFF,
355363 + ufshcd_dme_set_attr(hba, 0xd0430000, 0x0, 0x7FFF,
355365 + ufshcd_dme_set_attr(hba, 0x15b30000, 0x0, 0x1FFF,
355367 + ufshcd_dme_set_attr(hba, 0x15b40000, 0x0, 0xFFFF,
355369 + ufshcd_dme_set_attr(hba, 0x15b50000, 0x0, 0x7FFF,
355371 + ufshcd_dme_set_attr(hba, 0xd0440000, 0x0, 0x1FFF,
355373 + ufshcd_dme_set_attr(hba, 0xd0450000, 0x0, 0xFFFF,
355375 + ufshcd_dme_set_attr(hba, 0xd0460000, 0x0, 0x7FFF,
355379 + ufshcd_dme_set_attr(hba, 0xd09a0000, 0x0, 0x80000000, DME_LOCAL);
355381 + ufshcd_dme_set_attr(hba, 0xd09b0000, 0x0, 0x78000000, DME_LOCAL);
355384 + ufshcd_dme_set_attr(hba, 0x15710000, 0x0,
355387 + return 0;
355392 + {RG_PLL_PRE_DIV, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},
355393 + {RG_PLL_SWC_EN, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}},
355394 + {RG_PLL_FBK_S, {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}},
355395 + {RG_PLL_FBK_P, {0x4c, 0x41, 0x4c, 0x41, 0x4c, 0x41, 0x00}},
355396 + {RG_PLL_TXHSGR, {0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x00}},
355397 + {RG_PLL_RXHSGR, {0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x00}}
355410 + ufshcd_dme_set_attr(hba, RG_PLL_TXLSGR, 0x00, 0x07, DME_LOCAL);
355411 + ufshcd_dme_set_attr(hba, RG_PLL_RXLSGR, 0x00, 0x06, DME_LOCAL);
355413 + ufshcd_dme_set_attr(hba, RG_PLL_TXLSGR, 0x00, 0x06, DME_LOCAL);
355414 + ufshcd_dme_set_attr(hba, RG_PLL_RXLSGR, 0x00, 0x05, DME_LOCAL);
355416 + ufshcd_dme_set_attr(hba, RG_PLL_TXLSGR, 0x00, 0x05, DME_LOCAL);
355417 + ufshcd_dme_set_attr(hba, RG_PLL_RXLSGR, 0x00, 0x04, DME_LOCAL);
355419 + ufshcd_dme_set_attr(hba, RG_PLL_TXLSGR, 0x00, 0x04, DME_LOCAL);
355420 + ufshcd_dme_set_attr(hba, RG_PLL_RXLSGR, 0x00, 0x03, DME_LOCAL);
355425 + for (i = 0; i < sizeof(reglist_pll) / sizeof(reglist_pll[0]); i++)
355426 + ufshcd_dme_set_attr(hba, reglist_pll[i].addr, 0x0,
355443 + ufshcd_dme_get_attr(hba, 0xdf0000, &auto_chg, DME_LOCAL);
355467 + if (retry <= 0)
355471 + if (((value & UFS_HCS_UPMCRS_MASK) >> UFS_HCS_UPMCRS_OFF) != 0x1) {
355472 + UFS_PRINT("check HCS.UPMCRS error, HCS = 0x%x\n", value);
355477 + ufshcd_dme_set_attr(hba, 0x00c40004, 0x0, 0x80, DME_LOCAL);
355479 + ufshcd_dme_set_attr(hba, 0x00c50004, 0x0, 0x01, DME_LOCAL);
355481 + ufshcd_dme_set_attr(hba, 0x00c40005, 0x0, 0x80, DME_LOCAL);
355483 + ufshcd_dme_set_attr(hba, 0x00c50005, 0x0, 0x01, DME_LOCAL);
355518 + return 0;
355578 + return 0;
355608 @@ -0,0 +1,111 @@
355633 +#define BIT_UFS_SRST_REQ (0x1 << 12)
355634 +#define BIT_UFS_CLK_EN (0x1 << 13)
355635 +#define UFS_SRST_REQ (0x1 << 0)
355636 +#define UFS_RST_DEVICE (0x1 << 31)
355637 +#define BIT_UFS_PAD_RESET (0x1 << 15)
355638 +#define BIT_DA_UFS_RESET_DS2 (0x1 << 14)
355639 +#define BIT_DA_UFS_RESET_DS1 (0x1 << 13)
355640 +#define BIT_DA_UFS_RESET_DS0 (0x1 << 12)
355641 +#define BIT_DA_UFS_RESET_SL (0x1 << 11)
355642 +#define BIT_DA_UFS_RESET_OEN (0x1 << 10)
355643 +#define BIT_DA_UFS_RESET_PS (0x1 << 9)
355644 +#define BIT_DA_UFS_RESET_PE (0x1 << 8)
355645 +#define BIT_DA_UFS_REFCLK_DS2 (0x1 << 7)
355646 +#define BIT_DA_UFS_REFCLK_DS1 (0x1 << 6)
355647 +#define BIT_DA_UFS_REFCLK_DS0 (0x1 << 5)
355648 +#define BIT_DA_UFS_REFCLK_SL (0x1 << 4)
355649 +#define BIT_DA_UFS_REFCLK_OEN (0x1 << 3)
355650 +#define BIT_DA_UFS_REFCLK_PS (0x1 << 2)
355651 +#define BIT_DA_UFS_REFCLK_PE (0x1 << 1)
355652 +#define BIT_UFS_ENABLE (0x1 << 0)
355653 +#define MASK_DA_UFS_RESET_DS (0x7 << 12)
355654 +#define MASK_DA_UFS_REFCLK_DS (0x7 << 5)
355658 +#define UFS_HCE_RESET_BIT BIT(0)
355659 +#define UFS_HCS_DP_BIT BIT(0)
355662 +#define UFS_HCS_UPMCRS_MASK (0x3 << UFS_HCS_UPMCRS_OFF)
355669 +#define UFS_UTP_RUN_BIT BIT(0)
355670 +#define UFS_LBMCFG_DEFAULT_VALUE 0xb01
355671 +#define UFS_HCLKDIV_NORMAL_VALUE 0xFA
355672 +#define UFS_HCLKDIV_SLOW_VALUE 0x14
355673 +#define UFS_HCLKDIV_FPGA_VALUE 0x28
355676 +#define MTX_L0 0x0000
355677 +#define MTX_L1 0x0001
355678 +#define MRX_L0 0x0004
355679 +#define MRX_L1 0x0005
355689 +#define UNIPRO_DME_RESET 0xD010
355690 +#define UNIPRO_DME_LAYBER_ENABLE 0xD000
355693 +#define AD_DIF_P_LS_TIMEOUT_VAL 0x0003
355694 +#define PWM_PREPARE_TO 0x0000000A
355695 +#define SKP_DET_SEL 0x0009
355696 +#define SKP_DET_SEL_EN 0x00000001
355697 +#define MRX_EN 0x00F0
355698 +#define MRX_ENABLE (0x01 << 0)
355699 +#define RX_SQ_VREF 0x00F1
355700 +#define RX_SQ_VREF_175 0x00000002
355701 +#define VCO_AUTO_CHG 0x00DF
355702 +#define VCO_AUTO_CHG_EN (0x01 << 0)
355703 +#define VCO_FORCE_ON_EN (0x01 << 1)
355704 +#define PG_PLL_SWC_ENABLE 0x01
355705 +#define HS_R_A_FBK_P 0x41
355706 +#define HS_R_B_FBK_P 0x4C
355707 +#define HS_G_1_TXRXHSGR 0x02
355708 +#define HS_G_2_TXRXHSGR 0x01
355709 +#define HS_G_3_TXRXHSGR 0x00
355711 +#define RG_PLL_TXHS_EN 0x00C7
355712 +#define RG_PLL_TXHS_ENANBLE (0x01 << 0)
355713 +#define RG_PLL_TXHS_EN_CONTROL (0x01 << 1)
355714 +#define RG_PLL_TXLS_EN 0x00C8
355715 +#define RG_PLL_TXLS_ENABLE (0x01 << 0)
355716 +#define RG_PLL_TXLS_EN_CONTROL (0x01 << 1)
355718 +#define DWC_UFS_REG_HCLKDIV 0xFC
355739 + return 0;
355754 + hba->cd_gpio = of_get_named_gpio(np, "cd-gpio", 0);
355774 + hba->info_skip = 0;
355859 int err = 0;
355866 + return 0;
355941 + struct uic_command uic_cmd = {0};
355975 + hba->error_count = 0;
356033 + return 0;
356054 + hba->cd_wq = alloc_workqueue("ufshcd_cd_wq", WQ_FREEZABLE, 0);
356080 + UFSCARDHCD, hba) == 0) {
356100 return 0;
356128 + D_NO_DETECT = 0,
356135 + H_REMOVE = 0,
356220 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
356227 +#define SSP_CR1_MASK_BIGEND_HISI (0x1UL << 4)
356228 +#define SSP_CR1_MASK_ALTASENS_HISI (0x1UL << 6)
356230 +#define SSP_TX_FIFO_CR(r) (r + 0x28)
356231 +#define SSP_RX_FIFO_CR(r) (r + 0x2C)
356348 + GEN_MASK_BITS(0x1, SSP_CR1_MASK_ALTASENS_HISI, 6) \
356353 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
356395 + writel(0, SSP_TX_FIFO_CR(pl022->virtbase));
356396 + writel(0, SSP_RX_FIFO_CR(pl022->virtbase));
356422 + SSP_CR0_MASK_DSS, 0);
356432 + SSP_WRITE_BITS(chip->cr1, 0x1, SSP_CR1_MASK_ALTASENS_HISI, 6);
356436 SSP_CR0_MASK_DSS, 0);
356448 int status = 0, i, num_cs;
356452 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
356457 for (i = 0; i < num_cs; i++)
356497 for (i = 0; i < num_cs; i++) {
356511 if (platform_info->autosuspend_delay > 0) {
356537 return 0;
356558 .mask = 0x000fffff,
356567 + .id = 0x00800022,
356568 + .mask = 0xffffffff,
356572 { 0, 0 },
356591 - return 0;
356604 - return 0;
356650 } else if (hub->descriptor->bNbrPorts == 0) {
356652 + dev_info(hub_dev, "hub can't support USB3.0\n");
356690 + * requests is 0x3[11:8], modify the field change to 0x7.
356770 return 0;
356781 +#define DWC3_PIPE_TRANS_LIMIT_MASK (0xf << 8)
356782 +#define DWC3_PIPE_TRANS_LIMIT (0x7 << 8)
356790 +#define DWC3_EVENT_PRAM_MAX_SOFFN 0x3fff
356791 +#define DWC3_EVENT_PRAM_SOFFN_MASK 0x3fff
356793 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
356830 + * NOTICE: eps_directions bitmap[0~31] 0: out ep, 1: in ep
356833 +#define DWC3_EPS_DEFAULT_DIRECTIONS 0xaaaaaaaa
356845 +#define UDC_DISCONNECTED 0
356886 @@ -0,0 +1,446 @@
356928 +#define USB3_CTRL 0x190
356929 +#define REG_SYS_STAT 0x8c
356930 +#define PCIE_USB3_MODE_MASK (0x3 << 12)
356931 +#define USB3_PCLK_OCC_SEL (0x1 << 30)
356933 +#define PERI_USB3_GTXTHRCFG 0x2310000
356935 +#define REG_GUSB3PIPECTL0 0xc2c0
356936 +#define GTXTHRCFG 0xc108
356938 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
356939 +#define SUSPEND_USB3_SS_PHY (0x1 << 17)
356941 +#define GUSB2PHYCFG_OFFSET 0xc200
356942 +#define GCTL_OFFSET 0xc110
356943 +#define GUCTL_OFFSET 0xc12C
356944 +#define GFLADJ_OFFSET 0xc630
356946 +#define U2_FREECLK_EXISTS (0x1 << 30)
356947 +#define SOFITPSYNC (0x1 << 10)
356948 +#define REFCLKPER_MASK 0xffc00000
356949 +#define REFCLKPER_VAL 0x29
356952 +#define PLS1 (0x1 << 31)
356953 +#define DECR_MASK 0x7f000000
356954 +#define DECR_VAL 0xa
356957 +#define LPM_SEL (0x1 << 23)
356958 +#define FLADJ_MASK 0x003fff00
356959 +#define FLADJ_VAL 0x7f0
356963 +#define DOUBLE_PCIE_MODE 0x0
356964 +#define P0_PCIE_ADD_P1_USB3 (0x1 << 12)
356965 +#define DOUBLE_USB3 (0x2 << 12)
356968 +#define PCIE_X1_MODE (0x0 << 12)
356969 +#define USB3_MODE (0x1 << 12)
356995 + if (usb_priv->speed_id == 0)
357112 + return 0;
357134 + for (i = 0; i < hisi->num_clocks; i++) {
357139 + while (--i >= 0)
357147 + if (ret < 0) {
357148 + while (--i >= 0) {
357160 + return 0;
357222 + return 0;
357271 + for (i = 0; i < hisi->num_clocks; i++) {
357278 + return 0;
357295 + for (i = 0; i < hisi->num_clocks; i++) {
357310 + return 0;
357338 @@ -0,0 +1,54 @@
357386 +#define DEV_NODE_FLAG0 0
357394 index 0d95ca804..e89f7bcc9 100644
357398 WARN_ON(ret < 0);
357403 + u32 res = 0;
357407 + return 0;
357409 + for (i = 0; i < dwc->num_eps; i++) {
357493 * endpoint number. So USB endpoint 0x81 is 0x03.
357519 __dwc3_gadget_ep_set_halt(dep, 0, false);
357533 * index is 0, we will wrap backwards, skip the link TRB, and return
357557 + unsigned int chain_skip = 0;
357607 + dwc3_prepare_one_trb(dep, req, trb_length, chain, 0);
357644 return 0;
357681 return 0;
357697 return 0;
357706 + u8 num_in_eps = 0;
357707 + u8 num_out_eps = 0;
357708 + u8 epnum = 0;
357715 + for (i = 0; i < num_eps; i++) {
357716 + if (direction & 0x1)
357727 + dep->direction = !!(direction & 0x1);
357737 + if (epnum == 0 || epnum == 1) {
357750 + dep->endpoint.caps.dir_in = !!(direction & 0x1);
357751 + dep->endpoint.caps.dir_out = !(direction & 0x1);
357759 + return 0;
357772 for (epnum = 0; epnum < total; epnum++) {
357812 @@ -0,0 +1,139 @@
357847 +static int proc_dwc3_dir_cnt = 0;
357873 + return 0;
357920 + 0, dwc->parent_entry,
357932 + return 0;
357945 + if (proc_dwc3_dir_cnt == 0) {
357950 + return 0;
357961 + usb_ext->bmAttributes = cpu_to_le32(0x0);
357990 index 0b7b4d097..8075593d5 100644
358006 + common->actived = 0;
358022 common->running = 0;
358023 + common->actived = 0;
358034 for (i = 0; i < ARRAY_SIZE(common->luns); ++i)
358047 + .bFirstInterface = 0,
358050 + .bFunctionSubClass = 0,
358058 .wLockDelay = 0,
358064 + .bMaxBurst = 0,
358065 + .bmAttributes = 0,
358130 if (status < 0)
358135 uac1->ac_alt = 0;
358140 + ac_header_desc.baInterfaceNr[0] = status;
358142 uac1->as_out_alt = 0;
358150 uac1->as_in_alt = 0;
358182 + static char extension_guid[] = {0x41, 0x76, 0x9E, 0xA2, 0x04, 0xDE, 0xE3, 0x47,
358183 + 0x8B, 0x2B, 0xF4, 0x34, 0x1A, 0xFF, 0x00, 0x3B};
358189 pd->bmControls[1] = 0;
358190 pd->iProcessing = 0;
358199 + ed->baSourceID[0] = 2;
358202 + ed->bmControls[0] = 1;
358203 + ed->bmControls[1] = 0;
358204 + ed->iExtension = 0;
358210 ctl_cls[0] = NULL; /* assigned elsewhere by configfs */
358222 ctl_cls[0] = NULL; /* assigned elsewhere by configfs */
358320 + idx = 0;
358322 + i = 0;
358324 + *pg != '\0' && *pg != '\n')
358326 + while ((pg - page < len) && (*pg == '\0' || *pg == '\n'))
358328 + buf[i] = '\0';
358329 + ret = kstrtou8(buf, 0, &pd->bmControls[idx++]);
358330 + if (ret < 0)
358422 + for (result = 0, i = 0; i < ed->bControlSize; ++i) {
358485 + idx = 0;
358487 + i = 0;
358489 + *pg != '\0' && *pg != '\n')
358491 + while ((pg - page < len) && (*pg == '\0' || *pg == '\n'))
358493 + buf[i] = '\0';
358494 + ret = kstrtou8(buf, 0, &cd->bmControls[idx++]);
358495 + if (ret < 0)
358527 UVCG_UNCOMPRESSED = 0,
358603 + ret = kstrtou##bits(page, 0, &num); \
358662 + for (result = 0, i = 0; i < frm->frame.b_frame_interval_type; ++i) {
358681 + int ret = 0, n = 0;
358761 + h->frame.dw_bytes_per_line = cpu_to_le32(0);
358811 'Y', 'U', 'Y', '2', 0x00, 0x00, 0x10, 0x00,
358812 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71
358816 + 'N', 'V', '2', '1', 0x00, 0x00, 0x10, 0x00,
358817 + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71
358833 h->desc.bAspectRatioX = 0;
358834 h->desc.bAspectRatioY = 0;
358925 + ret = kstrtou8(page, 0, &num); \
358992 + 'H', '2', '6', '4', 0x00, 0x00, 0x10, 0x00,
358993 + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71
359007 + h->desc.bAspectRatioX = 0;
359008 + h->desc.bAspectRatioY = 0;
359009 + h->desc.bmInterfaceFlags = 0;
359010 + h->desc.bCopyProtect = 0;
359063 + return 0;
359099 + return 0;
359150 { 0, V4L2_PIX_FMT_MJPEG },
359151 + { 0, V4L2_PIX_FMT_H264 },
359183 + int ttllen = 0;
359187 + for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++) {
359206 + video->queue.buf_used = 0;
359245 if (ret < 0) {
359276 for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
359279 + for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++)
359311 + for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
359321 + for (sg_idx = 0 ; sg_idx < num_sgs ; sg_idx++) {
359329 + video->req[i]->length = 0;
359336 for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
359347 return 0;
359373 #define YISO_VENDOR_ID 0x0EAB
359374 #define YISO_PRODUCT_U893 0xC893
359377 +#define MEIG_VENDOR_ID 0x2DEE
359378 +#define MEIG_PRODUCT_SLM790 0x4D20
359392 index c989f777b..0bcb9027b 100644
359495 return 0;
359502 - v9fs_stat2inode(st, d_inode(dentry), dentry->d_sb, 0);
359529 return 0;
359536 - v9fs_stat2inode_dotl(st, d_inode(dentry), 0);
359601 +"block group start=%llu len=%llu flags=0x%llx doesn't match with chunk start=%llu len=%llu flags=0…
359608 + ret = 0;
359624 if (ret > 0)
359629 leaf = path->nodes[0];
359630 - btrfs_item_key_to_cpu(leaf, &found_key, path->slots[0]);
359631 + slot = path->slots[0];
359643 + if (ret < 0)
359652 - btrfs_item_ptr_offset(leaf, path->slots[0]),
359663 int fake_offset = 0;
359665 - int short_len = 0, fill_len = 0;
359668 int ret = 0;
359741 + type, de, d_createtime) == 0;
359750 + DT_DIR, de, d_createtime) == 0;
359759 + DT_DIR, de, d_createtime) == 0;
359767 + if (ctx->pos == 0) {
359794 + int fake_offset = 0;
359796 + int short_len = 0, fill_len = 0;
359797 + int ret = 0;
359809 + cpos = 0;
359822 + nr_slots = 0;
359828 + if (de->name[0] == DELETED_FLAG)
359842 + if (status < 0) {
359863 + if (short_len == 0)
359872 + fill_len = 0;
359878 + if (short_len == 0)
359889 + memset(d_createtime, 0, 8);
359916 + fake_offset = 0;
359939 + int reclen = 0;
359941 + int long_len = 0;
359943 + int short_len = 0;
359989 + if (__put_user(0, dirent->d_name + name_len))
359994 + if (__put_user(0, dirent->d_name + long_len))
360002 + u64 u_size = 0;
360018 + return 0;
360038 + buf.error = 0;
360039 + buf.result = 0;
360040 + buf.usecount = 0;
360057 + if (ret >= 0)
360074 + if (put_user(0, &(direntallbuf->direntall.d_reclen)))
360076 + if (put_user(0, &(direntallbuf->d_usecount)))
360078 + short_only = 0;
360108 memset(bhs[n]->b_data, 0, sb->s_blocksize);
360119 de = (struct msdos_dir_entry *)bhs[0]->b_data;
360122 lock_buffer(bhs[0]);
360125 memcpy(de[0].name, MSDOS_DOT, MSDOS_NAME);
360128 de[0].size = de[1].size = 0;
360129 memset(de + 2, 0, sb->s_blocksize - 2 * sizeof(*de));
360130 set_buffer_uptodate(bhs[0]);
360132 unlock_buffer(bhs[0]);
360134 mark_buffer_dirty_inode(bhs[0], dir);
360175 err = 0;
360177 + return 0;
360214 + return 0;
360232 return 0;
360239 + inode->i_ctime = inode->i_mtime = ((struct timespec64) { get_seconds(), 0 });
360300 + int err = 0;
360304 + return 0;
360309 + return 0;
360327 + raw_entry->size = 0;
360329 + if ((raw_entry->start != 0) || (raw_entry->starthi != 0)) {
360404 + month = max(1, (date >> 5) & 0xf);
360405 + day = max(1, date & 0x1f) - 1;
360407 + d_createtime[0] = year;
360411 + d_createtime[4] = ((time >> 5) & 0x3f); /*min*/
360412 + d_createtime[5] = (time & 0x1f); /*second 2s*/
360455 return 0;
360457 + return 0;
360460 ubifs_assert(c, 0);
360467 @@ -0,0 +1,105 @@
360529 +#define HI3516A_SYSAXI_CLK 0
360561 +#define HI3516A_CRG_NR_RSTS 0x12c
360578 @@ -0,0 +1,98 @@
360682 @@ -0,0 +1,89 @@
360777 @@ -0,0 +1,100 @@
360883 @@ -0,0 +1,89 @@
360978 @@ -0,0 +1,89 @@
361073 @@ -0,0 +1,86 @@
361125 +#define HI3518EV20X_SYSAPB_CLK 0
361165 @@ -0,0 +1,89 @@
361260 @@ -0,0 +1,127 @@
361393 @@ -0,0 +1,97 @@
361417 +/* interrupt specifier cell 0 */
361418 +#define GIC_SPI 0
361459 +#define HI3521A_SYSAPB_CLK 0
361475 +#define HI3521A_CRG_NR_RSTS 0xB8
361496 @@ -0,0 +1,94 @@
361596 @@ -0,0 +1,105 @@
361620 +/* interrupt specifier cell 0 */
361621 +#define GIC_SPI 0
361665 +#define HI3531A_PERIAXI_CLK 0
361686 +#define HI3531A_CRG_NR_RSTS 0x250
361707 @@ -0,0 +1,132 @@
361845 @@ -0,0 +1,132 @@
361983 @@ -0,0 +1,82 @@
362050 +#define HI3536DV100_CRG_NR_RSTS 0x200
362071 @@ -0,0 +1,121 @@
362198 @@ -0,0 +1,98 @@
362302 @@ -0,0 +1,176 @@
362439 +#define HI3559AV100_SHUB_SOURCE_SOC_24M 0
362484 @@ -0,0 +1,98 @@
362597 BLK_SEG_BOUNDARY_MASK = 0xFFFFFFFFUL,
362633 @@ -0,0 +1,54 @@
362693 @@ -0,0 +1,65 @@
362697 +#define DMAC_ERROR_BASE 0x64
362699 +#define DMAC_CHN_SUCCESS (DMAC_ERROR_BASE + 0x10)
362700 +#define DMAC_CHN_ERROR (DMAC_ERROR_BASE + 0x11)
362701 +#define DMAC_CHN_TIMEOUT (DMAC_ERROR_BASE + 0x12)
362702 +#define DMAC_CHN_ALLOCAT (DMAC_ERROR_BASE + 0x13)
362703 +#define DMAC_CHN_VACANCY (DMAC_ERROR_BASE + 0x14)
362704 +#define DMAC_NOT_FINISHED (DMAC_ERROR_BASE + 0xe)
362792 @@ -0,0 +1,477 @@
362818 +#define _64K (0x10000UL)
362819 +#define _128K (0x20000UL)
362820 +#define _256K (0x40000UL)
362821 +#define _512K (0x80000UL)
362822 +#define _1M (0x100000UL)
362823 +#define _2M (0x200000UL)
362824 +#define _4M (0x400000UL)
362825 +#define _8M (0x800000UL)
362826 +#define _16M (0x1000000UL)
362827 +#define _32M (0x2000000UL)
362828 +#define _64M (0x4000000UL)
362829 +#define _128M (0x8000000UL)
362830 +#define _256M (0x10000000UL)
362831 +#define _512M (0x20000000UL)
362832 +#define _1G (0x40000000ULL)
362833 +#define _2G (0x80000000ULL)
362834 +#define _4G (0x100000000ULL)
362835 +#define _8G (0x200000000ULL)
362836 +#define _16G (0x400000000ULL)
362837 +#define _64G (0x1000000000ULL)
362840 +#define FMC_CFG 0x00
362841 +#define FMC_CFG_SPI_NAND_SEL(_type) (((_size) & 0x3) << 11)
362843 +#define FMC_CFG_OP_MODE_MASK BIT_MASK(0)
362844 +#define FMC_CFG_OP_MODE_BOOT 0
362846 +#define SPI_NOR_ADDR_MODE_3BYTES (0x0 << 10)
362847 +#define SPI_NOR_ADDR_MODE_4BYTES (0x1 << 10)
362849 +#define FMC_CFG_BLOCK_SIZE(_size) (((_size) & 0x3) << 8)
362850 +#define FMC_CFG_ECC_TYPE(_type) (((_type) & 0x7) << 5)
362851 +#define FMC_CFG_PAGE_SIZE(_size) (((_size) & 0x3) << 3)
362852 +#define FMC_CFG_FLASH_SEL(_type) (((_type) & 0x3) << 1)
362853 +#define FMC_CFG_OP_MODE(_mode) ((_mode) & 0x1)
362855 +#define SPI_NAND_MFR_OTHER 0x0
362856 +#define SPI_NAND_MFR_WINBOND 0x1
362857 +#define SPI_NAND_MFR_ESMT 0x2
362858 +#define SPI_NAND_MFR_MICRON 0x3
362861 +#define SPI_NAND_SEL_MASK (0x3 << SPI_NAND_SEL_SHIFT)
362863 +#define SPI_NOR_ADDR_MODE_3_BYTES 0x0
362864 +#define SPI_NOR_ADDR_MODE_4_BYTES 0x1
362867 +#define SPI_NOR_ADDR_MODE_MASK (0x1 << SPI_NOR_ADDR_MODE_SHIFT)
362869 +#define BLOCK_SIZE_64_PAGE 0x0
362870 +#define BLOCK_SIZE_128_PAGE 0x1
362871 +#define BLOCK_SIZE_256_PAGE 0x2
362872 +#define BLOCK_SIZE_512_PAGE 0x3
362874 +#define BLOCK_SIZE_MASK (0x3 << 8)
362876 +#define ECC_TYPE_0BIT 0x0
362877 +#define ECC_TYPE_8BIT 0x1
362878 +#define ECC_TYPE_16BIT 0x2
362879 +#define ECC_TYPE_24BIT 0x3
362880 +#define ECC_TYPE_28BIT 0x4
362881 +#define ECC_TYPE_40BIT 0x5
362882 +#define ECC_TYPE_64BIT 0x6
362885 +#define ECC_TYPE_MASK (0x7 << ECC_TYPE_SHIFT)
362887 +#define PAGE_SIZE_2KB 0x0
362888 +#define PAGE_SIZE_4KB 0x1
362889 +#define PAGE_SIZE_8KB 0x2
362890 +#define PAGE_SIZE_16KB 0x3
362893 +#define PAGE_SIZE_MASK (0x3 << PAGE_SIZE_SHIFT)
362895 +#define FLASH_TYPE_SPI_NOR 0x0
362896 +#define FLASH_TYPE_SPI_NAND 0x1
362897 +#define FLASH_TYPE_NAND 0x2
362898 +#define FLASH_TYPE_UNKNOWN 0x3
362900 +#define FLASH_TYPE_SEL_MASK (0x3 << 1)
362901 +#define GET_SPI_FLASH_TYPE(_reg) (((_reg) >> 1) & 0x3)
362903 +#define FMC_GLOBAL_CFG 0x04
362906 +#define FLASH_TYPE_SEL_MASK (0x3 << 1)
362907 +#define FMC_CFG_FLASH_SEL(_type) (((_type) & 0x3) << 1)
362910 +#define FMC_SPI_TIMING_CFG 0x08
362911 +#define TIMING_CFG_TCSH(nr) (((nr) & 0xf) << 8)
362912 +#define TIMING_CFG_TCSS(nr) (((nr) & 0xf) << 4)
362913 +#define TIMING_CFG_TSHSL(nr) ((nr) & 0xf)
362915 +#define CS_HOLD_TIME 0x6
362916 +#define CS_SETUP_TIME 0x6
362917 +#define CS_DESELECT_TIME 0xf
362919 +#define FMC_PND_PWIDTH_CFG 0x0c
362920 +#define PWIDTH_CFG_RW_HCNT(_n) (((_n) & 0xf) << 8)
362921 +#define PWIDTH_CFG_R_LCNT(_n) (((_n) & 0xf) << 4)
362922 +#define PWIDTH_CFG_W_LCNT(_n) ((_n) & 0xf)
362924 +#define RW_H_WIDTH (0xa)
362925 +#define R_L_WIDTH (0xa)
362926 +#define W_L_WIDTH (0xa)
362928 +#define FMC_INT 0x18
362934 +#define FMC_INT_ERR_INVALID_MASK (0x8)
362936 +#define FMC_INT_ERR_VALID_MASK (0x4)
362938 +#define FMC_INT_OP_DONE BIT(0)
362940 +#define FMC_INT_EN 0x1c
362948 +#define FMC_INT_EN_OP_DONE BIT(0)
362950 +#define FMC_INT_CLR 0x20
362958 +#define FMC_INT_CLR_OP_DONE BIT(0)
362960 +#define FMC_INT_CLR_ALL 0xff
362962 +#define FMC_CMD 0x24
362963 +#define FMC_CMD_CMD2(_cmd) (((_cmd) & 0xff) << 8)
362964 +#define FMC_CMD_CMD1(_cmd) ((_cmd) & 0xff)
362966 +#define FMC_ADDRH 0x28
362967 +#define FMC_ADDRH_SET(_addr) ((_addr) & 0xff)
362969 +#define FMC_ADDRL 0x2c
362970 +#define FMC_ADDRL_BLOCK_MASK(_page) ((_page) & 0xffffffc0)
362971 +#define FMC_ADDRL_BLOCK_H_MASK(_page) (((_page) & 0xffff) << 16)
362972 +#define FMC_ADDRL_BLOCK_L_MASK(_page) ((_page) & 0xffc0)
362974 +#define READ_ID_ADDR 0x00
362975 +#define PROTECT_ADDR 0xa0
362976 +#define FEATURE_ADDR 0xb0
362977 +#define STATUS_ADDR 0xc0
362978 +#define FMC_OP_CFG 0x30
362981 +#define OP_CFG_MEM_IF_TYPE(_type) (((_type) & 0x7) << 7)
362982 +#define OP_CFG_ADDR_NUM(_addr) (((_addr) & 0x7) << 4)
362983 +#define OP_CFG_DUMMY_NUM(_dummy) ((_dummy) & 0xf)
362984 +#define OP_CFG_OEN_EN (0x1 << 13)
362987 +#define IF_TYPE_MASK (0x7 << IF_TYPE_SHIFT)
362993 +#define FMC_SPI_OP_ADDR 0x34
362995 +#define FMC_DATA_NUM 0x38
362996 +#define FMC_DATA_NUM_CNT(_n) ((_n) & 0x3fff)
363020 +#define FEATURE_QE_ENABLE (1 << 0)
363022 +#define FMC_OP 0x3c
363031 +#define FMC_OP_REG_OP_START BIT(0)
363033 +#define FMC_OP_DMA 0x68
363034 +#define FMC_DMA_LEN 0x40
363035 +#define FMC_DMA_LEN_SET(_len) ((_len) & 0x0fffffff)
363037 +#define FMC_DMA_AHB_CTRL 0x48
363041 +#define FMC_DMA_AHB_CTRL_BURST4_EN BIT(0)
363049 +#define FMC_DMA_SADDR_D0 0x4c
363051 +#define FMC_DMA_SADDR_D1 0x50
363053 +#define FMC_DMA_SADDR_D2 0x54
363055 +#define FMC_DMA_SADDR_D3 0x58
363057 +#define FMC_DMA_SADDR_OOB 0x5c
363060 +#define FMC_DMA_SADDRH_D0 0x200
363061 +#define FMC_DMA_SADDRH_SHIFT 0x3LL
363064 +#define FMC_DMA_SADDRH_OOB 0x210
363067 +#define FMC_DMA_BLK_SADDR 0x60
363068 +#define FMC_DMA_BLK_SADDR_SET(_addr) ((_addr) & 0xffffff)
363070 +#define FMC_DMA_BLK_LEN 0x64
363071 +#define FMC_DMA_BLK_LEN_SET(_len) ((_len) & 0xffff)
363073 +#define FMC_OP_CTRL 0x68
363074 +#define OP_CTRL_RD_OPCODE(code) (((code) & 0xff) << 16)
363075 +#define OP_CTRL_WR_OPCODE(code) (((code) & 0xff) << 8)
363076 +#define OP_CTRL_RD_OP_SEL(_op) (((_op) & 0x3) << 4)
363079 +#define OP_CTRL_DMA_OP_READY BIT(0)
363081 +#define RD_OP_READ_ALL_PAGE 0x0
363082 +#define RD_OP_READ_OOB 0x1
363083 +#define RD_OP_BLOCK_READ 0x2
363086 +#define RD_OP_MASK (0x3 << RD_OP_SHIFT)
363088 +#define OP_TYPE_DMA 0x0
363089 +#define OP_TYPE_REG 0x1
363091 +#define FMC_OP_READ 0x0
363092 +#define FMC_OP_WRITE 0x1
363093 +#define RW_OP_READ 0x0
363094 +#define RW_OP_WRITE 0x1
363096 +#define FMC_OP_PARA 0x70
363099 +#define FMC_BOOT_SET 0x74
363103 +#define FMC_STATUS 0xac
363106 +#define FMC_VERSION 0xbc
363111 +#define HIFMC_VER_100 (0x100)
363118 +#define HIFMC_ECC_ERR_NUM0_BUF0 0xc0
363119 +#define GET_ECC_ERR_NUM(_i, _reg) (((_reg) >> ((_i) * 8)) & 0xff)
363121 +#define DISABLE 0
363124 +#define HIFMC_REG_ADDRESS_LEN 0x200
363132 +#define GET_OP 0
363135 +#define STATUS_ECC_MASK (0x3 << 4)
363139 +#define STATUS_OIP_MASK (1 << 0)
363141 +#define FMC_VERSION 0xbc
363144 +#define HIFMC_VER_100 (0x100)
363151 + ((host->addr_value[0] >> 16) | (host->addr_value[1] << 16))
363171 +#define FMC_WAIT_TIMEOUT 0x2000000
363182 + } while (0)
363193 + } while (0)
363204 + } while (0)
363206 +#define BT_DBG 0 /* Boot init debug print */
363207 +#define ER_DBG 0 /* Erase debug print */
363208 +#define WR_DBG 0 /* Write debug print */
363209 +#define RD_DBG 0 /* Read debug print */
363210 +#define QE_DBG 0 /* Quad Enable debug print */
363211 +#define OP_DBG 0 /* OP command debug print */
363212 +#define DMA_DB 0 /* DMA read or write debug print */
363213 +#define AC_DBG 0 /* 3-4byte Address Cycle */
363214 +#define SR_DBG 0 /* Status Register debug print */
363215 +#define CR_DBG 0 /* Config Register debug print */
363216 +#define FT_DBG 0 /* Features debug print */
363217 +#define WE_DBG 0 /* Write Enable debug print */
363218 +#define BP_DBG 0 /* Block Protection debug print */
363219 +#define EC_DBG 0 /* enable/disable ecc0 and randomizer */
363220 +#define PM_DBG 0 /* power management debug */
363226 + } while (0)
363236 + } while (0)
363287 +#define MMC_HOST_TYPE_MMC 0 /* MMC card */
363300 +#define MMC_CARD_UNINIT 0
363315 +#define MTD_ERASE_PENDING 0x01
363316 +#define MTD_ERASING 0x02
363317 +#define MTD_ERASE_SUSPEND 0x04
363318 +#define MTD_ERASE_DONE 0x08
363319 +#define MTD_ERASE_FAILED 0x10
363407 - * @mtd->erasesize. Of course we expect @mtd->erasesize to be != 0.
363445 #define NAND_MFR_AMD 0x01
363446 #define NAND_MFR_MACRONIX 0xc2
363447 #define NAND_MFR_EON 0x92
363448 +#define NAND_MFR_WINBOND 0xef
363449 +#define NAND_MFR_ATO 0x9b
363450 +#define NAND_MFR_MXIC 0xc2
363451 +#define NAND_MFR_ALL_FLASH 0xc1
363452 +#define NAND_MFR_PARAGON 0xa1
363453 #define NAND_MFR_SANDISK 0x45
363454 #define NAND_MFR_INTEL 0x89
363455 #define NAND_MFR_ATO 0x9b
363456 -#define NAND_MFR_WINBOND 0xef
363457 +#define NAND_MFR_GD_ESMT 0xc8
363458 +#define NAND_MFR_HEYANGTEK 0xc9
363459 +#define NAND_MFR_DOSILICON 0xe5
363460 +#define NAND_MFR_FIDELIX 0xf8
363478 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
363482 +#define SNOR_MFR_WINBOND 0xef
363483 +#define SNOR_MFR_ESMT 0x8c
363484 +#define SNOR_MFR_GD 0xc8
363485 +#define SNOR_MFR_XTX 0x0b
363486 +#define SNOR_MFR_PUYA 0x85
363495 +#define _2M (0x200000UL)
363496 +#define _4M (0x400000UL)
363497 +#define _8M (0x800000UL)
363498 +#define _16M (0x1000000UL)
363499 +#define _32M (0x2000000UL)
363504 +#define DEBUG_SPI_NOR_BP 0
363507 +#define SPI_NOR_SR_BP_WIDTH_4 0xf
363510 +#define SPI_NOR_SR_BP_WIDTH_3 0x7
363513 +#define LOCK_LEVEL_MAX(bp_num) (((0x01) << bp_num) - 1)
363523 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
363526 +#define SPINOR_OP_RDSR3 0x15 /* Read Status Register-3 */
363527 +#define SPINOR_OP_WRSR3 0x11 /* Write Status Register-3 1 byte*/
363529 +#define SPINOR_OP_WRCR 0x31 /* Config register write */
363531 +#define CR_DUMMY_CYCLE (0x03 << 6) /* Macronix dummy cycle bits */
363535 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
363580 * Return: 0 for success, others for failure.
363729 @@ -0,0 +1,60 @@
363808 #define I2C_PEC 0x0708 /* != 0 to use PEC with SMBus */
363809 #define I2C_SMBUS 0x0720 /* SMBus transfer */
363811 +#define I2C_CONFIG_MUL_REG 0x070c
363812 +#define I2C_CONFIG_FLAGS 0x070d
363830 #define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
363831 #define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_NOSTART */
363832 #define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
363833 +#define I2C_M_16BIT_REG 0x0002 /* indicate reg bit-width is 16bit */
363834 +#define I2C_M_16BIT_DATA 0x0008 /* indicate data bit-width is 16bit */
363835 +#define I2C_M_DMA 0x0004 /* indicate use dma mode */
363873 #define FAT_IOCTL_SET_ATTRIBUTES _IOW('r', 0x11, __u32)
363874 /*Android kernel has used 0x12, so we use 0x13*/
363875 #define FAT_IOCTL_GET_VOLUME_ID _IOR('r', 0x13, __u32)
363878 +#define VFAT_IOCTL_READDIR_ALL _IOR('r', 0x14, struct fat_direntall_buf)
363892 #define UVC_EVENT_FIRST (V4L2_EVENT_PRIVATE_START + 0)
363893 #define UVC_EVENT_CONNECT (V4L2_EVENT_PRIVATE_START + 0)
364004 + if (hi3516_usb_mode != NULL && strcmp(hi3516_usb_mode, "host") == 0) {
364021 parse_args("Setting init args", after_dashes, NULL, 0, -1, -1,
364069 phys_addr_t selected_size = 0;
364135 .cpu_bitmap = { [BITS_TO_LONGS(NR_CPUS)] = 0},
364180 return 0;
364191 - unsigned char present = 0;
364235 - for (i = 0; i < nr; i++, pgoff++)
364238 - for (i = 0; i < nr; i++)
364239 - vec[i] = 0;
364252 + memset(vec, 0, nr);
364254 return 0;
364274 + *vec = 0;
364330 index 1011625a0..0ff0389e2 100644
364456 for (i = 0; i < gm->gm_pf_num; i++) {
364476 struct kvec *argv = &rqstp->rq_arg.head[0];
364477 struct kvec *resv = &rqstp->rq_res.head[0];
364504 - return 0;
364529 return 0;
364534 + return svc_find_xprt(serv, "rdma-bc", net, AF_UNSPEC, 0);
364569 return 0;
364575 + return svc_find_xprt(serv, "tcp-bc", net, AF_UNSPEC, 0);
364611 int ret = 0;
364656 if (count == 0)
364663 @@ -9,7 +9,7 @@ ret=0
364669 VERBOSE=0
364681 + $IP -6 rule add table main suppress_prefixlength 0
364683 + $IP -6 rule del table main suppress_prefixlength 0
364687 + return 0