Lines Matching refs:phy_cfg
8188 + union phy_configure_opts phy_cfg = {0};
8190 + phy_cfg.dp.lanes = 0;
8191 + phy_cfg.dp.set_lanes = true;
8192 + ret = phy_configure(dp->phy, &phy_cfg);
10004 + union phy_configure_opts phy_cfg = {0};
10006 + phy_cfg.dp.lanes = dp->link_train.lane_count;
10007 + phy_cfg.dp.link_rate =
10009 + phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp);
10010 + phy_cfg.dp.set_lanes = false;
10011 + phy_cfg.dp.set_rate = true;
10012 + phy_cfg.dp.set_voltages = false;
10013 + ret = phy_configure(dp->phy, &phy_cfg);
10054 + union phy_configure_opts phy_cfg = {0};
10056 + phy_cfg.dp.lanes = dp->link_train.lane_count;
10057 + phy_cfg.dp.set_lanes = true;
10058 + phy_cfg.dp.set_rate = false;
10059 + phy_cfg.dp.set_voltages = false;
10060 + ret = phy_configure(dp->phy, &phy_cfg);
10089 + union phy_configure_opts phy_cfg = {0};
10099 + phy_cfg.dp.voltage[lane] = vs;
10100 + phy_cfg.dp.pre[lane] = pe;
10103 + phy_cfg.dp.lanes = dp->link_train.lane_count;
10104 + phy_cfg.dp.link_rate =
10106 + phy_cfg.dp.set_lanes = false;
10107 + phy_cfg.dp.set_rate = false;
10108 + phy_cfg.dp.set_voltages = true;
10109 + ret = phy_configure(dp->phy, &phy_cfg);
47114 * @phy_cfg: phy register configuration, assigned by driver data.
47133 const struct rockchip_usb2phy_cfg *phy_cfg;
47618 + if (rphy->phy_cfg->vbus_detect)
47619 + rphy->phy_cfg->vbus_detect(rphy, vbus_det_en);
47645 + for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
47684 + for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
47988 - property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
48003 + property_enable(base, &rphy->phy_cfg->chg_det.chg_mode, true);
48040 - property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
48041 + if (rphy->phy_cfg->chg_det.chg_mode.offset !=
48043 + property_enable(base, &rphy->phy_cfg->chg_det.chg_mode, false);
48245 - rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
48314 - rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
48316 + for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
48529 + rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
48581 - rphy->phy_cfg = &phy_cfgs[index];
48595 - if (!rphy->phy_cfg) {
48616 + rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
48794 + rphy->phy_cfg = &phy_cfgs[index];
48801 + if (!rphy->phy_cfg) {
48829 + if (rphy->phy_cfg->phy_tuning) {
48830 + ret = rphy->phy_cfg->phy_tuning(rphy);
48870 + if (++index >= rphy->phy_cfg->num_ports)
48979 + if (rphy->phy_cfg->reg == 0x760)
49058 + if (rphy->phy_cfg->reg == 0xe450) {
49085 + if (rphy->phy_cfg->reg == 0xe450) {
49145 + if (rphy->phy_cfg->reg == 0xfe8a0000) {
49200 + if (rphy->phy_cfg->reg == 0x0000) {
49229 + } else if (rphy->phy_cfg->reg == 0x4000) {
49255 + } else if (rphy->phy_cfg->reg == 0x8000) {
49272 + } else if (rphy->phy_cfg->reg == 0xc000) {
49306 + for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
49354 - if (++index >= rphy->phy_cfg->num_ports)
49386 + if (rphy->phy_cfg->phy_tuning)
49387 + ret = rphy->phy_cfg->phy_tuning(rphy);
49389 + for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
50604 + const struct phy_reg *phy_cfg;
50615 + phy_cfg = dp_pll_hbr2_cfg;
50621 + phy_cfg = dp_pll_hbr_cfg;
50628 + phy_cfg = dp_pll_rbr_cfg;
50644 + writel(phy_cfg[i].value, tcphy->base + phy_cfg[i].addr);
50780 + const struct phy_reg *phy_cfg;
50835 + phy_cfg = ssc_on ? dp_pll_rbr_ssc_cfg : dp_pll_rbr_cfg;
50843 + phy_cfg = ssc_on ? dp_pll_hbr_ssc_cfg : dp_pll_hbr_cfg;
50851 + phy_cfg = ssc_on ? dp_pll_hbr2_ssc_cfg : dp_pll_hbr2_cfg;
50864 + writel(phy_cfg[i].value, tcphy->base + phy_cfg[i].addr);