2  * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3  * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
45     return ((MPIDR_AFF_LEVEL(mpidr, 3) << 32) | /* 3: Serial number, 32: Register bit offset */  in MpidrToAffinity()
46             (MPIDR_AFF_LEVEL(mpidr, 2) << 16) | /* 2: Serial number, 16: Register bit offset */  in MpidrToAffinity()
47             (MPIDR_AFF_LEVEL(mpidr, 1) << 8)  | /* 1: Serial number, 8: Register bit offset */  in MpidrToAffinity()
53 STATIC UINT32 NextCpu(UINT32 cpu, UINT32 cpuMask)  in NextCpu()  argument
55     UINT32 next = cpu + 1;  in NextCpu()
73     UINT32 cpu = *base;  in GicTargetList()  local
74     UINT64 mpidr = CPU_MAP_GET(cpu);  in GicTargetList()
75     while (cpu < LOSCFG_KERNEL_CORE_NUM) {  in GicTargetList()
78         nextCpu = NextCpu(cpu, cpuMask);  in GicTargetList()
83         cpu = nextCpu;  in GicTargetList()
84         mpidr = CPU_MAP_GET(cpu);  in GicTargetList()
86             cpu--;  in GicTargetList()
92     *base = cpu;  in GicTargetList()
99     UINT32 cpu = 0;  in GicSgi()  local
102     while (cpuMask && (cpu < LOSCFG_KERNEL_CORE_NUM)) {  in GicSgi()
103         if (cpuMask & (1U << cpu)) {  in GicSgi()
104             cluster = CPU_MAP_GET(cpu) & ~0xffUL;  in GicSgi()
106             tList = GicTargetList(&cpu, cpuMask, cluster);  in GicSgi()
109 …       val = ((MPIDR_AFF_LEVEL(cluster, 3) << 48) | /* 3: Serial number, 48: Register bit offset */  in GicSgi()
110 …              (MPIDR_AFF_LEVEL(cluster, 2) << 32) | /* 2: Serial number, 32: Register bit offset */  in GicSgi()
111 …              (MPIDR_AFF_LEVEL(cluster, 1) << 16) | /* 1: Serial number, 16: Register bit offset */  in GicSgi()
112                    (irq << 24) | tList); /* 24: Register bit offset */  in GicSgi()
117         cpu++;  in GicSgi()
141         count -= 1;  in GicWaitForRwp()
159 STATIC INLINE VOID GicrSetWaker(UINT32 cpu)  in GicrSetWaker()  argument
161     GIC_REG_32(GICR_WAKER(cpu)) &= ~GICR_WAKER_PROCESSORSLEEP;  in GicrSetWaker()
164     while ((GIC_REG_32(GICR_WAKER(cpu)) & 0x4) == GICR_WAKER_CHILDRENASLEEP);  in GicrSetWaker()
167 STATIC INLINE VOID GicrSetGroup(UINT32 cpu)  in GicrSetGroup()  argument
171     GIC_REG_32(GICR_IGROUPR0(cpu)) = 0;  in GicrSetGroup()
172     GIC_REG_32(GICR_IGRPMOD0(cpu)) = 0;  in GicrSetGroup()
174     GIC_REG_32(GICR_IGROUPR0(cpu)) = 0xffffffff;  in GicrSetGroup()
180     UINT32 pos = irq >> 2; /* one irq have the 8-bit interrupt priority field */  in GicdSetPmr()
192     UINT32 cpu = ArchCurrCpuid();  in GicrSetPmr()  local
193     UINT32 pos = irq >> 2; /* one irq have the 8-bit interrupt priority field */  in GicrSetPmr()
194     UINT32 newPri = GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4);  in GicrSetPmr()
196     /* Clear priority offset bits and set new priority */  in GicrSetPmr()
200     GIC_REG_32(GICR_IPRIORITYR0(cpu) + pos * 4) = newPri;  in GicrSetPmr()
226      * The value of this field control show the 8-bit interrupt priority field  in GiccInitPercpu()
283         GIC_REG_32(GICD_ISENABLER(vector >> 5)) = mask; /* 5: Register bit offset */  in HalIrqUnmask()
294 …GIC_REG_32(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32); /* 5: Register bit offset, 32: Interr…  in HalIrqPending()
326     UINT32 cpu = ArchCurrCpuid();  in HalIrqInitPercpu()  local
329     GicrSetWaker(cpu);  in HalIrqInitPercpu()
330     GicrSetGroup(cpu);  in HalIrqInitPercpu()
331     GicWaitForRwp(GICR_CTLR(cpu));  in HalIrqInitPercpu()
334     GIC_REG_32(GICR_ICENABLER0(cpu)) = 0xffffffff;  in HalIrqInitPercpu()
335     GIC_REG_32(GICR_ICPENDR0(cpu)) = 0xffffffff;  in HalIrqInitPercpu()
337     GIC_REG_32(GICR_ISENABLER0(cpu)) = 0xffffffff;  in HalIrqInitPercpu()
343     GicWaitForRwp(GICR_CTLR(cpu));  in HalIrqInitPercpu()
394     /* set spi to boot cpu only. ARE must be enabled */  in HalIrqInit()
403     /* register inter-processor interrupt */  in HalIrqInit()