Lines Matching refs:pan

225 - pan/mdg: Pull out skip_internal boolean
226 - pan/mdg: Print optimized and scheduled shader
227 - pan/mdg: Model zero/sign extension for 8/16-bit loads
228 - pan/mdg: Handle 8/16-bit UBO loads
229 - pan/mdg: Clarify some ISA unknowns
230 - pan/mdg: Delete stray comment
231 - pan/mdg: Delete dedicated fdot2 lowering
232 - pan/mdg: Assert that we don't see unknown jumps
233 - pan/mdg: Remove todo we'll probably never get to
235 - pan/va: Parse units from the XML
236 - pan/va: Fix some units
237 - pan/va: Make subgroup 4-bits
238 - pan/va: Fix conservative branch handling
239 - pan/va: Identify LEA_TEX_IMM table
240 - pan/bi: Avoid \*FADD.v2f16 hazard in optimizer
241 - pan/bi: Avoid \*FADD.v2f16 hazard in scheduler
242 - pan/bi: Test avoiding \*FADD.v2f16 hazard in optimizer
243 - pan/bi: Test avoiding FADD.v2f16 hazards in scheduler
275 - pan/bi: Disambiguate IDVS variants in shader-db
276 - pan/bi: Lower swizzles on CSEL.i32/MUX.i32
277 - pan/bi: Lower swizzles on MUX.v2i16
278 - pan/bi: Constant fold swizzles on constants
279 - pan/bi: Optimize replication
280 - pan/bi: Handle trivial i2i32
281 - pan/bi: Handle vectorized u2f16/i2f16
282 - pan/bi: Switch to lower_bool_to_bitsize
283 - pan/bi: Revert "Fix load_const of 1-bit booleans"
284 - pan/bi: Promote MUX to CSEL in the scheduler
287 - pan/bi: Specialize IDVS in NIR
288 - pan/bi: Enable nir_opt_shrink_vectors
289 - pan/bi: Clarify requirement for barriers
290 - pan/bi: Cull DTSEL_IMM dests in post-RA DCE
291 - pan/bi: Do not cull post-RA staging writes
292 - pan/bi: Add bi_{start, exit}_block helpers
293 - pan/bi: Use bi_exit_block
294 - pan/bi: Clean up nits in liveness analysis
295 - pan/bi: Add scoreboard state to IR
296 - pan/bi: Print scoreboarding state
297 - pan/bi: Implement basic scoreboarding pass
298 - pan/bi: Add BIFROST_MESA_DEBUG=nosb option
299 - pan/mdg: Fix partial execution mode names
313 - pan/mdg: Fix overflow in intra-bundle interference
314 - pan/bi: Reorder pushed uniforms to avoid moves
320 - pan/bi: Add bi_before_nonempty_block helper
321 - pan/bi: Account for message preloading in shaderdb
322 - pan/bi: Support message preloading
323 - pan/bi: Unit test message preloading optimization
329 - pan/va: Remove incorrect TEX test cases
330 - pan/va: Add MUX.v2i16 and MUX.v4i8 opcodes
331 - pan/va: Allow forcing enums for 1-bit modifiers
332 - pan/va: Handle extended staging counts in assembler
333 - pan/va: Don't use staging index as a sideband
334 - pan/va: Fix definitions of TEX_SINGLE and TEX_FETCH
335 - pan/va: Handle sr_write_count in the disassembler
336 - pan/va: Add TEX_FETCH assembler case
352 - pan/bi: Mark NOP as having no destinations
353 - pan/bi: Use a progress loop for constant folding
354 - pan/bi: Allow CSE of preloaded registers
355 - pan/bi: Support standalone Valhall disassembly
356 - pan/bi: Wire Valhall disassembler into compiler
357 - pan/bi: Add BI_SUBGROUP_SUBGROUP16 option
358 - pan/bi: Trade off registers/threads on Valhall
359 - pan/bi: Adapt bi_lower_branch for Valhall
360 - pan/bi: Extract INSTRUCTION_CASE macro
361 - pan/va: Add missing copyright notice
362 - pan/va: Handle force_enum differing from name
363 - pan/va: Add modifiers required for gathers
364 - pan/va: Add TEX_DUAL instruction
365 - pan/va: Add TEX_GATHER instruction
366 - pan/va: Fix definitions of LD_VAR_BUF_IMM
367 - pan/va: Fix LEA_BUF_IMM definition
368 - pan/va: Remap "store segment" to "memory access"
369 - pan/va: Add memory access modifier to LOADs
370 - pan/bi: Model Valhall texture instructions
371 - pan/bi: Extend BLEND to take a register format
372 - pan/bi: Generalize I->table for Valhall
373 - pan/bi: Add LD_VAR_BUF_IMM.f16/f32 instructions
374 - pan/bi: Model LEA_BUF_IMM in the IR
375 - pan/bi: Model pos/vary segments in STORE instructions
376 - pan/bi: Model offset for LOAD/STORE
377 - pan/bi: Model LD_BUFFER instructions
378 - pan/bi: Add BRANCHZI instruction
379 - pan/bi: Extend LD_TILE with a register format
380 - pan/bi: Add arithmetic flag to RSHIFT ops
381 - pan/bi: Run CSE after lowering FAU
385 - pan/bi: Handle non-2D arrays
387 - pan/va: Fix typo in BLEND text
388 - pan/va: Add start property to source
389 - pan/va: Handle 64-bit sources in message instrs
390 - pan/va: Fix BLEND instruction
391 - pan/va: Rewrite FAU handling in dis/assembler
392 - pan/va: Handle uniforms from page 1
393 - pan/va: Rename imm_mode -> fau_page
394 - pan/va: Use 64-bit special FAU for pages 1 and 3
395 - pan/va: Remove immediate modes from XML/asm
396 - pan/va: Use boring names for FAU special pages 1/3
397 - pan/va: Use XML for special FAU page 0
398 - pan/decode: Handle blend arrays on Valhall
399 - pan/decode: Unify tiler job handling
405 - pan/va: Correct definition of ZS_EMIT
406 - pan/va: Model LEA_TEX_IMM more accurately
407 - pan/va: Add LEA_ATTR_IMM instruction
408 - pan/va: Add missing .auto32 register format
409 - pan/va: Align error messages in disassembler tests
410 - pan/va: Fix ST_CVT definitions
411 - pan/bi: Add helpers to get vertex/instance ID
412 - pan/bi: Use vertex/instance ID helpers
413 - pan/bi: Print Valhall-specific FAU indices
414 - pan/bi: Don't analyze helper reqs in !frag shaders
415 - pan/bi: Add Valhall-specific zero builder
416 - pan/bi: Model Valhall action on bi_instr
417 - pan/bi: Emit arch-specific code for bi_dontcare
418 - pan/bi: Use bi_dontcare for ZS_EMIT
432 - pan/va: Allow forcing staging flags to read-write
433 - pan/va: Allow omitting staging registers
434 - pan/va: Add atomic instructions
435 - pan/bi: Use consistent modifier lists in packing
436 - pan/bi: Gate late DCE/CSE on "optimize"
437 - pan/bi: Rename PATOM_C to ATOM
438 - pan/bi: Add ATOM_RETURN pseudo-instruction
439 - pan/bi: Model Valhall-style A(CMP)XCHG
440 - pan/bi: Allow branch_offset on BLEND
441 - pan/bi: Check return addresses in blend shaders
442 - pan/bi: Augment ST_TILE with register format
443 - pan/bi: Model LD_VAR_BUF instructions
444 - pan/bi: Rename I->action to I->flow
445 - pan/va: Add ST_TILE instruction
446 - pan/va: Add LD_VAR_BUF instructions
447 - pan/va: Add Bifrost-style LD_VAR instructions
448 - pan/va: Unify flow control
449 - pan/va: Permit encoding more flags
450 - pan/va: Build opcode info structures
451 - pan/va: Generate header containing enums
452 - pan/va: Add helpers for swapping bitwise sources
453 - pan/va: Add packing routines
454 - pan/va: Optimize add with imm to ADD_IMM
455 - pan/va: Add unit tests for ADD_IMM optimizations
456 - pan/va: Add FAU validation
457 - pan/va: Validate FAU before packing
458 - pan/va: Add constant lowering pass
459 - pan/va: Add instruction selection lowering pass
460 - pan/va: Lower branch offsets
461 - pan/va: Test instruction selection lowerings
462 - pan/va: Implement the cycle model
463 - pan/va: Add shader-db support
464 - pan/va: Add packing unit tests
465 - pan/va: Lower BLEND to call blend shaders
466 - pan/bi: Add .shadow modifier to TEX_GATHER
467 - pan/bi: Fix write_mask size
468 - pan/bi: Call Valhall backend passes on v9
469 - pan/bi: Use nir_tex_instr_has_implicit_derivative
470 - pan/bi: Split out load/store to thread storage
471 - pan/bi: Use ID accessors for LEA_ATTR
472 - pan/bi: Preload r60/r61 for MSAA + blend shader
477 - pan/bi: Model Valhall image loads
478 - pan/va: Add indirect LEA_{ATTR, TEX}
479 - pan/va: Pack LEA_TEX_IMM
480 - pan/va: Model image load instructions
481 - pan/va: Don't truncate slots
482 - pan/va: Add flow control lowering pass
483 - pan/va: Allow small constants in register pairs
485 - pan/bi: Mark LD_TILE as w=format
486 - pan/bi: Fix spilling on Valhall
487 - pan/bi: Waits before tilebuffer access on Valhall
488 - pan/bi: Specialize BLEND emit for Valhall
489 - pan/bi: Emit Valhall texture instructions
490 - pan/bi: Handle Valhall texturing in helper analysis
491 - pan/bi: Track whether the malloc IDVS flow is used
492 - pan/bi: Emit Valhall-style varying loads
493 - pan/bi: Emit Valhall-style varying stores
494 - pan/bi: Set table for Valhall LD_ATTR
495 - pan/bi: Force psiz to mediump
496 - pan/bi: Lower gl_PointSize to FP16 on Valhall
497 - pan/bi: Make psiz variants
498 - pan/bi: Generate LD_BUFFER on Valhall
499 - pan/bi: Avoid masked writes for now
500 - pan/bi: Report whether workgroups can be merged
501 - pan/bi: Don't lower vertex_id for malloc IDVS
502 - pan/bi: Consider flow control in DCE
503 - pan/va: Add LD_TILE.v3.f16 packing test
530 - pan/bi: Don't use funny round modes in tests
531 - pan/bi: Mark some opcodes as default round-to-zero
532 - pan/bi: Use should_skip in bi_builder generation
533 - pan/bi: Imply round mode most of the time
581 - pan/midg: Add intra-bundle interferences
582 - pan/midg: Remove spurious printf() in print_vector_constants()
583 - pan/midg: Prefix scalar immediates with '#' instead of '<'
584 - pan/midg: Fix swizzling on 8-bit sources
585 - pan/midg: Fix 64-bit swizzle printer
586 - pan/midg: Fix the upper/lower limit on 8bit vectors
587 - pan/midg: Fix swizzle packing on 64bit instructions with src-expansion + dst-shrinking
588 - pan/midg: Add a pass to lower non-logbase2 global/shared loads
589 - pan/midg: Support 8/16 bit load/store
1543 - pan/mdg: Use util_logbase2 instead of C99 log2
1547 - pan/bi: Add interference between destinations
1548 - pan/bi: Check dependencies of both destinations of instructions
1551 - pan/bi: Make disassembler build reproducibly
1552 - pan/bi: Add documentation for bifrost_nir_lower_store_component
1555 - pan/bi: Skip psuedo sources in ISA.xml
1556 - pan/bi: Don't assign slots for the blend second source
1567 - pan/bi: Use texture index instead of sampler for message preloading
1569 - pan/mdg: Keep min_bound at 16 when alignment requires it
1570 - pan/mdg: Use MAX2 to set min_alignment
1571 - pan/mdg: Fix mask usage when filling before a spill
1572 - pan/mdg: Return the instruction from mir_insert_instruction_*_scheduled
1573 - pan/mdg: Fix multiple spilt writes in the same bundle