431 static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info,  in ac_sqtt_fill_asic_info()  argument
434    bool has_wave32 = rad_info->gfx_level >= GFX10;  in ac_sqtt_fill_asic_info()
447    if (rad_info->gfx_level < GFX9)  in ac_sqtt_fill_asic_info()
451    if (rad_info->gfx_level >= GFX9)  in ac_sqtt_fill_asic_info()
454    chunk->trace_shader_core_clock = rad_info->max_gpu_freq_mhz * 1000000ull;  in ac_sqtt_fill_asic_info()
455    chunk->trace_memory_clock = rad_info->memory_freq_mhz * 1000000ull;  in ac_sqtt_fill_asic_info()
464    chunk->device_id = rad_info->pci_id;  in ac_sqtt_fill_asic_info()
465    chunk->device_revision_id = rad_info->pci_rev_id;  in ac_sqtt_fill_asic_info()
466    chunk->vgprs_per_simd = rad_info->num_physical_wave64_vgprs_per_simd * (has_wave32 ? 2 : 1);  in ac_sqtt_fill_asic_info()
467    chunk->sgprs_per_simd = rad_info->num_physical_sgprs_per_simd;  in ac_sqtt_fill_asic_info()
468    chunk->shader_engines = rad_info->max_se;  in ac_sqtt_fill_asic_info()
469    chunk->compute_unit_per_shader_engine = rad_info->min_good_cu_per_sa * rad_info->max_sa_per_se;  in ac_sqtt_fill_asic_info()
470    chunk->simd_per_compute_unit = rad_info->num_simd_per_compute_unit;  in ac_sqtt_fill_asic_info()
471    chunk->wavefronts_per_simd = rad_info->max_wave64_per_simd;  in ac_sqtt_fill_asic_info()
473    chunk->minimum_vgpr_alloc = rad_info->min_wave64_vgpr_alloc;  in ac_sqtt_fill_asic_info()
474    chunk->vgpr_alloc_granularity = rad_info->wave64_vgpr_alloc_granularity * (has_wave32 ? 2 : 1);  in ac_sqtt_fill_asic_info()
475    chunk->minimum_sgpr_alloc = rad_info->min_sgpr_alloc;  in ac_sqtt_fill_asic_info()
476    chunk->sgpr_alloc_granularity = rad_info->sgpr_alloc_granularity;  in ac_sqtt_fill_asic_info()
480       rad_info->has_dedicated_vram ? SQTT_GPU_TYPE_DISCRETE : SQTT_GPU_TYPE_INTEGRATED;  in ac_sqtt_fill_asic_info()
481    chunk->gfxip_level = ac_gfx_level_to_sqtt_gfxip_level(rad_info->gfx_level);  in ac_sqtt_fill_asic_info()
489    chunk->vram_bus_width = rad_info->memory_bus_width;  in ac_sqtt_fill_asic_info()
490    chunk->vram_size = (uint64_t)rad_info->vram_size_kb * 1024;  in ac_sqtt_fill_asic_info()
491    chunk->l2_cache_size = rad_info->l2_cache_size;  in ac_sqtt_fill_asic_info()
492    chunk->l1_cache_size = rad_info->l1_cache_size;  in ac_sqtt_fill_asic_info()
493    chunk->lds_size = rad_info->lds_size_per_workgroup;  in ac_sqtt_fill_asic_info()
494    if (rad_info->gfx_level >= GFX10) {  in ac_sqtt_fill_asic_info()
499    strncpy(chunk->gpu_name, rad_info->name, SQTT_GPU_NAME_MAX_SIZE - 1);  in ac_sqtt_fill_asic_info()
503    chunk->prims_per_clock = rad_info->max_se;  in ac_sqtt_fill_asic_info()
504    if (rad_info->gfx_level == GFX10)  in ac_sqtt_fill_asic_info()
508    chunk->gpu_timestamp_frequency = rad_info->clock_crystal_freq * 1000;  in ac_sqtt_fill_asic_info()
509    chunk->max_shader_core_clock = rad_info->max_gpu_freq_mhz * 1000000;  in ac_sqtt_fill_asic_info()
510    chunk->max_memory_clock = rad_info->memory_freq_mhz * 1000000;  in ac_sqtt_fill_asic_info()
511    chunk->memory_ops_per_clock = ac_memory_ops_per_clock(rad_info->vram_type);  in ac_sqtt_fill_asic_info()
512    chunk->memory_chip_type = ac_vram_type_to_sqtt_memory_type(rad_info->vram_type);  in ac_sqtt_fill_asic_info()
513    chunk->lds_granularity = rad_info->lds_encode_granularity;  in ac_sqtt_fill_asic_info()
517          chunk->cu_mask[se][sa] = rad_info->cu_mask[se][sa];  in ac_sqtt_fill_asic_info()
1006 static void ac_sqtt_dump_data(struct radeon_info *rad_info,  in ac_sqtt_dump_data()  argument
1038    ac_sqtt_fill_asic_info(rad_info, &asic_info);  in ac_sqtt_dump_data()
1053       uint32_t flags = ac_gfx_level_to_elf_gfxip_level(rad_info->gfx_level);  in ac_sqtt_dump_data()
1173          ac_sqtt_fill_sqtt_desc(rad_info, &desc, i, se->shader_engine, se->compute_unit);  in ac_sqtt_dump_data()