48    radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));  in radeon_set_config_reg_seq()
49    radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);  in radeon_set_config_reg_seq()
56    radeon_emit(cs, value);  in radeon_set_config_reg()
65    radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));  in radeon_set_context_reg_seq()
66    radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);  in radeon_set_context_reg_seq()
73    radeon_emit(cs, value);  in radeon_set_context_reg()
81    radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));  in radeon_set_context_reg_idx()
82    radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_context_reg_idx()
83    radeon_emit(cs, value);  in radeon_set_context_reg_idx()
91    radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));  in radeon_set_context_reg_rmw()
92    radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);  in radeon_set_context_reg_rmw()
93    radeon_emit(cs, mask);  in radeon_set_context_reg_rmw()
94    radeon_emit(cs, value);  in radeon_set_context_reg_rmw()
103    radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));  in radeon_set_sh_reg_seq()
104    radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);  in radeon_set_sh_reg_seq()
111    radeon_emit(cs, value);  in radeon_set_sh_reg()
126    radeon_emit(cs, PKT3(opcode, 1, 0));  in radeon_set_sh_reg_idx()
127    radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_sh_reg_idx()
128    radeon_emit(cs, value);  in radeon_set_sh_reg_idx()
137    radeon_emit(cs, PKT3(PKT3_SET_SH_REG_INDEX, 1, 0));  in gfx10_set_sh_reg_idx3()
138    radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (3 << 28));  in gfx10_set_sh_reg_idx3()
139    radeon_emit(cs, value);  in gfx10_set_sh_reg_idx3()
148    radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));  in radeon_set_uconfig_reg_seq()
149    radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_uconfig_reg_seq()
158    radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 1));  in radeon_set_uconfig_reg_seq_perfctr()
159    radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_uconfig_reg_seq_perfctr()
166    radeon_emit(cs, value);  in radeon_set_uconfig_reg()
182    radeon_emit(cs, PKT3(opcode, 1, 0));  in radeon_set_uconfig_reg_idx()
183    radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_uconfig_reg_idx()
184    radeon_emit(cs, value);  in radeon_set_uconfig_reg_idx()
202    radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0) | PKT3_RESET_FILTER_CAM(filter_cam_workaround));  in radeon_set_perfctr_reg()
203    radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_perfctr_reg()
204    radeon_emit(cs, value);  in radeon_set_perfctr_reg()
213    radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));  in radeon_set_privileged_config_reg()
214    radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_PERF));  in radeon_set_privileged_config_reg()
215    radeon_emit(cs, value);  in radeon_set_privileged_config_reg()
216    radeon_emit(cs, 0); /* unused */  in radeon_set_privileged_config_reg()
217    radeon_emit(cs, reg >> 2);  in radeon_set_privileged_config_reg()
218    radeon_emit(cs, 0); /* unused */  in radeon_set_privileged_config_reg()