36    radeon_emit(cs, shaders & 0x7f);  in radv_perfcounter_emit_shaders()
37    radeon_emit(cs, 0xffffffff);  in radv_perfcounter_emit_shaders()
45       radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in radv_emit_windowed_counters()
46       radeon_emit(cs, EVENT_TYPE(enable ? V_028A90_PERFCOUNTER_START : V_028A90_PERFCOUNTER_STOP) |  in radv_emit_windowed_counters()
508       radeon_emit(cs, 0);  in radv_emit_select()
526       radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));  in radv_pc_emit_block_instance_read()
527       radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) | COPY_DATA_DST_SEL(COPY_DATA_TC_L2) |  in radv_pc_emit_block_instance_read()
529       radeon_emit(cs, reg >> 2);  in radv_pc_emit_block_instance_read()
530       radeon_emit(cs, 0); /* unused */  in radv_pc_emit_block_instance_read()
531       radeon_emit(cs, va);  in radv_pc_emit_block_instance_read()
532       radeon_emit(cs, va >> 32);  in radv_pc_emit_block_instance_read()
562    radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in radv_pc_wait_idle()
563    radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));  in radv_pc_wait_idle()
565    radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));  in radv_pc_wait_idle()
566    radeon_emit(cs, 0);          /* CP_COHER_CNTL */  in radv_pc_wait_idle()
567    radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */  in radv_pc_wait_idle()
568    radeon_emit(cs, 0xffffff);   /* CP_COHER_SIZE_HI */  in radv_pc_wait_idle()
569    radeon_emit(cs, 0);          /* CP_COHER_BASE */  in radv_pc_wait_idle()
570    radeon_emit(cs, 0);          /* CP_COHER_BASE_HI */  in radv_pc_wait_idle()
571    radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */  in radv_pc_wait_idle()
572    radeon_emit(cs, 0);          /* GCR_CNTL */  in radv_pc_wait_idle()
574    radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));  in radv_pc_wait_idle()
575    radeon_emit(cs, 0);  in radv_pc_wait_idle()
585    radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in radv_pc_stop_and_sample()
586    radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0));  in radv_pc_stop_and_sample()
602       radeon_emit(cs, PKT3(PKT3_COND_EXEC, 3, 0));  in radv_pc_stop_and_sample()
603       radeon_emit(cs, pred_va);  in radv_pc_stop_and_sample()
604       radeon_emit(cs, pred_va >> 32);  in radv_pc_stop_and_sample()
605       radeon_emit(cs, 0); /* Cache policy */  in radv_pc_stop_and_sample()
608       radeon_emit(cs, 0);  in radv_pc_stop_and_sample()
632          radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));  in radv_pc_stop_and_sample()
633          radeon_emit(cs,  in radv_pc_stop_and_sample()
635          radeon_emit(cs, signal_va);  in radv_pc_stop_and_sample()
636          radeon_emit(cs, signal_va >> 32);  in radv_pc_stop_and_sample()
637          radeon_emit(cs, 1); /* value */  in radv_pc_stop_and_sample()
666    radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));  in radv_pc_begin_query()
667    radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME));  in radv_pc_begin_query()
668    radeon_emit(cs, perf_ctr_va);  in radv_pc_begin_query()
669    radeon_emit(cs, perf_ctr_va >> 32);  in radv_pc_begin_query()
670    radeon_emit(cs, 0); /* value */  in radv_pc_begin_query()
685       radeon_emit(cs, PKT3(PKT3_COND_EXEC, 3, 0));  in radv_pc_begin_query()
686       radeon_emit(cs, pred_va);  in radv_pc_begin_query()
687       radeon_emit(cs, pred_va >> 32);  in radv_pc_begin_query()
688       radeon_emit(cs, 0); /* Cache policy */  in radv_pc_begin_query()
691       radeon_emit(cs, 0);  in radv_pc_begin_query()