800 struct radv_device {  struct
801    struct vk_device vk;
803    struct radv_instance *instance;
804    struct radeon_winsys *ws;
806    struct radeon_winsys_ctx *hw_ctx[RADV_NUM_HW_CTX];
807    struct radv_meta_state meta_state;
809    struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
810    int queue_count[RADV_MAX_QUEUE_FAMILIES];
812    bool pbb_allowed;
813    uint32_t scratch_waves;
814    uint32_t dispatch_initiator;
815    uint32_t dispatch_initiator_task;
820    float sample_locations_1x[1][2];
821    float sample_locations_2x[2][2];
822    float sample_locations_4x[4][2];
823    float sample_locations_8x[8][2];
826    uint32_t gfx_init_size_dw;
827    struct radeon_winsys_bo *gfx_init;
829    struct radeon_winsys_bo *trace_bo;
830    uint32_t *trace_id_ptr;
833    bool keep_shader_info;
835    struct radv_physical_device *physical_device;
838    struct radv_pipeline_cache *mem_cache;
844    uint32_t image_mrt_offset_counter;
845    uint32_t fmask_mrt_offset_counter;
847    struct list_head shader_arenas;
848    unsigned shader_arena_shift;
849    uint8_t shader_free_list_mask;
850    struct list_head shader_free_lists[RADV_SHADER_ALLOC_NUM_FREE_LISTS];
851    struct list_head shader_block_obj_pool;
852    mtx_t shader_arena_mutex;
855    uint64_t dmesg_timestamp;
858    bool robust_buffer_access;
882    struct radv_device_border_color_data border_color_data;  argument
908       struct radv_device_memory *mem;  argument
909    } vrs;
911    struct u_rwlock vs_prologs_lock;
912    struct hash_table *vs_prologs;
915    struct radv_queue *private_sdma_queue;
917    struct radv_shader_part *simple_vs_prologs[MAX_VERTEX_ATTRIBS];
918    struct radv_shader_part *instance_rate_vs_prologs[816];
920    simple_mtx_t trace_mtx;
944 bool radv_device_acquire_performance_counters(struct radv_device *device);  argument