Lines Matching refs:rad_info
85 .lower_ffma16 = split_fma || device->rad_info.gfx_level < GFX9, in get_nir_options_for_stage()
86 .lower_ffma32 = split_fma || device->rad_info.gfx_level < GFX10_3, in get_nir_options_for_stage()
91 .lower_iadd_sat = device->rad_info.gfx_level <= GFX8, in get_nir_options_for_stage()
96 .has_sdot_4x8 = device->rad_info.has_accelerated_dot_product, in get_nir_options_for_stage()
97 .has_udot_4x8 = device->rad_info.has_accelerated_dot_product, in get_nir_options_for_stage()
98 .has_dot_2x16 = device->rad_info.has_accelerated_dot_product, in get_nir_options_for_stage()
729 .float16 = device->physical_device->rad_info.has_packed_math_16bit, in radv_shader_spirv_to_nir()
774 .fragment_shading_rate = device->physical_device->rad_info.gfx_level >= GFX10_3, in radv_shader_spirv_to_nir()
879 if (device->physical_device->rad_info.gfx_level == GFX6) { in radv_shader_spirv_to_nir()
960 bool gfx7minus = device->physical_device->rad_info.gfx_level <= GFX7; in radv_shader_spirv_to_nir()
1048 device->physical_device->rad_info.gfx_level); in radv_shader_spirv_to_nir()
1056 if (ac_nir_lower_indirect_derefs(nir, device->physical_device->rad_info.gfx_level) && in radv_shader_spirv_to_nir()
1172 device->physical_device->rad_info.gfx_level, in radv_lower_io_to_mem()
1179 device->physical_device->rad_info.gfx_level, in radv_lower_io_to_mem()
1191 device->physical_device->rad_info.gfx_level, in radv_lower_io_to_mem()
1198 device->physical_device->rad_info.gfx_level, false); in radv_lower_io_to_mem()
1237 unsigned max_render_backends = pdevice->rad_info.max_render_backends; in radv_consider_culling()
1238 unsigned max_se = pdevice->rad_info.max_se; in radv_consider_culling()
1336 device->physical_device->rad_info.family, in radv_lower_ngg()
1482 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ? 0 in radv_alloc_shader_memory()
1628 enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level; in radv_should_use_wgp_mode()
1664 assert((pdevice->rad_info.gfx_level >= GFX10 && num_shared_vgprs % 8 == 0) || in radv_postprocess_config()
1665 (pdevice->rad_info.gfx_level < GFX10 && num_shared_vgprs == 0)); in radv_postprocess_config()
1694 if (pdevice->rad_info.gfx_level >= GFX10) { in radv_postprocess_config()
1706 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1709 assert(pdevice->rad_info.gfx_level <= GFX8); in radv_postprocess_config()
1717 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1723 if (pdevice->rad_info.gfx_level >= GFX9) { in radv_postprocess_config()
1728 if (pdevice->rad_info.gfx_level >= GFX10) { in radv_postprocess_config()
1731 } else if (pdevice->rad_info.gfx_level <= GFX10_3) { in radv_postprocess_config()
1745 S_00B428_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10) | S_00B428_WGP_MODE(wgp_mode); in radv_postprocess_config()
1750 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1752 assert(pdevice->rad_info.gfx_level <= GFX8); in radv_postprocess_config()
1759 assert(pdevice->rad_info.gfx_level <= GFX8); in radv_postprocess_config()
1767 if (info->vs.needs_instance_id && pdevice->rad_info.gfx_level >= GFX10) { in radv_postprocess_config()
1777 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1788 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1793 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1800 S_00B848_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10) | S_00B848_WGP_MODE(wgp_mode); in radv_postprocess_config()
1817 if (pdevice->rad_info.gfx_level >= GFX10 && info->is_ngg && in radv_postprocess_config()
1871 } else if (pdevice->rad_info.gfx_level >= GFX9 && stage == MESA_SHADER_GEOMETRY) { in radv_postprocess_config()
1878 es_vgpr_comp_cnt = pdevice->rad_info.gfx_level >= GFX10 ? 3 : 1; in radv_postprocess_config()
1905 } else if (pdevice->rad_info.gfx_level >= GFX9 && stage == MESA_SHADER_TESS_CTRL) { in radv_postprocess_config()
1922 if (device->physical_device->rad_info.gfx_level >= GFX9 && in radv_open_rtld_binary()
1944 .info = &device->physical_device->rad_info, in radv_open_rtld_binary()
2026 if (!ac_rtld_read_config(&device->physical_device->rad_info, &rtld_binary, &config)) { in radv_shader_create()
2033 unsigned encode_granularity = device->physical_device->rad_info.lds_encode_granularity; in radv_shader_create()
2202 enum radeon_family chip_family = device->physical_device->rad_info.family;
2211 options->gfx_level = device->physical_device->rad_info.gfx_level;
2212 …options->has_3d_cube_border_color_mipmap = device->physical_device->rad_info.has_3d_cube_border_co…
2219 options->address32_hi = device->physical_device->rad_info.address32_hi;
2220 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
2327 radv_declare_shader_args(device->physical_device->rad_info.gfx_level, &key, &info,
2429 options.family = device->physical_device->rad_info.family;
2430 options.gfx_level = device->physical_device->rad_info.gfx_level;
2431 …options.has_3d_cube_border_color_mipmap = device->physical_device->rad_info.has_3d_cube_border_col…
2432 options.address32_hi = device->physical_device->rad_info.address32_hi;
2492 options.family = device->physical_device->rad_info.family;
2493 options.gfx_level = device->physical_device->rad_info.gfx_level;
2494 options.address32_hi = device->physical_device->rad_info.address32_hi;
2504 radv_declare_ps_epilog_args(device->physical_device->rad_info.gfx_level, key, &args);
2645 struct radeon_info *info = &device->physical_device->rad_info;