Lines Matching refs:base_miplevel

166    uint32_t width = u_minify(layout->width0, args->base_miplevel);  in fdl6_view_init()
167    uint32_t height = u_minify(layout->height0, args->base_miplevel);  in fdl6_view_init()
192       storage_depth = u_minify(layout->depth0, args->base_miplevel);  in fdl6_view_init()
204       fdl_surface_offset(layout, args->base_miplevel, args->base_array_layer);  in fdl6_view_init()
206       fdl_ubwc_offset(layout, args->base_miplevel, args->base_array_layer);  in fdl6_view_init()
208    uint32_t pitch = fdl_pitch(layout, args->base_miplevel);  in fdl6_view_init()
209    uint32_t ubwc_pitch = fdl_ubwc_pitch(layout, args->base_miplevel);  in fdl6_view_init()
210    uint32_t layer_size = fdl_layer_stride(layout, args->base_miplevel);  in fdl6_view_init()
216    enum a6xx_tile_mode tile_mode = fdl_tile_mode(layout, args->base_miplevel);  in fdl6_view_init()
218    bool ubwc_enabled = fdl_ubwc_enabled(layout, args->base_miplevel);  in fdl6_view_init()
260    view->descriptor[6] = A6XX_TEX_CONST_6_MIN_LOD_CLAMP(args->min_lod_clamp - args->base_miplevel);  in fdl6_view_init()
282                fdl_ubwc_offset(layouts[i], args->base_miplevel, args->base_array_layer);  in fdl6_view_init()
287                fdl_surface_offset(layouts[i], args->base_miplevel, args->base_array_layer);  in fdl6_view_init()
294          A6XX_TEX_CONST_6_PLANE_PITCH(fdl_pitch(layouts[1], args->base_miplevel));  in fdl6_view_init()
355          A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(args->base_miplevel);  in fdl6_view_init()
401       tile_mode == TILE6_LINEAR && args->base_miplevel != layout->mip_levels - 1;  in fdl6_view_init()