Lines Matching +full:a630 +full:- +full:traces
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
9 <!-- these might be same as a5xx -->
25 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
46 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
107 <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
108 <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
109 <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
111 <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
115 <!-- Note: tiling/UBWC for these may be different from equivalent formats
117 -->
166 <!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
169 <!-- Not a hw enum, used internally in driver -->
174 <!-- probably same as a5xx -->
877 <!--
893 -->
906 <doc>Allow early z-test and early-lrz (if applicable)</doc>
908 <doc>Disable early z-test and early-lrz test (if applicable)</doc>
911 A special mode that allows early-lrz test but disables
912 early-z test. Which might sound a bit funny, since
913 lrz-test happens before z-test. But as long as a couple
914 conditions are maintained this allows using lrz-test in
917 1) Disable lrz-write in cases where it is uncertain during
919 shader has-kill, writes-z, or alpha/stencil test is
920 enabled. (For correctness, lrz-write must be disabled
922 z-prepass works.
924 2) Disable lrz-write and test if a depth-test direction
929 lrz-test. But geometry which may be (or contributes to
930 blend) will pass the lrz-test.
932 This allows us to keep early-lrz-test in cases where the frag
933 shader does not write-z (ie. we know the z-value before FS)
934 and does not have side-effects (image/ssbo writes, etc), but
936 enough case that it is useful to keep early-lrz test against
995 <!-- all the threshold values seem to be in units of quad-dwords: -->
1017 /* ROQ sizes are twice as big on a640/a680 than on a630 */
1024 <!-- total ROQ size: -->
1063 <!-- SDS == CP_SET_DRAW_STATE: -->
1066 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
1069 <!--
1072 -->
1076 <!--
1079 -->
1159 <!---
1163 -->
1165 <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
1167 <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
1169 <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
1171 <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
1173 <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
1175 <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
1177 <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
1179 <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
1181 <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
1183 <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
1471 <!--
1474 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1479 LIMIT is set to PITCH - 64, to make room for a bit of overflow
1480 -->
1515 <!-- always 0x03200000 ? -->
1518 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
1528 <!-- set with depthClampEnable, not clear what it does -->
1530 <!-- controls near z clip behavior (set for vulkan) -->
1532 <!-- guess based on a3xx and meaning of bits 8 and 9
1533 if the guess is right then this is related to point sprite clipping -->
1549 <!-- see also RB_RENDER_CONTROL0 -->
1562 <!-- 0x8006-0x800f invalid -->
1585 <!--
1588 -->
1598 <!-- 0x8093 invalid -->
1605 <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1629 <!-- 0x809e/0x809f invalid -->
1643 flushed before the data or vice-versa, leading to
1648 non-coherent blending.
1663 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
1669 <!-- I'm guessing this is the same as a3xx -->
1683 <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
1737 <!-- 0x80a7-0x80ae invalid -->
1755 <!-- 0x80f2-0x80ff invalid -->
1771 - 0.0 if GREATER
1772 - 1.0 if LESS
1775 <!-- set when depth-test + depth-write enabled -->
1780 If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into
1786 If DIR_WRITE is not enabled - there is no write to direction buffer.
1806 <!-- TODO: fix the shr fields -->
1811 <!--
1834 // fast-clear buffer is 1bit/block:
1840 -->
1842 <!-- 0x8108 invalid -->
1846 <!--
1852 the value stored in the LRZ buffer, if not - LRZ is disabled.
1853 -->
1860 <!-- 0x810b-0x810f invalid -->
1864 <!-- 0x8111-0x83ff invalid -->
1883 <!-- required when blitting D24S8/D24X8 -->
1885 <!-- some sort of channel mask, disabled channels are set to zero ? -->
1892 <!-- note: the low 8 bits for src coords are valid, probably fixed point
1895 -->
1907 <!-- 0x840c-0x85ff invalid -->
1909 <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
1919 <!-- note 0x8620-0x87ff are not all invalid
1921 -->
1923 <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
1936 <!-- set during binning pass: -->
1943 <!-- bit seems to be set whenever depth buffer enabled: -->
1945 <!-- bitmask of MRTs using UBWC flag buffer: -->
1961 <!-- 0x8807-0x8808 invalid -->
1962 <!--
1965 -->
1967 <!-- see also GRAS_CNTL -->
1978 <!-- enable bits for various FS sysvalue regs: -->
2019 <!-- Same as SP_SRGB_CNTL -->
2034 <!-- 0x8812-0x8817 invalid -->
2035 <!-- always 0x0 ? -->
2037 <!-- 0x8819-0x881e all 32 bits -->
2044 <!-- 0x881f invalid -->
2067 <!--
2070 -->
2073 <!--
2078 -->
2079 <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
2095 <!-- per-mrt enable bit -->
2103 <!-- 0x8866-0x886f invalid -->
2120 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2132 <!-- 0x887a-0x887f invalid -->
2136 <!--
2141 -->
2172 <!-- 0x888a-0x888f invalid -->
2178 <!-- 0x8892-0x8897 invalid -->
2182 <!-- 0x8899-0x88bf invalid -->
2183 <!-- clamps depth value for depth test/write -->
2186 <!-- 0x88c2-0x88cf invalid-->
2193 <!-- weird to duplicate other regs from same block?? -->
2203 <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2214 <!-- array-pitch is size of layer -->
2227 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2229 …bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color resto…
2230 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2231 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
2232 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2235 1 - depth
2236 2 - stencil
2237 3 - depth+stencil
2242 <!-- set when this is the last resolve on a650+ -->
2244 <!--
2249 -->
2252 <!-- 0x88e4-0x88ef invalid -->
2253 <!-- always 0x0 ? -->
2255 <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
2262 <!-- 0x88f5-0x88ff invalid -->
2266 <!-- TODO: actually part of array pitch -->
2277 <!-- 0x891b-0x8926 invalid -->
2279 <!-- 0x8929-0x89ff invalid -->
2281 <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
2283 <!--
2285 blob writing non-zero:
2286 -->
2301 <!-- the rest is only for src -->
2314 <!-- 0x8c02-0x8c16 invalid -->
2315 <!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
2319 <!-- this is a guess but seems likely (for NV12/IYUV): -->
2326 <!-- this is a guess but seems likely (for NV12 with UBWC): -->
2330 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
2331 <!-- unlike a5xx, these are per channel values rather than packed -->
2336 <!-- 0x8c34-0x8dff invalid -->
2338 <!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
2340 <!-- 0x8e00-0x8e03 invalid -->
2341 <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/> <!-- TODO: valid mask 0xfffffeff -->
2343 <!-- 0x8e06 invalid -->
2345 <!-- GMEM offset of CCU color cache
2350 -->
2352 <!-- GMEM offset of CCU depth cache -->
2354 <bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
2355 <!-- concurrent resolves are apparently a 2-bit enum on a650+ -->
2357 <!--TODO: valid mask 0xfffffc1f -->
2362 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
2368 <!-- 0x8e09-0x8e0f invalid -->
2371 <!-- 0x8e1d-0x8e1f invalid -->
2372 <!-- 0x8e20-0x8e25 more perfcntr sel? -->
2373 <!-- 0x8e26-0x8e27 invalid -->
2375 <!-- 0x8e29-0x8e2b invalid -->
2379 <!-- 0x8e3e-0x8e4f invalid -->
2380 <!-- GMEM save/restore for preemption: -->
2382 <!-- address for GMEM save/restore? -->
2384 <!-- 0x8e53-0x8e7f invalid -->
2385 <!-- 0x8e80-0x8e83 are valid -->
2386 <!-- 0x8e84-0x90ff invalid -->
2388 <!-- 0x9000-0x90ff invalid -->
2396 <!-- there can be up to 8 total clip/cull distance outputs,
2399 -->
2417 <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
2424 <!-- 0x9109-0x91ff invalid -->
2432 <!-- always 0x0 -->
2437 <!-- one bit per varying component: -->
2442 <!--
2462 This field is auto-incremented when VPC_SO_PROG is
2464 -->
2466 <!-- clear all A_EN and B_EN bits for all DWORD's -->
2469 <!-- special register, write multiple times to load SO program (not readable) -->
2492 <!-- 0x9237-0x92ff invalid -->
2493 <!-- always 0x0 ? -->
2499 plus # of transform-feedback (streamout) varyings if using the
2508 number of views minus one when multi-position
2519 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
2527 strictly required for multi-position output,
2529 views at once, but it can be used when multi-pos
2537 <!--
2539 -->
2549 <!-- 0x9307-0x95ff invalid -->
2551 <!-- TODO: 0x9600-0x97ff range -->
2552 <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
2554 <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? -->
2557 <!-- 0x960a-0x9623 invalid -->
2558 <!-- TODO: regs from 0x9624-0x963a -->
2559 <!-- 0x963b-0x97ff invalid -->
2563 <!-- always 0x0 ? -->
2590 <!-- probably a mirror of VFD_CONTROL_6 -->
2593 <!-- New in a6xx gen3+ -->
2601 <!-- 0x980b-0x983f invalid -->
2603 <!-- 0x9840 - 0x9842 are not readable -->
2613 <!-- I think only the low bit is actually used? -->
2618 <!--
2622 -->
2625 <!-- 0x9843-0x997f invalid -->
2632 <!-- which stream to send to GRAS -->
2634 <!-- discard primitives before rasterization -->
2638 <!-- 0x9982-0x9aff invalid -->
2642 <!-- maybe? b1 seems always set, so just assume it is for now: -->
2651 plus # of transform-feedback (streamout) varyings if using the
2658 <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
2665 <!-- since HS can't output anything, only PRIMITIVE_ID is valid -->
2673 <!-- TODO: first 16 bits are valid so something is wrong or missing here -->
2683 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
2692 Multi-position output lets the last geometry
2703 <!-- mask of enabled views, doesn't exist on A630 -->
2705 <!-- 0x9b09-0x9bff invalid -->
2707 <!-- special register (but note first 8 bits can be written/read) -->
2711 <!-- 0x9c01-0x9dff invalid -->
2712 <!-- TODO: 0x9e00-0xa000 range incomplete -->
2729 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2745 <!-- always 0x0 -->
2756 <!-- only used for VS in non-multi-position-output case -->
2764 patch within the HS->DS buffers. When a draw is
2786 <!--
2789 be passed through via fixed-function logic.
2790 -->
2800 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
2802 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
2815 <!-- IDX and byte OFFSET into VFD_FETCH -->
2838 <!--
2841 -->
2848 <!-- if set to SINGLE, only use 1 concurrent wave on each SP -->
2850 <!--
2853 - used (half): 0-15 68-179 (cnt=128, max=179)
2854 …- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 12…
2858 - used (merged): 0-191 (cnt=192, max=191)
2863 -->
2866 <!-- could it be a low bit of branchstack? -->
2868 <!-- seems to be nesting level for flow control:.. -->
2873 <!--
2876 -->
2883 <!--
2886 -->
2893 <!-- # of VS outputs including pos/psize -->
2895 <!-- FLAGS_REGID only for GS -->
2900 <!--
2903 -->
2905 <!--
2906 Creates a separate preamble-only thread?
2909 - Only shared, a1, and consts regs could be used
2911 - No cat5/cat6, only stc/ldc variants are working;
2912 - Values writen to shared regs are not accessible by the rest
2914 - Instructions before shps are also considered to be a part of
2919 -->
2922 <!-- bitmask of true/false conditions for VS brac.N instructions,
2923 bit N corresponds to brac.N -->
2925 <!-- # of VS outputs including pos/psize -->
2935 <!--
2941 -->
2975 - stp/ldp offset
2976 - fiber id
2977 - wavefront id (a swizzled version of what "getwid" returns)
2978 - SP ID (the same as what "getspid" returns)
2981 TOTALPVTMEMSIZE. In the per-wave layout, the
2984 - offset % 4 (offset within dword)
2985 - fiber id
2986 - offset / 4
2987 - wavefront id
2988 - SP ID
2992 wavefront). In the per-fiber layout, the indices
2995 - offset
2996 - fiber id % 4
2997 - wavefront id
2998 - fiber id / 4
2999 - SP ID
3005 with per-fiber layout. The blob will fall back
3006 to per-wave instead.
3016 stack seems to be after all the normal per-SP private
3033 <!-- There is no mergedregs bit, that comes from the VS. -->
3036 <!--
3041 -->
3045 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
3057 <!-- There is no mergedregs bit, that comes from the VS. -->
3062 <!-- TODO: exact same layout as 0xa802-0xa81a -->
3081 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
3093 <!-- There is no mergedregs bit, that comes from the VS. -->
3101 size less than 63 - size
3102 size of 63 (?) or 64 - 63
3103 size greater than 64 - 64
3105 What to program when the size is 61-63 is a guess, but
3112 <!-- TODO: exact same layout as 0xa802-0xa81a -->
3132 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
3152 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
3159 <!-- note: vk blob uses bit24 -->
3175 <!-- per-mrt enable bit -->
3182 <!-- Same as RB_SRGB_CNTL -->
3230 <!-- unknown bits 0x7fc0 always set -->
3232 …<!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? …
3245 <!--
3247 skip pre-fetch.. TODO test texelFetch
3251 -->
3262 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" /> <!-- always 0x0 ? -->
3265 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
3272 <!-- seems to make SP use less concurrent threads when possible? -->
3274 <!-- has a small impact on performance, not clear what it does -->
3280 <!-- set for compute shaders -->
3284 If 0 - all 32k of shared storage is enabled, otherwise
3288 64k (and has 36k of storage on A640 - reads between 36k-64k
3293 <!-- always 1 ? -->
3307 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 -->
3314 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 -->
3316 <!-- gl_LocalInvocationIndex -->
3318 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
3319 one of those 6 "SP cores" -->
3321 <!-- Must match SP_CS_CTRL -->
3323 <!-- 1 thread per wave (ignored if bit9 set) -->
3327 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->
3335 <!-- TODO: probably align=64 with 6 flags bits in the low bits ? -->
3339 <!--
3341 -->
3345 <!--
3348 out-of-bounds isam/isamm. GL and Vulkan robustness require us to
3349 return 0 on out-of-bound textureFetch().
3350 -->
3356 <!--
3358 load a 32-bit value (so hc0.y loads the same value as c0.y)
3363 -->
3366 <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
3373 <!-- TODO: probably align=64 with 6 flags bits in the low bits? -->
3377 <!--
3380 -->
3388 <!-- looks like HW only cares about the base type of this format,
3389 which matches the ifmt? -->
3391 <!-- set when ifmt is R2D_UNORM8_SRGB -->
3393 <!-- some sort of channel mask, not sure what it is for -->
3400 <!-- TODO: valid bits 0x3c3f, see kernel -->
3408 <!-- some perfcntrs are affected by a per-stage enable bit
3410 TODO: verify position of HS/DS/GS bits -->
3419 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
3420 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
3423 <!--
3427 -->
3435 <!-- could be all the stuff below here is actually TPL1?? -->
3446 <!-- looks to work in the same way as a5xx: -->
3457 <!--
3461 -->
3473 <!-- planes for NV12, etc. (TODO: not tested) -->
3487 <!-- always 0x100000 or 0x1000000? -->
3494 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
3498 …fset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint"/> <!-- always 0x0 or 0x44 ? -->
3506 <!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
3523 <!-- must match SP_FS_CTRL -->
3528 …reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean"/> <!-- never used by blob -->
3531 <!-- TODO: have test cases with either 0x3 or 0x7 -->
3535 <!-- SAMPLEID is loaded into a half-precision register: -->
3541 <!-- register loaded with position (bary.f) -->
3559 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
3562 <!-- localsize is value minus one: -->
3586 <!-- these are all vec3. first 3 need to be high regs
3589 -->
3596 <!-- gl_LocalInvocationIndex -->
3598 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
3599 one of those 6 "SP cores" -->
3601 <!-- Must match SP_CS_CTRL -->
3603 <!-- 1 thread per wave (ignored if bit9 set) -->
3606 <!--note: vulkan blob doesn't use these -->
3615 <!-- mirror of SP_CS_BINDLESS_BASE -->
3617 <!-- 64 alignment, 2 low bits for unknown flags (always 0x3 when enabled?) -->
3621 <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->
3625 <!-- always 1 ? -->
3638 <!-- I think only the low bit is actually used? -->
3650 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
3661 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
3665 <!-- SS6_BINDLESS: one bit per bindless base -->
3678 c504-c511 in each stage. Both VS and FS shared consts
3694 <!-- mirror of SP_BINDLESS_BASE -->
3696 <!-- align 64 with two LSB for unknown flags (always 0x3 enabled) -->
3705 <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/> <!-- all bits valid except bit 29 -->
3712 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
3715 <!--
3718 - write EVENT_CMD pipe register
3719 - write CP_EVENT_START
3720 - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
3721 - write PC_EVENT_CMD with event or PC_DRAW_CMD
3722 - write HLSQ_EVENT_CMD(CONTEXT_DONE)
3723 - write PC_EVENT_CMD(CONTEXT_DONE)
3724 - write CP_EVENT_END
3726 -->
3741 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3744 <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3748 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
3750 <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3757 <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3778 … name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3784 [-1, 1] if the format is snorm, *after*
3805 <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3813 <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3828 <!-- overlaps with MIPLVLS -->
3833 <!--
3837 -->
3845 <!--
3850 …behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.bu…
3851 -->
3853 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
3860 <!--
3865 -->
3868 <!--
3872 -->
3876 <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
3877 the address of the non-flag base buffer is determined automatically,
3879 -->
3888 <!-- overlaps with PLANE_PITCH -->
3890 <!-- pitch for plane 2 / plane 3 -->
3893 <!-- 7/8 is plane 2 address for planar formats -->
3900 <!-- 9/10 is plane 3 address for planar formats -->
3906 <!-- log2 size of the first level, required for mipmapping -->
3923 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->