Lines Matching refs:rtex
815 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; in r600_init_color_surface() local
826 if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) { in r600_init_color_surface()
828 rtex = rtex->flushed_depth_texture; in r600_init_color_surface()
829 assert(rtex); in r600_init_color_surface()
832 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; in r600_init_color_surface()
836 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1; in r600_init_color_surface()
837 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) … in r600_init_color_surface()
842 switch (rtex->surface.u.legacy.level[level].mode) { in r600_init_color_surface()
881 do_endian_swap = !rtex->db_compatible; in r600_init_color_surface()
960 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource); in r600_init_color_surface()
961 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource); in r600_init_color_surface()
963 if (rtex->cmask.size) { in r600_init_color_surface()
964 surf->cb_color_cmask = rtex->cmask.offset >> 8; in r600_init_color_surface()
965 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max); in r600_init_color_surface()
967 if (rtex->fmask.size) { in r600_init_color_surface()
969 surf->cb_color_fmask = rtex->fmask.offset >> 8; in r600_init_color_surface()
970 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max); in r600_init_color_surface()
984 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask); in r600_init_color_surface()
985 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask); in r600_init_color_surface()
1045 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; in r600_init_depth_surface() local
1049 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256; in r600_init_depth_surface()
1050 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1; in r600_init_depth_surface()
1051 …slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) … in r600_init_depth_surface()
1055 switch (rtex->surface.u.legacy.level[level].mode) { in r600_init_depth_surface()
1074 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1; in r600_init_depth_surface()
1076 if (r600_htile_enabled(rtex, level)) { in r600_init_depth_surface()
1077 surf->db_htile_data_base = rtex->htile_offset >> 8; in r600_init_depth_surface()
1093 struct r600_texture *rtex; in r600_set_framebuffer_state() local
1133 rtex = (struct r600_texture*)surf->base.texture; in r600_set_framebuffer_state()
1150 if (rtex->fmask.size) { in r600_set_framebuffer_state()
1555 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture; in r600_emit_db_state() local
1558 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value)); in r600_emit_db_state()
1561 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource, in r600_emit_db_state()