Lines Matching refs:devinfo
1097 reset_masks(struct intel_device_info *devinfo) in reset_masks() argument
1099 devinfo->subslice_slice_stride = 0; in reset_masks()
1100 devinfo->eu_subslice_stride = 0; in reset_masks()
1101 devinfo->eu_slice_stride = 0; in reset_masks()
1103 devinfo->num_slices = 0; in reset_masks()
1104 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices)); in reset_masks()
1106 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks)); in reset_masks()
1107 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks)); in reset_masks()
1108 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks)); in reset_masks()
1109 memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices)); in reset_masks()
1113 update_slice_subslice_counts(struct intel_device_info *devinfo) in update_slice_subslice_counts() argument
1115 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks); in update_slice_subslice_counts()
1116 devinfo->subslice_total = 0; in update_slice_subslice_counts()
1117 for (int s = 0; s < devinfo->max_slices; s++) { in update_slice_subslice_counts()
1118 if (!intel_device_info_slice_available(devinfo, s)) in update_slice_subslice_counts()
1121 for (int b = 0; b < devinfo->subslice_slice_stride; b++) { in update_slice_subslice_counts()
1122 devinfo->num_subslices[s] += in update_slice_subslice_counts()
1123 __builtin_popcount(devinfo->subslice_masks[s * devinfo->subslice_slice_stride + b]); in update_slice_subslice_counts()
1125 devinfo->subslice_total += devinfo->num_subslices[s]; in update_slice_subslice_counts()
1127 assert(devinfo->num_slices > 0); in update_slice_subslice_counts()
1128 assert(devinfo->subslice_total > 0); in update_slice_subslice_counts()
1132 update_pixel_pipes(struct intel_device_info *devinfo, uint8_t *subslice_masks) in update_pixel_pipes() argument
1134 if (devinfo->ver < 11) in update_pixel_pipes()
1142 assert(devinfo->slice_masks == 1 || devinfo->verx10 >= 125); in update_pixel_pipes()
1151 const unsigned ppipe_bits = devinfo->ver >= 12 ? 2 : 4; in update_pixel_pipes()
1155 devinfo->max_subslices_per_slice * devinfo->subslice_slice_stride; in update_pixel_pipes()
1157 BITFIELD_RANGE(offset % devinfo->max_subslices_per_slice, ppipe_bits); in update_pixel_pipes()
1159 if (subslice_idx < ARRAY_SIZE(devinfo->subslice_masks)) in update_pixel_pipes()
1160 devinfo->ppipe_subslices[p] = in update_pixel_pipes()
1163 devinfo->ppipe_subslices[p] = 0; in update_pixel_pipes()
1168 update_l3_banks(struct intel_device_info *devinfo) in update_l3_banks() argument
1170 if (devinfo->ver != 12) in update_l3_banks()
1173 if (devinfo->verx10 >= 125) { in update_l3_banks()
1174 if (devinfo->subslice_total > 16) { in update_l3_banks()
1175 assert(devinfo->subslice_total <= 32); in update_l3_banks()
1176 devinfo->l3_banks = 32; in update_l3_banks()
1177 } else if (devinfo->subslice_total > 8) { in update_l3_banks()
1178 devinfo->l3_banks = 16; in update_l3_banks()
1180 devinfo->l3_banks = 8; in update_l3_banks()
1183 assert(devinfo->num_slices == 1); in update_l3_banks()
1184 if (devinfo->subslice_total >= 6) { in update_l3_banks()
1185 assert(devinfo->subslice_total == 6); in update_l3_banks()
1186 devinfo->l3_banks = 8; in update_l3_banks()
1187 } else if (devinfo->subslice_total > 2) { in update_l3_banks()
1188 devinfo->l3_banks = 6; in update_l3_banks()
1190 devinfo->l3_banks = 4; in update_l3_banks()
1205 update_from_single_slice_topology(struct intel_device_info *devinfo, in update_from_single_slice_topology() argument
1214 uint8_t geom_subslice_masks[ARRAY_SIZE(devinfo->subslice_masks)] = { 0 }; in update_from_single_slice_topology()
1216 assert(devinfo->verx10 >= 125); in update_from_single_slice_topology()
1218 reset_masks(devinfo); in update_from_single_slice_topology()
1227 devinfo->max_subslices_per_slice = 4; in update_from_single_slice_topology()
1228 devinfo->max_eus_per_subslice = 16; in update_from_single_slice_topology()
1229 devinfo->subslice_slice_stride = 1; in update_from_single_slice_topology()
1230 devinfo->eu_slice_stride = DIV_ROUND_UP(16 * 4, 8); in update_from_single_slice_topology()
1231 devinfo->eu_subslice_stride = DIV_ROUND_UP(16, 8); in update_from_single_slice_topology()
1250 geom_subslice_masks[s * devinfo->subslice_slice_stride + in update_from_single_slice_topology()
1257 devinfo->max_slices = MAX2(devinfo->max_slices, s + 1); in update_from_single_slice_topology()
1258 devinfo->slice_masks |= 1u << s; in update_from_single_slice_topology()
1260 devinfo->subslice_masks[s * devinfo->subslice_slice_stride + in update_from_single_slice_topology()
1263 for (uint32_t eu = 0; eu < devinfo->max_eus_per_subslice; eu++) { in update_from_single_slice_topology()
1272 devinfo->eu_masks[s * devinfo->eu_slice_stride + in update_from_single_slice_topology()
1273 ss * devinfo->eu_subslice_stride + in update_from_single_slice_topology()
1278 update_slice_subslice_counts(devinfo); in update_from_single_slice_topology()
1279 update_pixel_pipes(devinfo, geom_subslice_masks); in update_from_single_slice_topology()
1280 update_l3_banks(devinfo); in update_from_single_slice_topology()
1284 update_from_topology(struct intel_device_info *devinfo, in update_from_topology() argument
1287 reset_masks(devinfo); in update_from_topology()
1293 devinfo->subslice_slice_stride = topology->subslice_stride; in update_from_topology()
1295 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8); in update_from_topology()
1296 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride; in update_from_topology()
1298 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8)); in update_from_topology()
1299 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8)); in update_from_topology()
1300 devinfo->max_slices = topology->max_slices; in update_from_topology()
1301 devinfo->max_subslices_per_slice = topology->max_subslices; in update_from_topology()
1302 devinfo->max_eus_per_subslice = topology->max_eus_per_subslice; in update_from_topology()
1306 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len); in update_from_topology()
1307 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset], in update_from_topology()
1312 assert(sizeof(devinfo->eu_masks) >= eu_mask_len); in update_from_topology()
1313 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len); in update_from_topology()
1316 update_slice_subslice_counts(devinfo); in update_from_topology()
1317 update_pixel_pipes(devinfo, devinfo->subslice_masks); in update_from_topology()
1318 update_l3_banks(devinfo); in update_from_topology()
1325 update_from_masks(struct intel_device_info *devinfo, uint32_t slice_mask, in update_from_masks() argument
1379 update_from_topology(devinfo, topology); in update_from_masks()
1387 fill_masks(struct intel_device_info *devinfo) in fill_masks() argument
1392 for (int s = 1; s < devinfo->num_slices; s++) in fill_masks()
1393 assert(devinfo->num_subslices[0] == devinfo->num_subslices[s]); in fill_masks()
1395 update_from_masks(devinfo, in fill_masks()
1396 (1U << devinfo->num_slices) - 1, in fill_masks()
1397 (1U << devinfo->num_subslices[0]) - 1, in fill_masks()
1398 devinfo->num_slices * devinfo->num_subslices[0] * in fill_masks()
1399 devinfo->max_eus_per_subslice); in fill_masks()
1437 update_cs_workgroup_threads(struct intel_device_info *devinfo) in update_cs_workgroup_threads() argument
1446 devinfo->max_cs_workgroup_threads = in update_cs_workgroup_threads()
1447 devinfo->verx10 >= 125 ? devinfo->max_cs_threads : in update_cs_workgroup_threads()
1448 MIN2(devinfo->max_cs_threads, 64); in update_cs_workgroup_threads()
1453 struct intel_device_info *devinfo) in intel_get_device_info_from_pci_id() argument
1458 case id: *devinfo = intel_device_info_##family; break; in intel_get_device_info_from_pci_id()
1464 case id: *devinfo = intel_device_info_gfx3; break; in intel_get_device_info_from_pci_id()
1478 sizeof(devinfo->name)); \ in intel_get_device_info_from_pci_id()
1479 strncpy(devinfo->name, _name " (" _fam_str ")", sizeof(devinfo->name)); \ in intel_get_device_info_from_pci_id()
1484 strncpy(devinfo->name, "Intel Unknown", sizeof(devinfo->name)); in intel_get_device_info_from_pci_id()
1487 fill_masks(devinfo); in intel_get_device_info_from_pci_id()
1503 switch(devinfo->ver) { in intel_get_device_info_from_pci_id()
1505 devinfo->max_wm_threads = 64 /* threads-per-PSD */ in intel_get_device_info_from_pci_id()
1506 * devinfo->num_slices in intel_get_device_info_from_pci_id()
1511 devinfo->max_wm_threads = 128 /* threads-per-PSD */ in intel_get_device_info_from_pci_id()
1512 * devinfo->num_slices in intel_get_device_info_from_pci_id()
1516 assert(devinfo->ver < 9); in intel_get_device_info_from_pci_id()
1520 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices)); in intel_get_device_info_from_pci_id()
1522 if (devinfo->verx10 == 0) in intel_get_device_info_from_pci_id()
1523 devinfo->verx10 = devinfo->ver * 10; in intel_get_device_info_from_pci_id()
1525 if (devinfo->display_ver == 0) in intel_get_device_info_from_pci_id()
1526 devinfo->display_ver = devinfo->ver; in intel_get_device_info_from_pci_id()
1528 update_cs_workgroup_threads(devinfo); in intel_get_device_info_from_pci_id()
1538 getparam_topology(struct intel_device_info *devinfo, int fd) in getparam_topology() argument
1552 return update_from_masks(devinfo, slice_mask, subslice_mask, n_eus); in getparam_topology()
1558 if (devinfo->ver >= 8) in getparam_topology()
1568 query_topology(struct intel_device_info *devinfo, int fd) in query_topology() argument
1575 if (devinfo->verx10 >= 125) { in query_topology()
1583 update_from_single_slice_topology(devinfo, topo_info, geom_topo_info); in query_topology()
1586 update_from_topology(devinfo, topo_info); in query_topology()
1600 query_regions(struct intel_device_info *devinfo, int fd, bool update) in query_regions() argument
1612 devinfo->mem.sram.mem_class = mem->region.memory_class; in query_regions()
1613 devinfo->mem.sram.mem_instance = mem->region.memory_instance; in query_regions()
1614 devinfo->mem.sram.mappable.size = mem->probed_size; in query_regions()
1616 assert(devinfo->mem.sram.mem_class == mem->region.memory_class); in query_regions()
1617 assert(devinfo->mem.sram.mem_instance == mem->region.memory_instance); in query_regions()
1618 assert(devinfo->mem.sram.mappable.size == mem->probed_size); in query_regions()
1625 devinfo->mem.sram.mappable.free = MIN2(available, mem->probed_size); in query_regions()
1630 devinfo->mem.vram.mem_class = mem->region.memory_class; in query_regions()
1631 devinfo->mem.vram.mem_instance = mem->region.memory_instance; in query_regions()
1633 devinfo->mem.vram.mappable.size = mem->probed_cpu_visible_size; in query_regions()
1634 devinfo->mem.vram.unmappable.size = in query_regions()
1641 devinfo->mem.vram.mappable.size = mem->probed_size; in query_regions()
1642 devinfo->mem.vram.unmappable.size = 0; in query_regions()
1645 assert(devinfo->mem.vram.mem_class == mem->region.memory_class); in query_regions()
1646 assert(devinfo->mem.vram.mem_instance == mem->region.memory_instance); in query_regions()
1647 assert((devinfo->mem.vram.mappable.size + in query_regions()
1648 devinfo->mem.vram.unmappable.size) == mem->probed_size); in query_regions()
1652 devinfo->mem.vram.mappable.free = mem->unallocated_cpu_visible_size; in query_regions()
1653 devinfo->mem.vram.unmappable.free = in query_regions()
1662 devinfo->mem.vram.mappable.free = mem->unallocated_size; in query_regions()
1663 devinfo->mem.vram.unmappable.free = 0; in query_regions()
1673 devinfo->mem.use_class_instance = true; in query_regions()
1678 compute_system_memory(struct intel_device_info *devinfo, bool update) in compute_system_memory() argument
1688 devinfo->mem.sram.mappable.size = total_phys; in compute_system_memory()
1690 assert(devinfo->mem.sram.mappable.size == total_phys); in compute_system_memory()
1692 devinfo->mem.sram.mappable.free = available; in compute_system_memory()
1792 fixup_chv_device_info(struct intel_device_info *devinfo) in fixup_chv_device_info() argument
1794 assert(devinfo->platform == INTEL_PLATFORM_CHV); in fixup_chv_device_info()
1801 const uint32_t subslice_total = intel_device_info_subslice_total(devinfo); in fixup_chv_device_info()
1802 const uint32_t eu_total = intel_device_info_eu_total(devinfo); in fixup_chv_device_info()
1806 eu_total / subslice_total * devinfo->num_thread_per_eu; in fixup_chv_device_info()
1809 if (max_cs_threads > devinfo->max_cs_threads) in fixup_chv_device_info()
1810 devinfo->max_cs_threads = max_cs_threads; in fixup_chv_device_info()
1812 update_cs_workgroup_threads(devinfo); in fixup_chv_device_info()
1817 if (devinfo->pci_device_id != 0x22B1) in fixup_chv_device_info()
1827 char *needle = strstr(devinfo->name, "XXX"); in fixup_chv_device_info()
1834 init_max_scratch_ids(struct intel_device_info *devinfo) in init_max_scratch_ids() argument
1857 if (devinfo->verx10 == 125) in init_max_scratch_ids()
1859 else if (devinfo->ver == 12) in init_max_scratch_ids()
1860 subslices = (devinfo->platform == INTEL_PLATFORM_DG1 || devinfo->gt == 2 ? 6 : 2); in init_max_scratch_ids()
1861 else if (devinfo->ver == 11) in init_max_scratch_ids()
1863 else if (devinfo->ver >= 9 && devinfo->ver < 11) in init_max_scratch_ids()
1864 subslices = 4 * devinfo->num_slices; in init_max_scratch_ids()
1866 subslices = devinfo->subslice_total; in init_max_scratch_ids()
1867 assert(subslices >= devinfo->subslice_total); in init_max_scratch_ids()
1870 if (devinfo->ver >= 12) { in init_max_scratch_ids()
1873 } else if (devinfo->ver >= 11) { in init_max_scratch_ids()
1885 } else if (devinfo->platform == INTEL_PLATFORM_HSW) { in init_max_scratch_ids()
1902 } else if (devinfo->platform == INTEL_PLATFORM_CHV) { in init_max_scratch_ids()
1909 scratch_ids_per_subslice = devinfo->max_cs_threads; in init_max_scratch_ids()
1914 if (devinfo->verx10 >= 125) { in init_max_scratch_ids()
1921 devinfo->max_scratch_ids[i] = max_thread_ids; in init_max_scratch_ids()
1924 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads, in init_max_scratch_ids()
1925 [MESA_SHADER_TESS_CTRL] = devinfo->max_tcs_threads, in init_max_scratch_ids()
1926 [MESA_SHADER_TESS_EVAL] = devinfo->max_tes_threads, in init_max_scratch_ids()
1927 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads, in init_max_scratch_ids()
1928 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads, in init_max_scratch_ids()
1931 STATIC_ASSERT(sizeof(devinfo->max_scratch_ids) == sizeof(max_scratch_ids)); in init_max_scratch_ids()
1932 memcpy(devinfo->max_scratch_ids, max_scratch_ids, in init_max_scratch_ids()
1933 sizeof(devinfo->max_scratch_ids)); in init_max_scratch_ids()
1938 intel_get_device_info_from_fd(int fd, struct intel_device_info *devinfo) in intel_get_device_info_from_fd() argument
1955 (drmdev->deviceinfo.pci->device_id, devinfo)) { in intel_get_device_info_from_fd()
1959 devinfo->pci_domain = drmdev->businfo.pci->domain; in intel_get_device_info_from_fd()
1960 devinfo->pci_bus = drmdev->businfo.pci->bus; in intel_get_device_info_from_fd()
1961 devinfo->pci_dev = drmdev->businfo.pci->dev; in intel_get_device_info_from_fd()
1962 devinfo->pci_func = drmdev->businfo.pci->func; in intel_get_device_info_from_fd()
1963 devinfo->pci_device_id = drmdev->deviceinfo.pci->device_id; in intel_get_device_info_from_fd()
1964 devinfo->pci_revision_id = drmdev->deviceinfo.pci->revision_id; in intel_get_device_info_from_fd()
1966 devinfo->no_hw = env_var_as_boolean("INTEL_NO_HW", false); in intel_get_device_info_from_fd()
1968 if (devinfo->ver == 10) { in intel_get_device_info_from_fd()
1974 if (devinfo->no_hw) { in intel_get_device_info_from_fd()
1976 devinfo->gtt_size = in intel_get_device_info_from_fd()
1977 devinfo->ver >= 8 ? (1ull << 48) : 2ull * 1024 * 1024 * 1024; in intel_get_device_info_from_fd()
1978 compute_system_memory(devinfo, false); in intel_get_device_info_from_fd()
1982 if (intel_get_and_process_hwconfig_table(fd, devinfo)) { in intel_get_device_info_from_fd()
1984 devinfo->max_cs_threads = in intel_get_device_info_from_fd()
1985 devinfo->max_eus_per_subslice * devinfo->num_thread_per_eu; in intel_get_device_info_from_fd()
1987 update_cs_workgroup_threads(devinfo); in intel_get_device_info_from_fd()
1993 devinfo->timestamp_frequency = timestamp_frequency; in intel_get_device_info_from_fd()
1994 else if (devinfo->ver >= 10) { in intel_get_device_info_from_fd()
1999 if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision)) in intel_get_device_info_from_fd()
2000 devinfo->revision = 0; in intel_get_device_info_from_fd()
2002 if (!query_topology(devinfo, fd)) { in intel_get_device_info_from_fd()
2003 if (devinfo->ver >= 10) { in intel_get_device_info_from_fd()
2011 getparam_topology(devinfo, fd); in intel_get_device_info_from_fd()
2017 if (!query_regions(devinfo, fd, false)) in intel_get_device_info_from_fd()
2018 compute_system_memory(devinfo, false); in intel_get_device_info_from_fd()
2021 if (devinfo->has_local_mem && !devinfo->mem.use_class_instance) { in intel_get_device_info_from_fd()
2026 if (devinfo->platform == INTEL_PLATFORM_CHV) in intel_get_device_info_from_fd()
2027 fixup_chv_device_info(devinfo); in intel_get_device_info_from_fd()
2040 devinfo->has_bit6_swizzle = devinfo->ver < 8 && has_bit6_swizzle(fd); in intel_get_device_info_from_fd()
2042 intel_get_aperture_size(fd, &devinfo->aperture_bytes); in intel_get_device_info_from_fd()
2043 get_context_param(fd, 0, I915_CONTEXT_PARAM_GTT_SIZE, &devinfo->gtt_size); in intel_get_device_info_from_fd()
2044 devinfo->has_tiling_uapi = has_get_tiling(fd); in intel_get_device_info_from_fd()
2047 assert(devinfo->subslice_total >= 1 || devinfo->ver <= 7); in intel_get_device_info_from_fd()
2048 devinfo->subslice_total = MAX2(devinfo->subslice_total, 1); in intel_get_device_info_from_fd()
2050 init_max_scratch_ids(devinfo); in intel_get_device_info_from_fd()
2055 bool intel_device_info_update_memory_info(struct intel_device_info *devinfo, int fd) in intel_device_info_update_memory_info() argument
2057 return query_regions(devinfo, fd, true) || compute_system_memory(devinfo, true); in intel_device_info_update_memory_info()