Lines Matching refs:u0
30 80 7c 47 20 00 c0 a3 01 SHADDX.u64 r0, u0, ^r60.w0, shift:0x4
61 80 00 00 00 82 82 60 00 LOAD.i8.unsigned.slot0 @r2, u0, offset:0
62 80 00 00 08 82 82 60 00 LOAD.i16.unsigned.slot0 @r2, u0, offset:0
63 80 00 00 10 82 82 60 00 LOAD.i24.unsigned.slot0 @r2, u0, offset:0
64 80 00 00 18 82 82 60 00 LOAD.i32.unsigned.slot0 @r2, u0, offset:0
65 80 00 00 20 c4 82 60 00 LOAD.i48.unsigned.slot0 @r2:r3, u0, offset:0
66 80 00 00 28 f4 82 60 00 LOAD.i64.unsigned.slot0 @r2:r3, u0, offset:0
67 80 00 00 30 e6 82 60 00 LOAD.i96.unsigned.slot0 @r2:r3:r4, u0, offset:0
68 80 00 00 38 f8 84 60 00 LOAD.i128.unsigned.slot0 @r4:r5:r6:r7, u0, offset:0
69 80 00 00 18 94 82 60 00 LOAD.i32.d0.unsigned.slot0 @r2:r3, u0, offset:0
70 80 00 00 18 14 82 60 00 LOAD.i32.d0.slot0 @r2:r3, u0, offset:0
71 80 00 00 08 34 82 60 00 LOAD.i16.d0.slot0 @r2:r3, u0, offset:0
72 80 00 00 00 74 82 60 00 LOAD.i8.d0.slot0 @r2:r3, u0, offset:0
73 80 00 00 00 f4 82 60 00 LOAD.i8.d0.unsigned.slot0 @r2:r3, u0, offset:0
74 80 00 00 08 22 82 60 00 LOAD.i16.w0.slot0 @r2, u0, offset:0
75 80 00 00 00 62 82 60 00 LOAD.i8.w0.slot0 @r2, u0, offset:0
76 80 00 00 00 c2 82 60 00 LOAD.i8.h0.unsigned.slot0 @r2, u0, offset:0
77 80 14 00 08 92 82 60 00 LOAD.i16.h1.unsigned.slot0 @r2, u0, offset:20
78 80 00 00 08 82 82 60 00 LOAD.i16.unsigned.slot0 @r2, u0, offset:0
100 80 00 27 20 00 c2 a3 01 SHADDX.u64 r2, u0, r0.w0, shift:0x2
115 80 81 00 68 f4 80 6a 00 LD_BUFFER.i64.unsigned.slot1 @r0:r1, u0, u1
122 40 44 80 00 00 c0 b8 00 MUX.i32.neg r0, ^r0, ^r4, u0
123 40 44 80 00 01 c0 b8 00 MUX.i32 r0, ^r0, ^r4, u0
124 40 44 80 00 02 c0 b8 00 MUX.i32.fp_zero r0, ^r0, ^r4, u0
125 40 44 80 00 03 c0 b8 00 MUX.i32.bit r0, ^r0, ^r4, u0
191 81 0b 80 33 04 8e 78 00 LD_TILE.v4.f16.slot0 @r14:r15, u1, r11, u0
216 80 00 c0 17 34 7c 25 01 TEX_FETCH.slot0.f.32.2d @r0:r1:r2:r3, @r60:r61, u0
223 … 80 15 b4 80 38 49 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.zero.wait @r0:r1:r2:r3, u2, u0
224 …5 b4 80 38 09 VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.computed.wait0 @r0:r1:r2:r3, u2, u0
225 …0 80 1d 84 80 38 41 VAR_TEX_SINGLE.slot0.skip.sample_store.s.32.2d.computed.wait0126 @r0, u2, u0