705                 bool branch = alu && (unit == ALU_ENAB_BR_COMPACT);  in mir_choose_instruction()  local
713                 if (alu && !branch && unit != ~0 && !(mir_has_unit(instructions[i], unit)))  in mir_choose_instruction()
720                 if (branch && !instructions[i]->compact_branch)  in mir_choose_instruction()
741                 bool conditional = alu && !branch && OP_IS_CSEL(instructions[i]->op);  in mir_choose_instruction()
742                 conditional |= (branch && instructions[i]->branch.conditional);  in mir_choose_instruction()
971         bool branch = last->compact_branch;  in mir_schedule_condition()  local
972         unsigned condition_index = branch ? 0 : 2;  in mir_schedule_condition()
975         bool vector = !branch && OP_IS_CSEL_V(last->op);  in mir_schedule_condition()
1008         if (branch)  in mir_schedule_condition()
1095                 midgard_instruction *branch,  in mir_schedule_zs_write()  argument
1103         unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx];  in mir_schedule_zs_write()
1136         branch->src[idx] = mov->dest;  in mir_schedule_zs_write()
1139                 unsigned swizzle = (branch->src[0] == ~0) ? COMPONENT_Y : COMPONENT_X;  in mir_schedule_zs_write()
1179         midgard_instruction *branch = NULL;  in mir_schedule_alu()  local
1181 …   mir_choose_alu(&branch, instructions, liveness, worklist, len, &predicate, ALU_ENAB_BR_COMPACT);  in mir_schedule_alu()
1182         mir_update_worklist(worklist, len, instructions, branch);  in mir_schedule_alu()
1183         unsigned writeout = branch ? branch->writeout : 0;  in mir_schedule_alu()
1185         if (branch && branch->branch.conditional) {  in mir_schedule_alu()
1186 …d_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, branch);  in mir_schedule_alu()
1200         if (writeout && (branch->constants.u32[0] || ctx->inputs->is_blend)) {  in mir_schedule_alu()
1206                 sadd->inline_constant = branch->constants.u32[0];  in mir_schedule_alu()
1207                 branch->src[1] = sadd->dest;  in mir_schedule_alu()
1208                 branch->src_types[1] = sadd->dest_type;  in mir_schedule_alu()
1213                 bundle.last_writeout = branch->last_writeout;  in mir_schedule_alu()
1251                 branch->dest = vadd->dest;  in mir_schedule_alu()
1252                 branch->dest_type = vadd->dest_type;  in mir_schedule_alu()
1256 …chedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vl…  in mir_schedule_alu()
1259 …chedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vl…  in mir_schedule_alu()
1300                 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0];  in mir_schedule_alu()
1312                         bad_writeout |= mir_has_arg(stages[i], branch->src[0]);  in mir_schedule_alu()
1342 …          unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx);  in mir_schedule_alu()
1358                         mir_rewrite_index_src_single(branch, src, temp);  in mir_schedule_alu()
1372         midgard_instruction *stages[] = { vmul, sadd, vadd, smul, vlut, branch };  in mir_schedule_alu()
1385                         if (branch)  in mir_schedule_alu()
1404         bool tilebuf_wait = branch && branch->compact_branch &&  in mir_schedule_alu()
1405            branch->branch.target_type == TARGET_TILEBUF_WAIT;  in mir_schedule_alu()