Lines Matching refs:NMI
346 9.2.1 NMI Masks Further NMls
2323 2 NMI Interrupt
7726 Nonmaskable interrupts, which are signalled via the NMI
7747 The NMI and the exceptions recognized by the processor are assigned
7818 9.2.1 NMI Masks Further NMIs
7820 While an NMI handler is executing, the processor ignores further interrupt
7821 signals at the NMI pin until the next IRET instruction is executed.
7871 SS instruction, inhibits NMI, INTR, debug exceptions, and single-step traps
7927 NMI interrupt
8387 2 NMI
8936 or nonmaskable interrupt (NMI) occurs. Initialization software should take
10882 13. NMI interrupting NMI handlers.
10884 After an NMI is recognized on the 80386, the NMI interrupt is masked
11703 13. NMI interrupting NMI handlers.
11705 After an NMI is recognized on the 80386, the NMI interrupt is masked
15063 An enabled interrupt, NMI, or a reset will resume execution. If an
15064 interrupt (including NMI) is used to resume execution after HLT, the saved
18082 A POP SS instruction inhibits all interrupts, including NMI, until after