1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * ddbridge-regs.h: Digital Devices PCIe bridge driver 4 * 5 * Copyright (C) 2010-2017 Digital Devices GmbH 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 only, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef __DDBRIDGE_REGS_H__ 18 #define __DDBRIDGE_REGS_H__ 19 20 /* ------------------------------------------------------------------------- */ 21 /* SPI Controller */ 22 23 #define SPI_CONTROL 0x10 24 #define SPI_DATA 0x14 25 26 /* ------------------------------------------------------------------------- */ 27 /* GPIO */ 28 29 #define GPIO_OUTPUT 0x20 30 #define GPIO_INPUT 0x24 31 #define GPIO_DIRECTION 0x28 32 33 /* ------------------------------------------------------------------------- */ 34 35 #define BOARD_CONTROL 0x30 36 37 /* ------------------------------------------------------------------------- */ 38 39 /* Interrupt controller 40 * How many MSI's are available depends on HW (Min 2 max 8) 41 * How many are usable also depends on Host platform 42 */ 43 44 #define INTERRUPT_BASE (0x40) 45 46 #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00) 47 #define MSI1_ENABLE (INTERRUPT_BASE + 0x04) 48 #define MSI2_ENABLE (INTERRUPT_BASE + 0x08) 49 #define MSI3_ENABLE (INTERRUPT_BASE + 0x0C) 50 #define MSI4_ENABLE (INTERRUPT_BASE + 0x10) 51 #define MSI5_ENABLE (INTERRUPT_BASE + 0x14) 52 #define MSI6_ENABLE (INTERRUPT_BASE + 0x18) 53 #define MSI7_ENABLE (INTERRUPT_BASE + 0x1C) 54 55 #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) 56 #define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) 57 58 /* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */ 59 #define TEMPMON_BASE (0x1c0) 60 #define TEMPMON_CONTROL (TEMPMON_BASE + 0x00) 61 62 #define TEMPMON_CONTROL_AUTOSCAN (0x00000002) 63 #define TEMPMON_CONTROL_INTENABLE (0x00000004) 64 #define TEMPMON_CONTROL_OVERTEMP (0x00008000) 65 66 /* SHORT Temperature in Celsius x 256 */ 67 #define TEMPMON_SENSOR0 (TEMPMON_BASE + 0x04) 68 #define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08) 69 70 #define TEMPMON_FANCONTROL (TEMPMON_BASE + 0x10) 71 72 /* ------------------------------------------------------------------------- */ 73 /* I2C Master Controller */ 74 75 #define I2C_COMMAND (0x00) 76 #define I2C_TIMING (0x04) 77 #define I2C_TASKLENGTH (0x08) /* High read, low write */ 78 #define I2C_TASKADDRESS (0x0C) /* High read, low write */ 79 #define I2C_MONITOR (0x1C) 80 81 #define I2C_SPEED_400 (0x04030404) 82 #define I2C_SPEED_100 (0x13121313) 83 84 /* ------------------------------------------------------------------------- */ 85 /* DMA Controller */ 86 87 #define DMA_BASE_WRITE (0x100) 88 #define DMA_BASE_READ (0x140) 89 90 #define TS_CONTROL(_io) ((_io)->regs + 0x00) 91 #define TS_CONTROL2(_io) ((_io)->regs + 0x04) 92 93 /* ------------------------------------------------------------------------- */ 94 /* DMA Buffer */ 95 96 #define DMA_BUFFER_CONTROL(_dma) ((_dma)->regs + 0x00) 97 #define DMA_BUFFER_ACK(_dma) ((_dma)->regs + 0x04) 98 #define DMA_BUFFER_CURRENT(_dma) ((_dma)->regs + 0x08) 99 #define DMA_BUFFER_SIZE(_dma) ((_dma)->regs + 0x0c) 100 101 /* ------------------------------------------------------------------------- */ 102 /* CI Interface (only CI-Bridge) */ 103 104 #define CI_BASE (0x400) 105 #define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00) 106 107 #define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04) 108 #define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08) 109 #define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c) 110 #define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10) 111 112 #define CI_RESET_CAM (0x00000001) 113 #define CI_POWER_ON (0x00000002) 114 #define CI_ENABLE (0x00000004) 115 #define CI_BYPASS_DISABLE (0x00000010) 116 117 #define CI_CAM_READY (0x00010000) 118 #define CI_CAM_DETECT (0x00020000) 119 #define CI_READY (0x80000000) 120 121 #define CI_READ_CMD (0x40000000) 122 #define CI_WRITE_CMD (0x80000000) 123 124 #define CI_BUFFER_BASE (0x3000) 125 #define CI_BUFFER_SIZE (0x0800) 126 127 #define CI_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE) 128 129 /* ------------------------------------------------------------------------- */ 130 /* LNB commands (mxl5xx / Max S8) */ 131 132 #define LNB_BASE (0x400) 133 #define LNB_CONTROL(i) (LNB_BASE + (i) * 0x20 + 0x00) 134 135 #define LNB_CMD (7ULL << 0) 136 #define LNB_CMD_NOP 0 137 #define LNB_CMD_INIT 1 138 #define LNB_CMD_LOW 3 139 #define LNB_CMD_HIGH 4 140 #define LNB_CMD_OFF 5 141 #define LNB_CMD_DISEQC 6 142 143 #define LNB_BUSY BIT_ULL(4) 144 #define LNB_TONE BIT_ULL(15) 145 146 #define LNB_BUF_LEVEL(i) (LNB_BASE + (i) * 0x20 + 0x10) 147 #define LNB_BUF_WRITE(i) (LNB_BASE + (i) * 0x20 + 0x14) 148 149 #endif /* __DDBRIDGE_REGS_H__ */ 150