1 /* 2 * Copyright (c) 2019 Nuclei Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the License); you may 7 * not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 #ifndef __RISCV_ENCODING_H__ 19 #define __RISCV_ENCODING_H__ 20 21 #include "riscv_bits.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 /** 26 * \defgroup NMSIS_Core_CSR_Encoding Core CSR Encodings 27 * \ingroup NMSIS_Core 28 * \brief NMSIS Core CSR Encodings 29 * \details 30 * 31 * The following macros are used for CSR encodings 32 * @{ 33 */ 34 #define MSTATUS_UIE 0x00000001 35 #define MSTATUS_SIE 0x00000002 36 #define MSTATUS_HIE 0x00000004 37 #define MSTATUS_MIE 0x00000008 38 #define MSTATUS_UPIE 0x00000010 39 #define MSTATUS_SPIE 0x00000020 40 #define MSTATUS_HPIE 0x00000040 41 #define MSTATUS_MPIE 0x00000080 42 #define MSTATUS_SPP 0x00000100 43 #define MSTATUS_MPP 0x00001800 44 #define MSTATUS_FS 0x00006000 45 #define MSTATUS_XS 0x00018000 46 #define MSTATUS_MPRV 0x00020000 47 #define MSTATUS_PUM 0x00040000 48 #define MSTATUS_MXR 0x00080000 49 #define MSTATUS_VM 0x1F000000 50 #define MSTATUS32_SD 0x80000000 51 #define MSTATUS64_SD 0x8000000000000000 52 53 #define MSTATUS_FS_INITIAL 0x00002000 54 #define MSTATUS_FS_CLEAN 0x00004000 55 #define MSTATUS_FS_DIRTY 0x00006000 56 57 #define SSTATUS_UIE 0x00000001 58 #define SSTATUS_SIE 0x00000002 59 #define SSTATUS_UPIE 0x00000010 60 #define SSTATUS_SPIE 0x00000020 61 #define SSTATUS_SPP 0x00000100 62 #define SSTATUS_FS 0x00006000 63 #define SSTATUS_XS 0x00018000 64 #define SSTATUS_PUM 0x00040000 65 #define SSTATUS32_SD 0x80000000 66 #define SSTATUS64_SD 0x8000000000000000 67 68 #define CSR_MCACHE_CTL_IE 0x00000001 69 #define CSR_MCACHE_CTL_DE 0x00010000 70 71 #define DCSR_XDEBUGVER (3U<<30) 72 #define DCSR_NDRESET (1<<29) 73 #define DCSR_FULLRESET (1<<28) 74 #define DCSR_EBREAKM (1<<15) 75 #define DCSR_EBREAKH (1<<14) 76 #define DCSR_EBREAKS (1<<13) 77 #define DCSR_EBREAKU (1<<12) 78 #define DCSR_STOPCYCLE (1<<10) 79 #define DCSR_STOPTIME (1<<9) 80 #define DCSR_CAUSE (7<<6) 81 #define DCSR_DEBUGINT (1<<5) 82 #define DCSR_HALT (1<<3) 83 #define DCSR_STEP (1<<2) 84 #define DCSR_PRV (3<<0) 85 86 #define DCSR_CAUSE_NONE 0 87 #define DCSR_CAUSE_SWBP 1 88 #define DCSR_CAUSE_HWBP 2 89 #define DCSR_CAUSE_DEBUGINT 3 90 #define DCSR_CAUSE_STEP 4 91 #define DCSR_CAUSE_HALT 5 92 93 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) 94 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) 95 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) 96 97 #define MCONTROL_SELECT (1<<19) 98 #define MCONTROL_TIMING (1<<18) 99 #define MCONTROL_ACTION (0x3f<<12) 100 #define MCONTROL_CHAIN (1<<11) 101 #define MCONTROL_MATCH (0xf<<7) 102 #define MCONTROL_M (1<<6) 103 #define MCONTROL_H (1<<5) 104 #define MCONTROL_S (1<<4) 105 #define MCONTROL_U (1<<3) 106 #define MCONTROL_EXECUTE (1<<2) 107 #define MCONTROL_STORE (1<<1) 108 #define MCONTROL_LOAD (1<<0) 109 110 #define MCONTROL_TYPE_NONE 0 111 #define MCONTROL_TYPE_MATCH 2 112 113 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 114 #define MCONTROL_ACTION_DEBUG_MODE 1 115 #define MCONTROL_ACTION_TRACE_START 2 116 #define MCONTROL_ACTION_TRACE_STOP 3 117 #define MCONTROL_ACTION_TRACE_EMIT 4 118 119 #define MCONTROL_MATCH_EQUAL 0 120 #define MCONTROL_MATCH_NAPOT 1 121 #define MCONTROL_MATCH_GE 2 122 #define MCONTROL_MATCH_LT 3 123 #define MCONTROL_MATCH_MASK_LOW 4 124 #define MCONTROL_MATCH_MASK_HIGH 5 125 126 #define MIP_SSIP (1 << IRQ_S_SOFT) 127 #define MIP_HSIP (1 << IRQ_H_SOFT) 128 #define MIP_MSIP (1 << IRQ_M_SOFT) 129 #define MIP_STIP (1 << IRQ_S_TIMER) 130 #define MIP_HTIP (1 << IRQ_H_TIMER) 131 #define MIP_MTIP (1 << IRQ_M_TIMER) 132 #define MIP_SEIP (1 << IRQ_S_EXT) 133 #define MIP_HEIP (1 << IRQ_H_EXT) 134 #define MIP_MEIP (1 << IRQ_M_EXT) 135 136 #define MIE_SSIE MIP_SSIP 137 #define MIE_HSIE MIP_HSIP 138 #define MIE_MSIE MIP_MSIP 139 #define MIE_STIE MIP_STIP 140 #define MIE_HTIE MIP_HTIP 141 #define MIE_MTIE MIP_MTIP 142 #define MIE_SEIE MIP_SEIP 143 #define MIE_HEIE MIP_HEIP 144 #define MIE_MEIE MIP_MEIP 145 146 /* === Nuclei custom CSR bit mask === */ 147 148 #define WFE_WFE (0x1) 149 #define TXEVT_TXEVT (0x1) 150 #define SLEEPVALUE_SLEEPVALUE (0x1) 151 152 #define MCOUNTINHIBIT_IR (1<<2) 153 #define MCOUNTINHIBIT_CY (1<<0) 154 155 #define MILM_CTL_ILM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) 156 #define MILM_CTL_ILM_EN (1<<0) 157 158 #define MDLM_CTL_DLM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) 159 #define MDLM_CTL_DLM_EN (1<<0) 160 161 #define MSUBM_PTYP (0x3<<8) 162 #define MSUBM_TYP (0x3<<6) 163 164 #define MDCAUSE_MDCAUSE (0x3) 165 166 #define MMISC_CTL_NMI_CAUSE_FFF (1<<9) 167 #define MMISC_CTL_MISALIGN (1<<6) 168 #define MMISC_CTL_BPU (1<<3) 169 170 #define MCACHE_CTL_IC_EN (1<<0) 171 #define MCACHE_CTL_IC_SCPD_MOD (1<<1) 172 #define MCACHE_CTL_DC_EN (1<<16) 173 174 #define MTVT2_MTVT2EN (1<<0) 175 #define MTVT2_COMMON_CODE_ENTRY (((1ULL<<((__riscv_xlen)-2))-1)<<2) 176 177 #define MCFG_INFO_TEE (1<<0) 178 #define MCFG_INFO_ECC (1<<1) 179 #define MCFG_INFO_CLIC (1<<2) 180 #define MCFG_INFO_PLIC (1<<3) 181 #define MCFG_INFO_FIO (1<<4) 182 #define MCFG_INFO_PPI (1<<5) 183 #define MCFG_INFO_NICE (1<<6) 184 #define MCFG_INFO_ILM (1<<7) 185 #define MCFG_INFO_DLM (1<<8) 186 #define MCFG_INFO_ICACHE (1<<9) 187 #define MCFG_INFO_DCACHE (1<<10) 188 189 #define MICFG_IC_SET (0xF<<0) 190 #define MICFG_IC_WAY (0x7<<4) 191 #define MICFG_IC_LSIZE (0x7<<7) 192 #define MICFG_ILM_SIZE (0x1F<<16) 193 #define MICFG_ILM_XONLY (1<<21) 194 195 #define MDCFG_DC_SET (0xF<<0) 196 #define MDCFG_DC_WAY (0x7<<4) 197 #define MDCFG_DC_LSIZE (0x7<<7) 198 #define MDCFG_DLM_SIZE (0x1F<<16) 199 200 #define MPPICFG_INFO_PPI_SIZE (0x1F<<1) 201 #define MPPICFG_INFO_PPI_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) 202 203 #define MFIOCFG_INFO_FIO_SIZE (0x1F<<1) 204 #define MFIOCFG_INFO_FIO_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10) 205 206 #define SIP_SSIP MIP_SSIP 207 #define SIP_STIP MIP_STIP 208 209 #define PRV_U 0 210 #define PRV_S 1 211 #define PRV_H 2 212 #define PRV_M 3 213 214 #define VM_MBARE 0 215 #define VM_MBB 1 216 #define VM_MBBID 2 217 #define VM_SV32 8 218 #define VM_SV39 9 219 #define VM_SV48 10 220 221 #define IRQ_S_SOFT 1 222 #define IRQ_H_SOFT 2 223 #define IRQ_M_SOFT 3 224 #define IRQ_S_TIMER 5 225 #define IRQ_H_TIMER 6 226 #define IRQ_M_TIMER 7 227 #define IRQ_S_EXT 9 228 #define IRQ_H_EXT 10 229 #define IRQ_M_EXT 11 230 #define IRQ_COP 12 231 #define IRQ_HOST 13 232 233 #define DEFAULT_RSTVEC 0x00001000 234 #define DEFAULT_NMIVEC 0x00001004 235 #define DEFAULT_MTVEC 0x00001010 236 #define CONFIG_STRING_ADDR 0x0000100C 237 #define EXT_IO_BASE 0x40000000 238 #define DRAM_BASE 0x80000000 239 240 /* === FPU FRM Rounding Mode === */ 241 /** FPU Round to Nearest, ties to Even*/ 242 #define FRM_RNDMODE_RNE 0x0 243 /** FPU Round Towards Zero */ 244 #define FRM_RNDMODE_RTZ 0x1 245 /** FPU Round Down (towards -inf) */ 246 #define FRM_RNDMODE_RDN 0x2 247 /** FPU Round Up (towards +inf) */ 248 #define FRM_RNDMODE_RUP 0x3 249 /** FPU Round to nearest, ties to Max Magnitude */ 250 #define FRM_RNDMODE_RMM 0x4 251 /** 252 * In instruction's rm, selects dynamic rounding mode. 253 * In Rounding Mode register, Invalid */ 254 #define FRM_RNDMODE_DYN 0x7 255 256 /* === FPU FFLAGS Accrued Exceptions === */ 257 /** FPU Inexact */ 258 #define FFLAGS_AE_NX (1<<0) 259 /** FPU Underflow */ 260 #define FFLAGS_AE_UF (1<<1) 261 /** FPU Overflow */ 262 #define FFLAGS_AE_OF (1<<2) 263 /** FPU Divide by Zero */ 264 #define FFLAGS_AE_DZ (1<<3) 265 /** FPU Invalid Operation */ 266 #define FFLAGS_AE_NV (1<<4) 267 268 /** Floating Point Register f0-f31, eg. f0 -> FREG(0) */ 269 #define FREG(idx) f##idx 270 271 272 /* === PMP CFG Bits === */ 273 #define PMP_R 0x01 274 #define PMP_W 0x02 275 #define PMP_X 0x04 276 #define PMP_A 0x18 277 #define PMP_A_TOR 0x08 278 #define PMP_A_NA4 0x10 279 #define PMP_A_NAPOT 0x18 280 #define PMP_L 0x80 281 282 #define PMP_SHIFT 2 283 #define PMP_COUNT 16 284 285 // page table entry (PTE) fields 286 #define PTE_V 0x001 // Valid 287 #define PTE_R 0x002 // Read 288 #define PTE_W 0x004 // Write 289 #define PTE_X 0x008 // Execute 290 #define PTE_U 0x010 // User 291 #define PTE_G 0x020 // Global 292 #define PTE_A 0x040 // Accessed 293 #define PTE_D 0x080 // Dirty 294 #define PTE_SOFT 0x300 // Reserved for Software 295 296 #define PTE_PPN_SHIFT 10 297 298 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) 299 300 #ifdef __riscv 301 302 #ifdef __riscv64 303 # define MSTATUS_SD MSTATUS64_SD 304 # define SSTATUS_SD SSTATUS64_SD 305 # define RISCV_PGLEVEL_BITS 9 306 #else 307 # define MSTATUS_SD MSTATUS32_SD 308 # define SSTATUS_SD SSTATUS32_SD 309 # define RISCV_PGLEVEL_BITS 10 310 #endif /* __riscv64 */ 311 312 #define RISCV_PGSHIFT 12 313 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) 314 315 #endif /* __riscv */ 316 317 #define DOWNLOAD_MODE_FLASHXIP 0 318 #define DOWNLOAD_MODE_FLASH 1 319 #define DOWNLOAD_MODE_ILM 2 320 #define DOWNLOAD_MODE_DDR 3 321 322 /** 323 * \defgroup NMSIS_Core_CSR_Registers Core CSR Registers 324 * \ingroup NMSIS_Core 325 * \brief NMSIS Core CSR Register Definitions 326 * \details 327 * 328 * The following macros are used for CSR Register Definitions. 329 * @{ 330 */ 331 /* === Standard RISC-V CSR Registers === */ 332 #define CSR_USTATUS 0x0 333 #define CSR_FFLAGS 0x1 334 #define CSR_FRM 0x2 335 #define CSR_FCSR 0x3 336 #define CSR_CYCLE 0xc00 337 #define CSR_TIME 0xc01 338 #define CSR_INSTRET 0xc02 339 #define CSR_HPMCOUNTER3 0xc03 340 #define CSR_HPMCOUNTER4 0xc04 341 #define CSR_HPMCOUNTER5 0xc05 342 #define CSR_HPMCOUNTER6 0xc06 343 #define CSR_HPMCOUNTER7 0xc07 344 #define CSR_HPMCOUNTER8 0xc08 345 #define CSR_HPMCOUNTER9 0xc09 346 #define CSR_HPMCOUNTER10 0xc0a 347 #define CSR_HPMCOUNTER11 0xc0b 348 #define CSR_HPMCOUNTER12 0xc0c 349 #define CSR_HPMCOUNTER13 0xc0d 350 #define CSR_HPMCOUNTER14 0xc0e 351 #define CSR_HPMCOUNTER15 0xc0f 352 #define CSR_HPMCOUNTER16 0xc10 353 #define CSR_HPMCOUNTER17 0xc11 354 #define CSR_HPMCOUNTER18 0xc12 355 #define CSR_HPMCOUNTER19 0xc13 356 #define CSR_HPMCOUNTER20 0xc14 357 #define CSR_HPMCOUNTER21 0xc15 358 #define CSR_HPMCOUNTER22 0xc16 359 #define CSR_HPMCOUNTER23 0xc17 360 #define CSR_HPMCOUNTER24 0xc18 361 #define CSR_HPMCOUNTER25 0xc19 362 #define CSR_HPMCOUNTER26 0xc1a 363 #define CSR_HPMCOUNTER27 0xc1b 364 #define CSR_HPMCOUNTER28 0xc1c 365 #define CSR_HPMCOUNTER29 0xc1d 366 #define CSR_HPMCOUNTER30 0xc1e 367 #define CSR_HPMCOUNTER31 0xc1f 368 #define CSR_SSTATUS 0x100 369 #define CSR_SIE 0x104 370 #define CSR_STVEC 0x105 371 #define CSR_SSCRATCH 0x140 372 #define CSR_SEPC 0x141 373 #define CSR_SCAUSE 0x142 374 #define CSR_SBADADDR 0x143 375 #define CSR_SIP 0x144 376 #define CSR_SPTBR 0x180 377 #define CSR_MSTATUS 0x300 378 #define CSR_MISA 0x301 379 #define CSR_MEDELEG 0x302 380 #define CSR_MIDELEG 0x303 381 #define CSR_MIE 0x304 382 #define CSR_MTVEC 0x305 383 #define CSR_MCOUNTEREN 0x306 384 #define CSR_MSCRATCH 0x340 385 #define CSR_MEPC 0x341 386 #define CSR_MCAUSE 0x342 387 #define CSR_MBADADDR 0x343 388 #define CSR_MTVAL 0x343 389 #define CSR_MIP 0x344 390 #define CSR_PMPCFG0 0x3a0 391 #define CSR_PMPCFG1 0x3a1 392 #define CSR_PMPCFG2 0x3a2 393 #define CSR_PMPCFG3 0x3a3 394 #define CSR_PMPADDR0 0x3b0 395 #define CSR_PMPADDR1 0x3b1 396 #define CSR_PMPADDR2 0x3b2 397 #define CSR_PMPADDR3 0x3b3 398 #define CSR_PMPADDR4 0x3b4 399 #define CSR_PMPADDR5 0x3b5 400 #define CSR_PMPADDR6 0x3b6 401 #define CSR_PMPADDR7 0x3b7 402 #define CSR_PMPADDR8 0x3b8 403 #define CSR_PMPADDR9 0x3b9 404 #define CSR_PMPADDR10 0x3ba 405 #define CSR_PMPADDR11 0x3bb 406 #define CSR_PMPADDR12 0x3bc 407 #define CSR_PMPADDR13 0x3bd 408 #define CSR_PMPADDR14 0x3be 409 #define CSR_PMPADDR15 0x3bf 410 #define CSR_TSELECT 0x7a0 411 #define CSR_TDATA1 0x7a1 412 #define CSR_TDATA2 0x7a2 413 #define CSR_TDATA3 0x7a3 414 #define CSR_DCSR 0x7b0 415 #define CSR_DPC 0x7b1 416 #define CSR_DSCRATCH 0x7b2 417 #define CSR_MCYCLE 0xb00 418 #define CSR_MINSTRET 0xb02 419 #define CSR_MHPMCOUNTER3 0xb03 420 #define CSR_MHPMCOUNTER4 0xb04 421 #define CSR_MHPMCOUNTER5 0xb05 422 #define CSR_MHPMCOUNTER6 0xb06 423 #define CSR_MHPMCOUNTER7 0xb07 424 #define CSR_MHPMCOUNTER8 0xb08 425 #define CSR_MHPMCOUNTER9 0xb09 426 #define CSR_MHPMCOUNTER10 0xb0a 427 #define CSR_MHPMCOUNTER11 0xb0b 428 #define CSR_MHPMCOUNTER12 0xb0c 429 #define CSR_MHPMCOUNTER13 0xb0d 430 #define CSR_MHPMCOUNTER14 0xb0e 431 #define CSR_MHPMCOUNTER15 0xb0f 432 #define CSR_MHPMCOUNTER16 0xb10 433 #define CSR_MHPMCOUNTER17 0xb11 434 #define CSR_MHPMCOUNTER18 0xb12 435 #define CSR_MHPMCOUNTER19 0xb13 436 #define CSR_MHPMCOUNTER20 0xb14 437 #define CSR_MHPMCOUNTER21 0xb15 438 #define CSR_MHPMCOUNTER22 0xb16 439 #define CSR_MHPMCOUNTER23 0xb17 440 #define CSR_MHPMCOUNTER24 0xb18 441 #define CSR_MHPMCOUNTER25 0xb19 442 #define CSR_MHPMCOUNTER26 0xb1a 443 #define CSR_MHPMCOUNTER27 0xb1b 444 #define CSR_MHPMCOUNTER28 0xb1c 445 #define CSR_MHPMCOUNTER29 0xb1d 446 #define CSR_MHPMCOUNTER30 0xb1e 447 #define CSR_MHPMCOUNTER31 0xb1f 448 #define CSR_MUCOUNTEREN 0x320 449 #define CSR_MSCOUNTEREN 0x321 450 #define CSR_MHPMEVENT3 0x323 451 #define CSR_MHPMEVENT4 0x324 452 #define CSR_MHPMEVENT5 0x325 453 #define CSR_MHPMEVENT6 0x326 454 #define CSR_MHPMEVENT7 0x327 455 #define CSR_MHPMEVENT8 0x328 456 #define CSR_MHPMEVENT9 0x329 457 #define CSR_MHPMEVENT10 0x32a 458 #define CSR_MHPMEVENT11 0x32b 459 #define CSR_MHPMEVENT12 0x32c 460 #define CSR_MHPMEVENT13 0x32d 461 #define CSR_MHPMEVENT14 0x32e 462 #define CSR_MHPMEVENT15 0x32f 463 #define CSR_MHPMEVENT16 0x330 464 #define CSR_MHPMEVENT17 0x331 465 #define CSR_MHPMEVENT18 0x332 466 #define CSR_MHPMEVENT19 0x333 467 #define CSR_MHPMEVENT20 0x334 468 #define CSR_MHPMEVENT21 0x335 469 #define CSR_MHPMEVENT22 0x336 470 #define CSR_MHPMEVENT23 0x337 471 #define CSR_MHPMEVENT24 0x338 472 #define CSR_MHPMEVENT25 0x339 473 #define CSR_MHPMEVENT26 0x33a 474 #define CSR_MHPMEVENT27 0x33b 475 #define CSR_MHPMEVENT28 0x33c 476 #define CSR_MHPMEVENT29 0x33d 477 #define CSR_MHPMEVENT30 0x33e 478 #define CSR_MHPMEVENT31 0x33f 479 #define CSR_MVENDORID 0xf11 480 #define CSR_MARCHID 0xf12 481 #define CSR_MIMPID 0xf13 482 #define CSR_MHARTID 0xf14 483 #define CSR_CYCLEH 0xc80 484 #define CSR_TIMEH 0xc81 485 #define CSR_INSTRETH 0xc82 486 #define CSR_HPMCOUNTER3H 0xc83 487 #define CSR_HPMCOUNTER4H 0xc84 488 #define CSR_HPMCOUNTER5H 0xc85 489 #define CSR_HPMCOUNTER6H 0xc86 490 #define CSR_HPMCOUNTER7H 0xc87 491 #define CSR_HPMCOUNTER8H 0xc88 492 #define CSR_HPMCOUNTER9H 0xc89 493 #define CSR_HPMCOUNTER10H 0xc8a 494 #define CSR_HPMCOUNTER11H 0xc8b 495 #define CSR_HPMCOUNTER12H 0xc8c 496 #define CSR_HPMCOUNTER13H 0xc8d 497 #define CSR_HPMCOUNTER14H 0xc8e 498 #define CSR_HPMCOUNTER15H 0xc8f 499 #define CSR_HPMCOUNTER16H 0xc90 500 #define CSR_HPMCOUNTER17H 0xc91 501 #define CSR_HPMCOUNTER18H 0xc92 502 #define CSR_HPMCOUNTER19H 0xc93 503 #define CSR_HPMCOUNTER20H 0xc94 504 #define CSR_HPMCOUNTER21H 0xc95 505 #define CSR_HPMCOUNTER22H 0xc96 506 #define CSR_HPMCOUNTER23H 0xc97 507 #define CSR_HPMCOUNTER24H 0xc98 508 #define CSR_HPMCOUNTER25H 0xc99 509 #define CSR_HPMCOUNTER26H 0xc9a 510 #define CSR_HPMCOUNTER27H 0xc9b 511 #define CSR_HPMCOUNTER28H 0xc9c 512 #define CSR_HPMCOUNTER29H 0xc9d 513 #define CSR_HPMCOUNTER30H 0xc9e 514 #define CSR_HPMCOUNTER31H 0xc9f 515 #define CSR_MCYCLEH 0xb80 516 #define CSR_MINSTRETH 0xb82 517 #define CSR_MHPMCOUNTER3H 0xb83 518 #define CSR_MHPMCOUNTER4H 0xb84 519 #define CSR_MHPMCOUNTER5H 0xb85 520 #define CSR_MHPMCOUNTER6H 0xb86 521 #define CSR_MHPMCOUNTER7H 0xb87 522 #define CSR_MHPMCOUNTER8H 0xb88 523 #define CSR_MHPMCOUNTER9H 0xb89 524 #define CSR_MHPMCOUNTER10H 0xb8a 525 #define CSR_MHPMCOUNTER11H 0xb8b 526 #define CSR_MHPMCOUNTER12H 0xb8c 527 #define CSR_MHPMCOUNTER13H 0xb8d 528 #define CSR_MHPMCOUNTER14H 0xb8e 529 #define CSR_MHPMCOUNTER15H 0xb8f 530 #define CSR_MHPMCOUNTER16H 0xb90 531 #define CSR_MHPMCOUNTER17H 0xb91 532 #define CSR_MHPMCOUNTER18H 0xb92 533 #define CSR_MHPMCOUNTER19H 0xb93 534 #define CSR_MHPMCOUNTER20H 0xb94 535 #define CSR_MHPMCOUNTER21H 0xb95 536 #define CSR_MHPMCOUNTER22H 0xb96 537 #define CSR_MHPMCOUNTER23H 0xb97 538 #define CSR_MHPMCOUNTER24H 0xb98 539 #define CSR_MHPMCOUNTER25H 0xb99 540 #define CSR_MHPMCOUNTER26H 0xb9a 541 #define CSR_MHPMCOUNTER27H 0xb9b 542 #define CSR_MHPMCOUNTER28H 0xb9c 543 #define CSR_MHPMCOUNTER29H 0xb9d 544 #define CSR_MHPMCOUNTER30H 0xb9e 545 #define CSR_MHPMCOUNTER31H 0xb9f 546 547 /* === CLIC CSR Registers === */ 548 #define CSR_MTVT 0x307 549 #define CSR_MNXTI 0x345 550 #define CSR_MINTSTATUS 0x346 551 #define CSR_MSCRATCHCSW 0x348 552 #define CSR_MSCRATCHCSWL 0x349 553 #define CSR_MCLICBASE 0x350 554 555 /* === Nuclei custom CSR Registers === */ 556 #define CSR_MCOUNTINHIBIT 0x320 557 #define CSR_MILM_CTL 0x7C0 558 #define CSR_MDLM_CTL 0x7C1 559 #define CSR_MNVEC 0x7C3 560 #define CSR_MSUBM 0x7C4 561 #define CSR_MDCAUSE 0x7C9 562 #define CSR_MCACHE_CTL 0x7CA 563 #define CSR_MMISC_CTL 0x7D0 564 #define CSR_MSAVESTATUS 0x7D6 565 #define CSR_MSAVEEPC1 0x7D7 566 #define CSR_MSAVECAUSE1 0x7D8 567 #define CSR_MSAVEEPC2 0x7D9 568 #define CSR_MSAVECAUSE2 0x7DA 569 #define CSR_MSAVEDCAUSE1 0x7DB 570 #define CSR_MSAVEDCAUSE2 0x7DC 571 #define CSR_PUSHMSUBM 0x7EB 572 #define CSR_MTVT2 0x7EC 573 #define CSR_JALMNXTI 0x7ED 574 #define CSR_PUSHMCAUSE 0x7EE 575 #define CSR_PUSHMEPC 0x7EF 576 #define CSR_MPPICFG_INFO 0x7F0 577 #define CSR_MFIOCFG_INFO 0x7F1 578 #define CSR_SLEEPVALUE 0x811 579 #define CSR_TXEVT 0x812 580 #define CSR_WFE 0x810 581 #define CSR_MICFG_INFO 0xFC0 582 #define CSR_MDCFG_INFO 0xFC1 583 #define CSR_MCFG_INFO 0xFC2 584 585 /** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Registers **/ 586 587 /* Exception Code in MCAUSE CSR */ 588 #define CAUSE_MISALIGNED_FETCH 0x0 589 #define CAUSE_FAULT_FETCH 0x1 590 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 591 #define CAUSE_BREAKPOINT 0x3 592 #define CAUSE_MISALIGNED_LOAD 0x4 593 #define CAUSE_FAULT_LOAD 0x5 594 #define CAUSE_MISALIGNED_STORE 0x6 595 #define CAUSE_FAULT_STORE 0x7 596 #define CAUSE_USER_ECALL 0x8 597 #define CAUSE_SUPERVISOR_ECALL 0x9 598 #define CAUSE_HYPERVISOR_ECALL 0xa 599 #define CAUSE_MACHINE_ECALL 0xb 600 601 /* Exception Subcode in MDCAUSE CSR */ 602 #define DCAUSE_FAULT_FETCH_PMP 0x1 603 #define DCAUSE_FAULT_FETCH_INST 0x2 604 605 #define DCAUSE_FAULT_LOAD_PMP 0x1 606 #define DCAUSE_FAULT_LOAD_INST 0x2 607 #define DCAUSE_FAULT_LOAD_NICE 0x3 608 609 #define DCAUSE_FAULT_STORE_PMP 0x1 610 #define DCAUSE_FAULT_STORE_INST 0x2 611 612 /** @} */ /** End of Doxygen Group NMSIS_Core_CSR_Encoding **/ 613 614 #ifdef __cplusplus 615 } 616 #endif 617 #endif /* __RISCV_ENCODING_H__ */ 618