1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #ifndef __HCLGE_DEBUGFS_H 5 #define __HCLGE_DEBUGFS_H 6 7 #include <linux/etherdevice.h> 8 #include "hclge_cmd.h" 9 10 #define HCLGE_DBG_BUF_LEN 256 11 #define HCLGE_DBG_MNG_TBL_MAX 64 12 13 #define HCLGE_DBG_MNG_VLAN_MASK_B BIT(0) 14 #define HCLGE_DBG_MNG_MAC_MASK_B BIT(1) 15 #define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2) 16 #define HCLGE_DBG_MNG_E_TYPE_B BIT(11) 17 #define HCLGE_DBG_MNG_DROP_B BIT(13) 18 #define HCLGE_DBG_MNG_VLAN_TAG 0x0FFF 19 #define HCLGE_DBG_MNG_PF_ID 0x0007 20 #define HCLGE_DBG_MNG_VF_ID 0x00FF 21 22 /* Get DFX BD number offset */ 23 #define HCLGE_DBG_DFX_BIOS_OFFSET 1 24 #define HCLGE_DBG_DFX_SSU_0_OFFSET 2 25 #define HCLGE_DBG_DFX_SSU_1_OFFSET 3 26 #define HCLGE_DBG_DFX_IGU_OFFSET 4 27 #define HCLGE_DBG_DFX_RPU_0_OFFSET 5 28 29 #define HCLGE_DBG_DFX_RPU_1_OFFSET 6 30 #define HCLGE_DBG_DFX_NCSI_OFFSET 7 31 #define HCLGE_DBG_DFX_RTC_OFFSET 8 32 #define HCLGE_DBG_DFX_PPP_OFFSET 9 33 #define HCLGE_DBG_DFX_RCB_OFFSET 10 34 #define HCLGE_DBG_DFX_TQP_OFFSET 11 35 36 #define HCLGE_DBG_DFX_SSU_2_OFFSET 12 37 38 struct hclge_qos_pri_map_cmd { 39 u8 pri0_tc : 4, 40 pri1_tc : 4; 41 u8 pri2_tc : 4, 42 pri3_tc : 4; 43 u8 pri4_tc : 4, 44 pri5_tc : 4; 45 u8 pri6_tc : 4, 46 pri7_tc : 4; 47 u8 vlan_pri : 4, 48 rev : 4; 49 }; 50 51 struct hclge_dbg_bitmap_cmd { 52 union { 53 u8 bitmap; 54 struct { 55 u8 bit0 : 1, 56 bit1 : 1, 57 bit2 : 1, 58 bit3 : 1, 59 bit4 : 1, 60 bit5 : 1, 61 bit6 : 1, 62 bit7 : 1; 63 }; 64 }; 65 }; 66 67 struct hclge_dbg_reg_common_msg { 68 int msg_num; 69 int offset; 70 enum hclge_opcode_type cmd; 71 }; 72 73 #define HCLGE_DBG_MAX_DFX_MSG_LEN 60 74 struct hclge_dbg_dfx_message { 75 int flag; 76 char message[HCLGE_DBG_MAX_DFX_MSG_LEN]; 77 }; 78 79 #define HCLGE_DBG_MAC_REG_TYPE_LEN 32 80 struct hclge_dbg_reg_type_info { 81 const char *reg_type; 82 const struct hclge_dbg_dfx_message *dfx_msg; 83 struct hclge_dbg_reg_common_msg reg_msg; 84 }; 85 86 static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = { 87 {false, "Reserved"}, 88 {true, "BP_CPU_STATE"}, 89 {true, "DFX_MSIX_INFO_NIC_0"}, 90 {true, "DFX_MSIX_INFO_NIC_1"}, 91 {true, "DFX_MSIX_INFO_NIC_2"}, 92 {true, "DFX_MSIX_INFO_NIC_3"}, 93 94 {true, "DFX_MSIX_INFO_ROC_0"}, 95 {true, "DFX_MSIX_INFO_ROC_1"}, 96 {true, "DFX_MSIX_INFO_ROC_2"}, 97 {true, "DFX_MSIX_INFO_ROC_3"}, 98 {false, "Reserved"}, 99 {false, "Reserved"}, 100 }; 101 102 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = { 103 {false, "Reserved"}, 104 {true, "SSU_ETS_PORT_STATUS"}, 105 {true, "SSU_ETS_TCG_STATUS"}, 106 {false, "Reserved"}, 107 {false, "Reserved"}, 108 {true, "SSU_BP_STATUS_0"}, 109 110 {true, "SSU_BP_STATUS_1"}, 111 {true, "SSU_BP_STATUS_2"}, 112 {true, "SSU_BP_STATUS_3"}, 113 {true, "SSU_BP_STATUS_4"}, 114 {true, "SSU_BP_STATUS_5"}, 115 {true, "SSU_MAC_TX_PFC_IND"}, 116 117 {true, "MAC_SSU_RX_PFC_IND"}, 118 {true, "BTMP_AGEING_ST_B0"}, 119 {true, "BTMP_AGEING_ST_B1"}, 120 {true, "BTMP_AGEING_ST_B2"}, 121 {false, "Reserved"}, 122 {false, "Reserved"}, 123 124 {true, "FULL_DROP_NUM"}, 125 {true, "PART_DROP_NUM"}, 126 {true, "PPP_KEY_DROP_NUM"}, 127 {true, "PPP_RLT_DROP_NUM"}, 128 {true, "LO_PRI_UNICAST_RLT_DROP_NUM"}, 129 {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"}, 130 131 {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"}, 132 {true, "NCSI_PACKET_CURR_BUFFER_CNT"}, 133 {true, "BTMP_AGEING_RLS_CNT_BANK0"}, 134 {true, "BTMP_AGEING_RLS_CNT_BANK1"}, 135 {true, "BTMP_AGEING_RLS_CNT_BANK2"}, 136 {true, "SSU_MB_RD_RLT_DROP_CNT"}, 137 138 {true, "SSU_PPP_MAC_KEY_NUM_L"}, 139 {true, "SSU_PPP_MAC_KEY_NUM_H"}, 140 {true, "SSU_PPP_HOST_KEY_NUM_L"}, 141 {true, "SSU_PPP_HOST_KEY_NUM_H"}, 142 {true, "PPP_SSU_MAC_RLT_NUM_L"}, 143 {true, "PPP_SSU_MAC_RLT_NUM_H"}, 144 145 {true, "PPP_SSU_HOST_RLT_NUM_L"}, 146 {true, "PPP_SSU_HOST_RLT_NUM_H"}, 147 {true, "NCSI_RX_PACKET_IN_CNT_L"}, 148 {true, "NCSI_RX_PACKET_IN_CNT_H"}, 149 {true, "NCSI_TX_PACKET_OUT_CNT_L"}, 150 {true, "NCSI_TX_PACKET_OUT_CNT_H"}, 151 152 {true, "SSU_KEY_DROP_NUM"}, 153 {true, "MB_UNCOPY_NUM"}, 154 {true, "RX_OQ_DROP_PKT_CNT"}, 155 {true, "TX_OQ_DROP_PKT_CNT"}, 156 {true, "BANK_UNBALANCE_DROP_CNT"}, 157 {true, "BANK_UNBALANCE_RX_DROP_CNT"}, 158 159 {true, "NIC_L2_ERR_DROP_PKT_CNT"}, 160 {true, "ROC_L2_ERR_DROP_PKT_CNT"}, 161 {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"}, 162 {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"}, 163 {true, "RX_OQ_GLB_DROP_PKT_CNT"}, 164 {false, "Reserved"}, 165 166 {true, "LO_PRI_UNICAST_CUR_CNT"}, 167 {true, "HI_PRI_MULTICAST_CUR_CNT"}, 168 {true, "LO_PRI_MULTICAST_CUR_CNT"}, 169 {false, "Reserved"}, 170 {false, "Reserved"}, 171 {false, "Reserved"}, 172 }; 173 174 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = { 175 {true, "prt_id"}, 176 {true, "PACKET_TC_CURR_BUFFER_CNT_0"}, 177 {true, "PACKET_TC_CURR_BUFFER_CNT_1"}, 178 {true, "PACKET_TC_CURR_BUFFER_CNT_2"}, 179 {true, "PACKET_TC_CURR_BUFFER_CNT_3"}, 180 {true, "PACKET_TC_CURR_BUFFER_CNT_4"}, 181 182 {true, "PACKET_TC_CURR_BUFFER_CNT_5"}, 183 {true, "PACKET_TC_CURR_BUFFER_CNT_6"}, 184 {true, "PACKET_TC_CURR_BUFFER_CNT_7"}, 185 {true, "PACKET_CURR_BUFFER_CNT"}, 186 {false, "Reserved"}, 187 {false, "Reserved"}, 188 189 {true, "RX_PACKET_IN_CNT_L"}, 190 {true, "RX_PACKET_IN_CNT_H"}, 191 {true, "RX_PACKET_OUT_CNT_L"}, 192 {true, "RX_PACKET_OUT_CNT_H"}, 193 {true, "TX_PACKET_IN_CNT_L"}, 194 {true, "TX_PACKET_IN_CNT_H"}, 195 196 {true, "TX_PACKET_OUT_CNT_L"}, 197 {true, "TX_PACKET_OUT_CNT_H"}, 198 {true, "ROC_RX_PACKET_IN_CNT_L"}, 199 {true, "ROC_RX_PACKET_IN_CNT_H"}, 200 {true, "ROC_TX_PACKET_OUT_CNT_L"}, 201 {true, "ROC_TX_PACKET_OUT_CNT_H"}, 202 203 {true, "RX_PACKET_TC_IN_CNT_0_L"}, 204 {true, "RX_PACKET_TC_IN_CNT_0_H"}, 205 {true, "RX_PACKET_TC_IN_CNT_1_L"}, 206 {true, "RX_PACKET_TC_IN_CNT_1_H"}, 207 {true, "RX_PACKET_TC_IN_CNT_2_L"}, 208 {true, "RX_PACKET_TC_IN_CNT_2_H"}, 209 210 {true, "RX_PACKET_TC_IN_CNT_3_L"}, 211 {true, "RX_PACKET_TC_IN_CNT_3_H"}, 212 {true, "RX_PACKET_TC_IN_CNT_4_L"}, 213 {true, "RX_PACKET_TC_IN_CNT_4_H"}, 214 {true, "RX_PACKET_TC_IN_CNT_5_L"}, 215 {true, "RX_PACKET_TC_IN_CNT_5_H"}, 216 217 {true, "RX_PACKET_TC_IN_CNT_6_L"}, 218 {true, "RX_PACKET_TC_IN_CNT_6_H"}, 219 {true, "RX_PACKET_TC_IN_CNT_7_L"}, 220 {true, "RX_PACKET_TC_IN_CNT_7_H"}, 221 {true, "RX_PACKET_TC_OUT_CNT_0_L"}, 222 {true, "RX_PACKET_TC_OUT_CNT_0_H"}, 223 224 {true, "RX_PACKET_TC_OUT_CNT_1_L"}, 225 {true, "RX_PACKET_TC_OUT_CNT_1_H"}, 226 {true, "RX_PACKET_TC_OUT_CNT_2_L"}, 227 {true, "RX_PACKET_TC_OUT_CNT_2_H"}, 228 {true, "RX_PACKET_TC_OUT_CNT_3_L"}, 229 {true, "RX_PACKET_TC_OUT_CNT_3_H"}, 230 231 {true, "RX_PACKET_TC_OUT_CNT_4_L"}, 232 {true, "RX_PACKET_TC_OUT_CNT_4_H"}, 233 {true, "RX_PACKET_TC_OUT_CNT_5_L"}, 234 {true, "RX_PACKET_TC_OUT_CNT_5_H"}, 235 {true, "RX_PACKET_TC_OUT_CNT_6_L"}, 236 {true, "RX_PACKET_TC_OUT_CNT_6_H"}, 237 238 {true, "RX_PACKET_TC_OUT_CNT_7_L"}, 239 {true, "RX_PACKET_TC_OUT_CNT_7_H"}, 240 {true, "TX_PACKET_TC_IN_CNT_0_L"}, 241 {true, "TX_PACKET_TC_IN_CNT_0_H"}, 242 {true, "TX_PACKET_TC_IN_CNT_1_L"}, 243 {true, "TX_PACKET_TC_IN_CNT_1_H"}, 244 245 {true, "TX_PACKET_TC_IN_CNT_2_L"}, 246 {true, "TX_PACKET_TC_IN_CNT_2_H"}, 247 {true, "TX_PACKET_TC_IN_CNT_3_L"}, 248 {true, "TX_PACKET_TC_IN_CNT_3_H"}, 249 {true, "TX_PACKET_TC_IN_CNT_4_L"}, 250 {true, "TX_PACKET_TC_IN_CNT_4_H"}, 251 252 {true, "TX_PACKET_TC_IN_CNT_5_L"}, 253 {true, "TX_PACKET_TC_IN_CNT_5_H"}, 254 {true, "TX_PACKET_TC_IN_CNT_6_L"}, 255 {true, "TX_PACKET_TC_IN_CNT_6_H"}, 256 {true, "TX_PACKET_TC_IN_CNT_7_L"}, 257 {true, "TX_PACKET_TC_IN_CNT_7_H"}, 258 259 {true, "TX_PACKET_TC_OUT_CNT_0_L"}, 260 {true, "TX_PACKET_TC_OUT_CNT_0_H"}, 261 {true, "TX_PACKET_TC_OUT_CNT_1_L"}, 262 {true, "TX_PACKET_TC_OUT_CNT_1_H"}, 263 {true, "TX_PACKET_TC_OUT_CNT_2_L"}, 264 {true, "TX_PACKET_TC_OUT_CNT_2_H"}, 265 266 {true, "TX_PACKET_TC_OUT_CNT_3_L"}, 267 {true, "TX_PACKET_TC_OUT_CNT_3_H"}, 268 {true, "TX_PACKET_TC_OUT_CNT_4_L"}, 269 {true, "TX_PACKET_TC_OUT_CNT_4_H"}, 270 {true, "TX_PACKET_TC_OUT_CNT_5_L"}, 271 {true, "TX_PACKET_TC_OUT_CNT_5_H"}, 272 273 {true, "TX_PACKET_TC_OUT_CNT_6_L"}, 274 {true, "TX_PACKET_TC_OUT_CNT_6_H"}, 275 {true, "TX_PACKET_TC_OUT_CNT_7_L"}, 276 {true, "TX_PACKET_TC_OUT_CNT_7_H"}, 277 {false, "Reserved"}, 278 {false, "Reserved"}, 279 }; 280 281 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = { 282 {true, "OQ_INDEX"}, 283 {true, "QUEUE_CNT"}, 284 {false, "Reserved"}, 285 {false, "Reserved"}, 286 {false, "Reserved"}, 287 {false, "Reserved"}, 288 }; 289 290 static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = { 291 {true, "prt_id"}, 292 {true, "IGU_RX_ERR_PKT"}, 293 {true, "IGU_RX_NO_SOF_PKT"}, 294 {true, "EGU_TX_1588_SHORT_PKT"}, 295 {true, "EGU_TX_1588_PKT"}, 296 {true, "EGU_TX_ERR_PKT"}, 297 298 {true, "IGU_RX_OUT_L2_PKT"}, 299 {true, "IGU_RX_OUT_L3_PKT"}, 300 {true, "IGU_RX_OUT_L4_PKT"}, 301 {true, "IGU_RX_IN_L2_PKT"}, 302 {true, "IGU_RX_IN_L3_PKT"}, 303 {true, "IGU_RX_IN_L4_PKT"}, 304 305 {true, "IGU_RX_EL3E_PKT"}, 306 {true, "IGU_RX_EL4E_PKT"}, 307 {true, "IGU_RX_L3E_PKT"}, 308 {true, "IGU_RX_L4E_PKT"}, 309 {true, "IGU_RX_ROCEE_PKT"}, 310 {true, "IGU_RX_OUT_UDP0_PKT"}, 311 312 {true, "IGU_RX_IN_UDP0_PKT"}, 313 {false, "Reserved"}, 314 {false, "Reserved"}, 315 {false, "Reserved"}, 316 {false, "Reserved"}, 317 {false, "Reserved"}, 318 319 {true, "IGU_RX_OVERSIZE_PKT_L"}, 320 {true, "IGU_RX_OVERSIZE_PKT_H"}, 321 {true, "IGU_RX_UNDERSIZE_PKT_L"}, 322 {true, "IGU_RX_UNDERSIZE_PKT_H"}, 323 {true, "IGU_RX_OUT_ALL_PKT_L"}, 324 {true, "IGU_RX_OUT_ALL_PKT_H"}, 325 326 {true, "IGU_TX_OUT_ALL_PKT_L"}, 327 {true, "IGU_TX_OUT_ALL_PKT_H"}, 328 {true, "IGU_RX_UNI_PKT_L"}, 329 {true, "IGU_RX_UNI_PKT_H"}, 330 {true, "IGU_RX_MULTI_PKT_L"}, 331 {true, "IGU_RX_MULTI_PKT_H"}, 332 333 {true, "IGU_RX_BROAD_PKT_L"}, 334 {true, "IGU_RX_BROAD_PKT_H"}, 335 {true, "EGU_TX_OUT_ALL_PKT_L"}, 336 {true, "EGU_TX_OUT_ALL_PKT_H"}, 337 {true, "EGU_TX_UNI_PKT_L"}, 338 {true, "EGU_TX_UNI_PKT_H"}, 339 340 {true, "EGU_TX_MULTI_PKT_L"}, 341 {true, "EGU_TX_MULTI_PKT_H"}, 342 {true, "EGU_TX_BROAD_PKT_L"}, 343 {true, "EGU_TX_BROAD_PKT_H"}, 344 {true, "IGU_TX_KEY_NUM_L"}, 345 {true, "IGU_TX_KEY_NUM_H"}, 346 347 {true, "IGU_RX_NON_TUN_PKT_L"}, 348 {true, "IGU_RX_NON_TUN_PKT_H"}, 349 {true, "IGU_RX_TUN_PKT_L"}, 350 {true, "IGU_RX_TUN_PKT_H"}, 351 {false, "Reserved"}, 352 {false, "Reserved"}, 353 }; 354 355 static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = { 356 {true, "tc_queue_num"}, 357 {true, "FSM_DFX_ST0"}, 358 {true, "FSM_DFX_ST1"}, 359 {true, "RPU_RX_PKT_DROP_CNT"}, 360 {true, "BUF_WAIT_TIMEOUT"}, 361 {true, "BUF_WAIT_TIMEOUT_QID"}, 362 }; 363 364 static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = { 365 {false, "Reserved"}, 366 {true, "FIFO_DFX_ST0"}, 367 {true, "FIFO_DFX_ST1"}, 368 {true, "FIFO_DFX_ST2"}, 369 {true, "FIFO_DFX_ST3"}, 370 {true, "FIFO_DFX_ST4"}, 371 372 {true, "FIFO_DFX_ST5"}, 373 {false, "Reserved"}, 374 {false, "Reserved"}, 375 {false, "Reserved"}, 376 {false, "Reserved"}, 377 {false, "Reserved"}, 378 }; 379 380 static const struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = { 381 {false, "Reserved"}, 382 {true, "NCSI_EGU_TX_FIFO_STS"}, 383 {true, "NCSI_PAUSE_STATUS"}, 384 {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"}, 385 {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"}, 386 {true, "NCSI_RX_CTRL_CKS_ERR_CNT"}, 387 388 {true, "NCSI_RX_CTRL_PKT_CNT"}, 389 {true, "NCSI_RX_PT_DMAC_ERR_CNT"}, 390 {true, "NCSI_RX_PT_SMAC_ERR_CNT"}, 391 {true, "NCSI_RX_PT_PKT_CNT"}, 392 {true, "NCSI_RX_FCS_ERR_CNT"}, 393 {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"}, 394 395 {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"}, 396 {true, "NCSI_TX_CTRL_PKT_CNT"}, 397 {true, "NCSI_TX_PT_DMAC_ERR_CNT"}, 398 {true, "NCSI_TX_PT_SMAC_ERR_CNT"}, 399 {true, "NCSI_TX_PT_PKT_CNT"}, 400 {true, "NCSI_TX_PT_PKT_TRUNC_CNT"}, 401 402 {true, "NCSI_TX_PT_PKT_ERR_CNT"}, 403 {true, "NCSI_TX_CTRL_PKT_ERR_CNT"}, 404 {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"}, 405 {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"}, 406 {false, "Reserved"}, 407 {false, "Reserved"}, 408 409 {true, "NCSI_MAC_RX_OCTETS_OK"}, 410 {true, "NCSI_MAC_RX_OCTETS_BAD"}, 411 {true, "NCSI_MAC_RX_UC_PKTS"}, 412 {true, "NCSI_MAC_RX_MC_PKTS"}, 413 {true, "NCSI_MAC_RX_BC_PKTS"}, 414 {true, "NCSI_MAC_RX_PKTS_64OCTETS"}, 415 416 {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"}, 417 {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"}, 418 {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"}, 419 {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"}, 420 {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"}, 421 {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"}, 422 423 {true, "NCSI_MAC_RX_FCS_ERRORS"}, 424 {true, "NCSI_MAC_RX_LONG_ERRORS"}, 425 {true, "NCSI_MAC_RX_JABBER_ERRORS"}, 426 {true, "NCSI_MAC_RX_RUNT_ERR_CNT"}, 427 {true, "NCSI_MAC_RX_SHORT_ERR_CNT"}, 428 {true, "NCSI_MAC_RX_FILT_PKT_CNT"}, 429 430 {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"}, 431 {true, "NCSI_MAC_TX_OCTETS_OK"}, 432 {true, "NCSI_MAC_TX_OCTETS_BAD"}, 433 {true, "NCSI_MAC_TX_UC_PKTS"}, 434 {true, "NCSI_MAC_TX_MC_PKTS"}, 435 {true, "NCSI_MAC_TX_BC_PKTS"}, 436 437 {true, "NCSI_MAC_TX_PKTS_64OCTETS"}, 438 {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"}, 439 {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"}, 440 {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"}, 441 {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"}, 442 {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"}, 443 444 {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"}, 445 {true, "NCSI_MAC_TX_UNDERRUN"}, 446 {true, "NCSI_MAC_TX_CRC_ERROR"}, 447 {true, "NCSI_MAC_TX_PAUSE_FRAMES"}, 448 {true, "NCSI_MAC_RX_PAD_PKTS"}, 449 {true, "NCSI_MAC_RX_PAUSE_FRAMES"}, 450 }; 451 452 static const struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = { 453 {false, "Reserved"}, 454 {true, "LGE_IGU_AFIFO_DFX_0"}, 455 {true, "LGE_IGU_AFIFO_DFX_1"}, 456 {true, "LGE_IGU_AFIFO_DFX_2"}, 457 {true, "LGE_IGU_AFIFO_DFX_3"}, 458 {true, "LGE_IGU_AFIFO_DFX_4"}, 459 460 {true, "LGE_IGU_AFIFO_DFX_5"}, 461 {true, "LGE_IGU_AFIFO_DFX_6"}, 462 {true, "LGE_IGU_AFIFO_DFX_7"}, 463 {true, "LGE_EGU_AFIFO_DFX_0"}, 464 {true, "LGE_EGU_AFIFO_DFX_1"}, 465 {true, "LGE_EGU_AFIFO_DFX_2"}, 466 467 {true, "LGE_EGU_AFIFO_DFX_3"}, 468 {true, "LGE_EGU_AFIFO_DFX_4"}, 469 {true, "LGE_EGU_AFIFO_DFX_5"}, 470 {true, "LGE_EGU_AFIFO_DFX_6"}, 471 {true, "LGE_EGU_AFIFO_DFX_7"}, 472 {true, "CGE_IGU_AFIFO_DFX_0"}, 473 474 {true, "CGE_IGU_AFIFO_DFX_1"}, 475 {true, "CGE_EGU_AFIFO_DFX_0"}, 476 {true, "CGE_EGU_AFIFO_DFX_1"}, 477 {false, "Reserved"}, 478 {false, "Reserved"}, 479 {false, "Reserved"}, 480 }; 481 482 static const struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = { 483 {false, "Reserved"}, 484 {true, "DROP_FROM_PRT_PKT_CNT"}, 485 {true, "DROP_FROM_HOST_PKT_CNT"}, 486 {true, "DROP_TX_VLAN_PROC_CNT"}, 487 {true, "DROP_MNG_CNT"}, 488 {true, "DROP_FD_CNT"}, 489 490 {true, "DROP_NO_DST_CNT"}, 491 {true, "DROP_MC_MBID_FULL_CNT"}, 492 {true, "DROP_SC_FILTERED"}, 493 {true, "PPP_MC_DROP_PKT_CNT"}, 494 {true, "DROP_PT_CNT"}, 495 {true, "DROP_MAC_ANTI_SPOOF_CNT"}, 496 497 {true, "DROP_IG_VFV_CNT"}, 498 {true, "DROP_IG_PRTV_CNT"}, 499 {true, "DROP_CNM_PFC_PAUSE_CNT"}, 500 {true, "DROP_TORUS_TC_CNT"}, 501 {true, "DROP_TORUS_LPBK_CNT"}, 502 {true, "PPP_HFS_STS"}, 503 504 {true, "PPP_MC_RSLT_STS"}, 505 {true, "PPP_P3U_STS"}, 506 {true, "PPP_RSLT_DESCR_STS"}, 507 {true, "PPP_UMV_STS_0"}, 508 {true, "PPP_UMV_STS_1"}, 509 {true, "PPP_VFV_STS"}, 510 511 {true, "PPP_GRO_KEY_CNT"}, 512 {true, "PPP_GRO_INFO_CNT"}, 513 {true, "PPP_GRO_DROP_CNT"}, 514 {true, "PPP_GRO_OUT_CNT"}, 515 {true, "PPP_GRO_KEY_MATCH_DATA_CNT"}, 516 {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"}, 517 518 {true, "PPP_GRO_INFO_MATCH_CNT"}, 519 {true, "PPP_GRO_FREE_ENTRY_CNT"}, 520 {true, "PPP_GRO_INNER_DFX_SIGNAL"}, 521 {false, "Reserved"}, 522 {false, "Reserved"}, 523 {false, "Reserved"}, 524 525 {true, "GET_RX_PKT_CNT_L"}, 526 {true, "GET_RX_PKT_CNT_H"}, 527 {true, "GET_TX_PKT_CNT_L"}, 528 {true, "GET_TX_PKT_CNT_H"}, 529 {true, "SEND_UC_PRT2HOST_PKT_CNT_L"}, 530 {true, "SEND_UC_PRT2HOST_PKT_CNT_H"}, 531 532 {true, "SEND_UC_PRT2PRT_PKT_CNT_L"}, 533 {true, "SEND_UC_PRT2PRT_PKT_CNT_H"}, 534 {true, "SEND_UC_HOST2HOST_PKT_CNT_L"}, 535 {true, "SEND_UC_HOST2HOST_PKT_CNT_H"}, 536 {true, "SEND_UC_HOST2PRT_PKT_CNT_L"}, 537 {true, "SEND_UC_HOST2PRT_PKT_CNT_H"}, 538 539 {true, "SEND_MC_FROM_PRT_CNT_L"}, 540 {true, "SEND_MC_FROM_PRT_CNT_H"}, 541 {true, "SEND_MC_FROM_HOST_CNT_L"}, 542 {true, "SEND_MC_FROM_HOST_CNT_H"}, 543 {true, "SSU_MC_RD_CNT_L"}, 544 {true, "SSU_MC_RD_CNT_H"}, 545 546 {true, "SSU_MC_DROP_CNT_L"}, 547 {true, "SSU_MC_DROP_CNT_H"}, 548 {true, "SSU_MC_RD_PKT_CNT_L"}, 549 {true, "SSU_MC_RD_PKT_CNT_H"}, 550 {true, "PPP_MC_2HOST_PKT_CNT_L"}, 551 {true, "PPP_MC_2HOST_PKT_CNT_H"}, 552 553 {true, "PPP_MC_2PRT_PKT_CNT_L"}, 554 {true, "PPP_MC_2PRT_PKT_CNT_H"}, 555 {true, "NTSNOS_PKT_CNT_L"}, 556 {true, "NTSNOS_PKT_CNT_H"}, 557 {true, "NTUP_PKT_CNT_L"}, 558 {true, "NTUP_PKT_CNT_H"}, 559 560 {true, "NTLCL_PKT_CNT_L"}, 561 {true, "NTLCL_PKT_CNT_H"}, 562 {true, "NTTGT_PKT_CNT_L"}, 563 {true, "NTTGT_PKT_CNT_H"}, 564 {true, "RTNS_PKT_CNT_L"}, 565 {true, "RTNS_PKT_CNT_H"}, 566 567 {true, "RTLPBK_PKT_CNT_L"}, 568 {true, "RTLPBK_PKT_CNT_H"}, 569 {true, "NR_PKT_CNT_L"}, 570 {true, "NR_PKT_CNT_H"}, 571 {true, "RR_PKT_CNT_L"}, 572 {true, "RR_PKT_CNT_H"}, 573 574 {true, "MNG_TBL_HIT_CNT_L"}, 575 {true, "MNG_TBL_HIT_CNT_H"}, 576 {true, "FD_TBL_HIT_CNT_L"}, 577 {true, "FD_TBL_HIT_CNT_H"}, 578 {true, "FD_LKUP_CNT_L"}, 579 {true, "FD_LKUP_CNT_H"}, 580 581 {true, "BC_HIT_CNT_L"}, 582 {true, "BC_HIT_CNT_H"}, 583 {true, "UM_TBL_UC_HIT_CNT_L"}, 584 {true, "UM_TBL_UC_HIT_CNT_H"}, 585 {true, "UM_TBL_MC_HIT_CNT_L"}, 586 {true, "UM_TBL_MC_HIT_CNT_H"}, 587 588 {true, "UM_TBL_VMDQ1_HIT_CNT_L"}, 589 {true, "UM_TBL_VMDQ1_HIT_CNT_H"}, 590 {true, "MTA_TBL_HIT_CNT_L"}, 591 {true, "MTA_TBL_HIT_CNT_H"}, 592 {true, "FWD_BONDING_HIT_CNT_L"}, 593 {true, "FWD_BONDING_HIT_CNT_H"}, 594 595 {true, "PROMIS_TBL_HIT_CNT_L"}, 596 {true, "PROMIS_TBL_HIT_CNT_H"}, 597 {true, "GET_TUNL_PKT_CNT_L"}, 598 {true, "GET_TUNL_PKT_CNT_H"}, 599 {true, "GET_BMC_PKT_CNT_L"}, 600 {true, "GET_BMC_PKT_CNT_H"}, 601 602 {true, "SEND_UC_PRT2BMC_PKT_CNT_L"}, 603 {true, "SEND_UC_PRT2BMC_PKT_CNT_H"}, 604 {true, "SEND_UC_HOST2BMC_PKT_CNT_L"}, 605 {true, "SEND_UC_HOST2BMC_PKT_CNT_H"}, 606 {true, "SEND_UC_BMC2HOST_PKT_CNT_L"}, 607 {true, "SEND_UC_BMC2HOST_PKT_CNT_H"}, 608 609 {true, "SEND_UC_BMC2PRT_PKT_CNT_L"}, 610 {true, "SEND_UC_BMC2PRT_PKT_CNT_H"}, 611 {true, "PPP_MC_2BMC_PKT_CNT_L"}, 612 {true, "PPP_MC_2BMC_PKT_CNT_H"}, 613 {true, "VLAN_MIRR_CNT_L"}, 614 {true, "VLAN_MIRR_CNT_H"}, 615 616 {true, "IG_MIRR_CNT_L"}, 617 {true, "IG_MIRR_CNT_H"}, 618 {true, "EG_MIRR_CNT_L"}, 619 {true, "EG_MIRR_CNT_H"}, 620 {true, "RX_DEFAULT_HOST_HIT_CNT_L"}, 621 {true, "RX_DEFAULT_HOST_HIT_CNT_H"}, 622 623 {true, "LAN_PAIR_CNT_L"}, 624 {true, "LAN_PAIR_CNT_H"}, 625 {true, "UM_TBL_MC_HIT_PKT_CNT_L"}, 626 {true, "UM_TBL_MC_HIT_PKT_CNT_H"}, 627 {true, "MTA_TBL_HIT_PKT_CNT_L"}, 628 {true, "MTA_TBL_HIT_PKT_CNT_H"}, 629 630 {true, "PROMIS_TBL_HIT_PKT_CNT_L"}, 631 {true, "PROMIS_TBL_HIT_PKT_CNT_H"}, 632 {false, "Reserved"}, 633 {false, "Reserved"}, 634 {false, "Reserved"}, 635 {false, "Reserved"}, 636 }; 637 638 static const struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = { 639 {false, "Reserved"}, 640 {true, "FSM_DFX_ST0"}, 641 {true, "FSM_DFX_ST1"}, 642 {true, "FSM_DFX_ST2"}, 643 {true, "FIFO_DFX_ST0"}, 644 {true, "FIFO_DFX_ST1"}, 645 646 {true, "FIFO_DFX_ST2"}, 647 {true, "FIFO_DFX_ST3"}, 648 {true, "FIFO_DFX_ST4"}, 649 {true, "FIFO_DFX_ST5"}, 650 {true, "FIFO_DFX_ST6"}, 651 {true, "FIFO_DFX_ST7"}, 652 653 {true, "FIFO_DFX_ST8"}, 654 {true, "FIFO_DFX_ST9"}, 655 {true, "FIFO_DFX_ST10"}, 656 {true, "FIFO_DFX_ST11"}, 657 {true, "Q_CREDIT_VLD_0"}, 658 {true, "Q_CREDIT_VLD_1"}, 659 660 {true, "Q_CREDIT_VLD_2"}, 661 {true, "Q_CREDIT_VLD_3"}, 662 {true, "Q_CREDIT_VLD_4"}, 663 {true, "Q_CREDIT_VLD_5"}, 664 {true, "Q_CREDIT_VLD_6"}, 665 {true, "Q_CREDIT_VLD_7"}, 666 667 {true, "Q_CREDIT_VLD_8"}, 668 {true, "Q_CREDIT_VLD_9"}, 669 {true, "Q_CREDIT_VLD_10"}, 670 {true, "Q_CREDIT_VLD_11"}, 671 {true, "Q_CREDIT_VLD_12"}, 672 {true, "Q_CREDIT_VLD_13"}, 673 674 {true, "Q_CREDIT_VLD_14"}, 675 {true, "Q_CREDIT_VLD_15"}, 676 {true, "Q_CREDIT_VLD_16"}, 677 {true, "Q_CREDIT_VLD_17"}, 678 {true, "Q_CREDIT_VLD_18"}, 679 {true, "Q_CREDIT_VLD_19"}, 680 681 {true, "Q_CREDIT_VLD_20"}, 682 {true, "Q_CREDIT_VLD_21"}, 683 {true, "Q_CREDIT_VLD_22"}, 684 {true, "Q_CREDIT_VLD_23"}, 685 {true, "Q_CREDIT_VLD_24"}, 686 {true, "Q_CREDIT_VLD_25"}, 687 688 {true, "Q_CREDIT_VLD_26"}, 689 {true, "Q_CREDIT_VLD_27"}, 690 {true, "Q_CREDIT_VLD_28"}, 691 {true, "Q_CREDIT_VLD_29"}, 692 {true, "Q_CREDIT_VLD_30"}, 693 {true, "Q_CREDIT_VLD_31"}, 694 695 {true, "GRO_BD_SERR_CNT"}, 696 {true, "GRO_CONTEXT_SERR_CNT"}, 697 {true, "RX_STASH_CFG_SERR_CNT"}, 698 {true, "AXI_RD_FBD_SERR_CNT"}, 699 {true, "GRO_BD_MERR_CNT"}, 700 {true, "GRO_CONTEXT_MERR_CNT"}, 701 702 {true, "RX_STASH_CFG_MERR_CNT"}, 703 {true, "AXI_RD_FBD_MERR_CNT"}, 704 {false, "Reserved"}, 705 {false, "Reserved"}, 706 {false, "Reserved"}, 707 {false, "Reserved"}, 708 }; 709 710 static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = { 711 {true, "q_num"}, 712 {true, "RCB_CFG_RX_RING_TAIL"}, 713 {true, "RCB_CFG_RX_RING_HEAD"}, 714 {true, "RCB_CFG_RX_RING_FBDNUM"}, 715 {true, "RCB_CFG_RX_RING_OFFSET"}, 716 {true, "RCB_CFG_RX_RING_FBDOFFSET"}, 717 718 {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"}, 719 {true, "RCB_CFG_TX_RING_TAIL"}, 720 {true, "RCB_CFG_TX_RING_HEAD"}, 721 {true, "RCB_CFG_TX_RING_FBDNUM"}, 722 {true, "RCB_CFG_TX_RING_OFFSET"}, 723 {true, "RCB_CFG_TX_RING_EBDNUM"}, 724 }; 725 726 #endif 727