1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #ifndef _IXGBE_H_
5 #define _IXGBE_H_
6
7 #include <linux/bitops.h>
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <linux/netdevice.h>
11 #include <linux/cpumask.h>
12 #include <linux/aer.h>
13 #include <linux/if_vlan.h>
14 #include <linux/jiffies.h>
15 #include <linux/phy.h>
16
17 #include <linux/timecounter.h>
18 #include <linux/net_tstamp.h>
19 #include <linux/ptp_clock_kernel.h>
20
21 #include "ixgbe_type.h"
22 #include "ixgbe_common.h"
23 #include "ixgbe_dcb.h"
24 #if IS_ENABLED(CONFIG_FCOE)
25 #define IXGBE_FCOE
26 #include "ixgbe_fcoe.h"
27 #endif /* IS_ENABLED(CONFIG_FCOE) */
28 #ifdef CONFIG_IXGBE_DCA
29 #include <linux/dca.h>
30 #endif
31 #include "ixgbe_ipsec.h"
32
33 #include <net/xdp.h>
34
35 /* common prefix used by pr_<> macros */
36 #undef pr_fmt
37 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38
39 /* TX/RX descriptor defines */
40 #define IXGBE_DEFAULT_TXD 512
41 #define IXGBE_DEFAULT_TX_WORK 256
42 #define IXGBE_MAX_TXD 4096
43 #define IXGBE_MIN_TXD 64
44
45 #if (PAGE_SIZE < 8192)
46 #define IXGBE_DEFAULT_RXD 512
47 #else
48 #define IXGBE_DEFAULT_RXD 128
49 #endif
50 #define IXGBE_MAX_RXD 4096
51 #define IXGBE_MIN_RXD 64
52
53 /* flow control */
54 #define IXGBE_MIN_FCRTL 0x40
55 #define IXGBE_MAX_FCRTL 0x7FF80
56 #define IXGBE_MIN_FCRTH 0x600
57 #define IXGBE_MAX_FCRTH 0x7FFF0
58 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
59 #define IXGBE_MIN_FCPAUSE 0
60 #define IXGBE_MAX_FCPAUSE 0xFFFF
61
62 /* Supported Rx Buffer Sizes */
63 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
64 #define IXGBE_RXBUFFER_1536 1536
65 #define IXGBE_RXBUFFER_2K 2048
66 #define IXGBE_RXBUFFER_3K 3072
67 #define IXGBE_RXBUFFER_4K 4096
68 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
69
70 /* Attempt to maximize the headroom available for incoming frames. We
71 * use a 2K buffer for receives and need 1536/1534 to store the data for
72 * the frame. This leaves us with 512 bytes of room. From that we need
73 * to deduct the space needed for the shared info and the padding needed
74 * to IP align the frame.
75 *
76 * Note: For cache line sizes 256 or larger this value is going to end
77 * up negative. In these cases we should fall back to the 3K
78 * buffers.
79 */
80 #if (PAGE_SIZE < 8192)
81 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN)
82 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \
83 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K))
84
ixgbe_compute_pad(int rx_buf_len)85 static inline int ixgbe_compute_pad(int rx_buf_len)
86 {
87 int page_size, pad_size;
88
89 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
90 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
91
92 return pad_size;
93 }
94
ixgbe_skb_pad(void)95 static inline int ixgbe_skb_pad(void)
96 {
97 int rx_buf_len;
98
99 /* If a 2K buffer cannot handle a standard Ethernet frame then
100 * optimize padding for a 3K buffer instead of a 1.5K buffer.
101 *
102 * For a 3K buffer we need to add enough padding to allow for
103 * tailroom due to NET_IP_ALIGN possibly shifting us out of
104 * cache-line alignment.
105 */
106 if (IXGBE_2K_TOO_SMALL_WITH_PADDING)
107 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN);
108 else
109 rx_buf_len = IXGBE_RXBUFFER_1536;
110
111 /* if needed make room for NET_IP_ALIGN */
112 rx_buf_len -= NET_IP_ALIGN;
113
114 return ixgbe_compute_pad(rx_buf_len);
115 }
116
117 #define IXGBE_SKB_PAD ixgbe_skb_pad()
118 #else
119 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
120 #endif
121
122 /*
123 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
124 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
125 * this adds up to 448 bytes of extra data.
126 *
127 * Since netdev_alloc_skb now allocates a page fragment we can use a value
128 * of 256 and the resultant skb will have a truesize of 960 or less.
129 */
130 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
131
132 /* How many Rx Buffers do we bundle into one write to the hardware ? */
133 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
134
135 #define IXGBE_RX_DMA_ATTR \
136 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
137
138 enum ixgbe_tx_flags {
139 /* cmd_type flags */
140 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
141 IXGBE_TX_FLAGS_TSO = 0x02,
142 IXGBE_TX_FLAGS_TSTAMP = 0x04,
143
144 /* olinfo flags */
145 IXGBE_TX_FLAGS_CC = 0x08,
146 IXGBE_TX_FLAGS_IPV4 = 0x10,
147 IXGBE_TX_FLAGS_CSUM = 0x20,
148 IXGBE_TX_FLAGS_IPSEC = 0x40,
149
150 /* software defined flags */
151 IXGBE_TX_FLAGS_SW_VLAN = 0x80,
152 IXGBE_TX_FLAGS_FCOE = 0x100,
153 };
154
155 /* VLAN info */
156 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
157 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
158 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
159 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
160
161 #define IXGBE_MAX_VF_MC_ENTRIES 30
162 #define IXGBE_MAX_VF_FUNCTIONS 64
163 #define IXGBE_MAX_VFTA_ENTRIES 128
164 #define MAX_EMULATION_MAC_ADDRS 16
165 #define IXGBE_MAX_PF_MACVLANS 15
166 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
167 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
168 #define IXGBE_X540_VF_DEVICE_ID 0x1515
169
170 struct vf_data_storage {
171 struct pci_dev *vfdev;
172 unsigned char vf_mac_addresses[ETH_ALEN];
173 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
174 u16 num_vf_mc_hashes;
175 bool clear_to_send;
176 bool pf_set_mac;
177 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
178 u16 pf_qos;
179 u16 tx_rate;
180 int link_enable;
181 int link_state;
182 u8 spoofchk_enabled;
183 bool rss_query_enabled;
184 u8 trusted;
185 int xcast_mode;
186 unsigned int vf_api;
187 u8 primary_abort_count;
188 };
189
190 enum ixgbevf_xcast_modes {
191 IXGBEVF_XCAST_MODE_NONE = 0,
192 IXGBEVF_XCAST_MODE_MULTI,
193 IXGBEVF_XCAST_MODE_ALLMULTI,
194 IXGBEVF_XCAST_MODE_PROMISC,
195 };
196
197 struct vf_macvlans {
198 struct list_head l;
199 int vf;
200 bool free;
201 bool is_macvlan;
202 u8 vf_macvlan[ETH_ALEN];
203 };
204
205 #define IXGBE_MAX_TXD_PWR 14
206 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR)
207
208 /* Tx Descriptors needed, worst case */
209 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
210 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
211
212 /* wrapper around a pointer to a socket buffer,
213 * so a DMA handle can be stored along with the buffer */
214 struct ixgbe_tx_buffer {
215 union ixgbe_adv_tx_desc *next_to_watch;
216 unsigned long time_stamp;
217 union {
218 struct sk_buff *skb;
219 struct xdp_frame *xdpf;
220 };
221 unsigned int bytecount;
222 unsigned short gso_segs;
223 __be16 protocol;
224 DEFINE_DMA_UNMAP_ADDR(dma);
225 DEFINE_DMA_UNMAP_LEN(len);
226 u32 tx_flags;
227 };
228
229 struct ixgbe_rx_buffer {
230 union {
231 struct {
232 struct sk_buff *skb;
233 dma_addr_t dma;
234 struct page *page;
235 __u32 page_offset;
236 __u16 pagecnt_bias;
237 };
238 struct {
239 bool discard;
240 struct xdp_buff *xdp;
241 };
242 };
243 };
244
245 struct ixgbe_queue_stats {
246 u64 packets;
247 u64 bytes;
248 };
249
250 struct ixgbe_tx_queue_stats {
251 u64 restart_queue;
252 u64 tx_busy;
253 u64 tx_done_old;
254 };
255
256 struct ixgbe_rx_queue_stats {
257 u64 rsc_count;
258 u64 rsc_flush;
259 u64 non_eop_descs;
260 u64 alloc_rx_page;
261 u64 alloc_rx_page_failed;
262 u64 alloc_rx_buff_failed;
263 u64 csum_err;
264 };
265
266 #define IXGBE_TS_HDR_LEN 8
267
268 enum ixgbe_ring_state_t {
269 __IXGBE_RX_3K_BUFFER,
270 __IXGBE_RX_BUILD_SKB_ENABLED,
271 __IXGBE_RX_RSC_ENABLED,
272 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
273 __IXGBE_RX_FCOE,
274 __IXGBE_TX_FDIR_INIT_DONE,
275 __IXGBE_TX_XPS_INIT_DONE,
276 __IXGBE_TX_DETECT_HANG,
277 __IXGBE_HANG_CHECK_ARMED,
278 __IXGBE_TX_XDP_RING,
279 __IXGBE_TX_DISABLED,
280 };
281
282 #define ring_uses_build_skb(ring) \
283 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state)
284
285 struct ixgbe_fwd_adapter {
286 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
287 struct net_device *netdev;
288 unsigned int tx_base_queue;
289 unsigned int rx_base_queue;
290 int pool;
291 };
292
293 #define check_for_tx_hang(ring) \
294 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
295 #define set_check_for_tx_hang(ring) \
296 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
297 #define clear_check_for_tx_hang(ring) \
298 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
299 #define ring_is_rsc_enabled(ring) \
300 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
301 #define set_ring_rsc_enabled(ring) \
302 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
303 #define clear_ring_rsc_enabled(ring) \
304 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
305 #define ring_is_xdp(ring) \
306 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
307 #define set_ring_xdp(ring) \
308 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
309 #define clear_ring_xdp(ring) \
310 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
311 struct ixgbe_ring {
312 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
313 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
314 struct net_device *netdev; /* netdev ring belongs to */
315 struct bpf_prog *xdp_prog;
316 struct device *dev; /* device for DMA mapping */
317 void *desc; /* descriptor ring memory */
318 union {
319 struct ixgbe_tx_buffer *tx_buffer_info;
320 struct ixgbe_rx_buffer *rx_buffer_info;
321 };
322 unsigned long state;
323 u8 __iomem *tail;
324 dma_addr_t dma; /* phys. address of descriptor ring */
325 unsigned int size; /* length in bytes */
326
327 u16 count; /* amount of descriptors */
328
329 u8 queue_index; /* needed for multiqueue queue management */
330 u8 reg_idx; /* holds the special value that gets
331 * the hardware register offset
332 * associated with this ring, which is
333 * different for DCB and RSS modes
334 */
335 u16 next_to_use;
336 u16 next_to_clean;
337
338 unsigned long last_rx_timestamp;
339
340 union {
341 u16 next_to_alloc;
342 struct {
343 u8 atr_sample_rate;
344 u8 atr_count;
345 };
346 };
347
348 u8 dcb_tc;
349 struct ixgbe_queue_stats stats;
350 struct u64_stats_sync syncp;
351 union {
352 struct ixgbe_tx_queue_stats tx_stats;
353 struct ixgbe_rx_queue_stats rx_stats;
354 };
355 struct xdp_rxq_info xdp_rxq;
356 struct xsk_buff_pool *xsk_pool;
357 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */
358 u16 rx_buf_len;
359 } ____cacheline_internodealigned_in_smp;
360
361 enum ixgbe_ring_f_enum {
362 RING_F_NONE = 0,
363 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
364 RING_F_RSS,
365 RING_F_FDIR,
366 #ifdef IXGBE_FCOE
367 RING_F_FCOE,
368 #endif /* IXGBE_FCOE */
369
370 RING_F_ARRAY_SIZE /* must be last in enum set */
371 };
372
373 #define IXGBE_MAX_RSS_INDICES 16
374 #define IXGBE_MAX_RSS_INDICES_X550 63
375 #define IXGBE_MAX_VMDQ_INDICES 64
376 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
377 #define IXGBE_MAX_FCOE_INDICES 8
378 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
379 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
380 #define MAX_XDP_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
381 #define IXGBE_MAX_L2A_QUEUES 4
382 #define IXGBE_BAD_L2A_QUEUE 3
383 #define IXGBE_MAX_MACVLANS 63
384
385 struct ixgbe_ring_feature {
386 u16 limit; /* upper limit on feature indices */
387 u16 indices; /* current value of indices */
388 u16 mask; /* Mask used for feature to ring mapping */
389 u16 offset; /* offset to start of feature */
390 } ____cacheline_internodealigned_in_smp;
391
392 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
393 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
394 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
395
396 /*
397 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
398 * this is twice the size of a half page we need to double the page order
399 * for FCoE enabled Rx queues.
400 */
ixgbe_rx_bufsz(struct ixgbe_ring * ring)401 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
402 {
403 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
404 return IXGBE_RXBUFFER_3K;
405 #if (PAGE_SIZE < 8192)
406 if (ring_uses_build_skb(ring))
407 return IXGBE_MAX_2K_FRAME_BUILD_SKB;
408 #endif
409 return IXGBE_RXBUFFER_2K;
410 }
411
ixgbe_rx_pg_order(struct ixgbe_ring * ring)412 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
413 {
414 #if (PAGE_SIZE < 8192)
415 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
416 return 1;
417 #endif
418 return 0;
419 }
420 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
421
422 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2
423 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10
424 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126
425 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80
426 #define IXGBE_ITR_ADAPTIVE_BULK 0x00
427
428 struct ixgbe_ring_container {
429 struct ixgbe_ring *ring; /* pointer to linked list of rings */
430 unsigned long next_update; /* jiffies value of last update */
431 unsigned int total_bytes; /* total bytes processed this int */
432 unsigned int total_packets; /* total packets processed this int */
433 u16 work_limit; /* total work allowed per interrupt */
434 u8 count; /* total number of rings in vector */
435 u8 itr; /* current ITR setting for ring */
436 };
437
438 /* iterator for handling rings in ring container */
439 #define ixgbe_for_each_ring(pos, head) \
440 for (pos = (head).ring; pos != NULL; pos = pos->next)
441
442 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
443 ? 8 : 1)
444 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
445
446 /* MAX_Q_VECTORS of these are allocated,
447 * but we only use one per queue-specific vector.
448 */
449 struct ixgbe_q_vector {
450 struct ixgbe_adapter *adapter;
451 #ifdef CONFIG_IXGBE_DCA
452 int cpu; /* CPU for DCA */
453 #endif
454 u16 v_idx; /* index of q_vector within array, also used for
455 * finding the bit in EICR and friends that
456 * represents the vector for this ring */
457 u16 itr; /* Interrupt throttle rate written to EITR */
458 struct ixgbe_ring_container rx, tx;
459
460 struct napi_struct napi;
461 cpumask_t affinity_mask;
462 int numa_node;
463 struct rcu_head rcu; /* to avoid race with update stats on free */
464 char name[IFNAMSIZ + 9];
465
466 /* for dynamic allocation of rings associated with this q_vector */
467 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp;
468 };
469
470 #ifdef CONFIG_IXGBE_HWMON
471
472 #define IXGBE_HWMON_TYPE_LOC 0
473 #define IXGBE_HWMON_TYPE_TEMP 1
474 #define IXGBE_HWMON_TYPE_CAUTION 2
475 #define IXGBE_HWMON_TYPE_MAX 3
476
477 struct hwmon_attr {
478 struct device_attribute dev_attr;
479 struct ixgbe_hw *hw;
480 struct ixgbe_thermal_diode_data *sensor;
481 char name[12];
482 };
483
484 struct hwmon_buff {
485 struct attribute_group group;
486 const struct attribute_group *groups[2];
487 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
488 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
489 unsigned int n_hwmon;
490 };
491 #endif /* CONFIG_IXGBE_HWMON */
492
493 /*
494 * microsecond values for various ITR rates shifted by 2 to fit itr register
495 * with the first 3 bits reserved 0
496 */
497 #define IXGBE_MIN_RSC_ITR 24
498 #define IXGBE_100K_ITR 40
499 #define IXGBE_20K_ITR 200
500 #define IXGBE_12K_ITR 336
501
502 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
ixgbe_test_staterr(union ixgbe_adv_rx_desc * rx_desc,const u32 stat_err_bits)503 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
504 const u32 stat_err_bits)
505 {
506 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
507 }
508
ixgbe_desc_unused(struct ixgbe_ring * ring)509 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
510 {
511 u16 ntc = ring->next_to_clean;
512 u16 ntu = ring->next_to_use;
513
514 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
515 }
516
517 #define IXGBE_RX_DESC(R, i) \
518 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
519 #define IXGBE_TX_DESC(R, i) \
520 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
521 #define IXGBE_TX_CTXTDESC(R, i) \
522 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
523
524 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
525 #ifdef IXGBE_FCOE
526 /* Use 3K as the baby jumbo frame size for FCoE */
527 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
528 #endif /* IXGBE_FCOE */
529
530 #define OTHER_VECTOR 1
531 #define NON_Q_VECTORS (OTHER_VECTOR)
532
533 #define MAX_MSIX_VECTORS_82599 64
534 #define MAX_Q_VECTORS_82599 64
535 #define MAX_MSIX_VECTORS_82598 18
536 #define MAX_Q_VECTORS_82598 16
537
538 struct ixgbe_mac_addr {
539 u8 addr[ETH_ALEN];
540 u16 pool;
541 u16 state; /* bitmask */
542 };
543
544 #define IXGBE_MAC_STATE_DEFAULT 0x1
545 #define IXGBE_MAC_STATE_MODIFIED 0x2
546 #define IXGBE_MAC_STATE_IN_USE 0x4
547
548 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
549 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
550
551 #define MIN_MSIX_Q_VECTORS 1
552 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
553
554 /* default to trying for four seconds */
555 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
556 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */
557
558 #define IXGBE_PRIMARY_ABORT_LIMIT 5
559
560 /* board specific private data structure */
561 struct ixgbe_adapter {
562 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
563 /* OS defined structs */
564 struct net_device *netdev;
565 struct bpf_prog *xdp_prog;
566 struct pci_dev *pdev;
567 struct mii_bus *mii_bus;
568
569 unsigned long state;
570
571 /* Some features need tri-state capability,
572 * thus the additional *_CAPABLE flags.
573 */
574 u32 flags;
575 #define IXGBE_FLAG_MSI_ENABLED BIT(1)
576 #define IXGBE_FLAG_MSIX_ENABLED BIT(3)
577 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4)
578 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5)
579 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6)
580 #define IXGBE_FLAG_DCA_ENABLED BIT(8)
581 #define IXGBE_FLAG_DCA_CAPABLE BIT(9)
582 #define IXGBE_FLAG_IMIR_ENABLED BIT(10)
583 #define IXGBE_FLAG_MQ_CAPABLE BIT(11)
584 #define IXGBE_FLAG_DCB_ENABLED BIT(12)
585 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13)
586 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14)
587 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15)
588 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16)
589 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17)
590 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18)
591 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19)
592 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20)
593 #define IXGBE_FLAG_FCOE_ENABLED BIT(21)
594 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22)
595 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23)
596 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25)
597 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26)
598 #define IXGBE_FLAG_DCB_CAPABLE BIT(27)
599
600 u32 flags2;
601 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0)
602 #define IXGBE_FLAG2_RSC_ENABLED BIT(1)
603 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2)
604 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3)
605 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4)
606 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5)
607 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7)
608 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8)
609 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9)
610 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10)
611 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11)
612 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13)
613 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14)
614 #define IXGBE_FLAG2_EEE_ENABLED BIT(15)
615 #define IXGBE_FLAG2_RX_LEGACY BIT(16)
616 #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17)
617 #define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18)
618 #define IXGBE_FLAG2_AUTO_DISABLE_VF BIT(19)
619
620 /* Tx fast path data */
621 int num_tx_queues;
622 u16 tx_itr_setting;
623 u16 tx_work_limit;
624 u64 tx_ipsec;
625
626 /* Rx fast path data */
627 int num_rx_queues;
628 u16 rx_itr_setting;
629 u64 rx_ipsec;
630
631 /* Port number used to identify VXLAN traffic */
632 __be16 vxlan_port;
633 __be16 geneve_port;
634
635 /* XDP */
636 int num_xdp_queues;
637 struct ixgbe_ring *xdp_ring[MAX_XDP_QUEUES];
638 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */
639
640 /* TX */
641 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
642
643 u64 restart_queue;
644 u64 lsc_int;
645 u32 tx_timeout_count;
646
647 /* RX */
648 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
649 int num_rx_pools; /* == num_rx_queues in 82598 */
650 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
651 u64 hw_csum_rx_error;
652 u64 hw_rx_no_dma_resources;
653 u64 rsc_total_count;
654 u64 rsc_total_flush;
655 u64 non_eop_descs;
656 u32 alloc_rx_page;
657 u32 alloc_rx_page_failed;
658 u32 alloc_rx_buff_failed;
659
660 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
661
662 /* DCB parameters */
663 struct ieee_pfc *ixgbe_ieee_pfc;
664 struct ieee_ets *ixgbe_ieee_ets;
665 struct ixgbe_dcb_config dcb_cfg;
666 struct ixgbe_dcb_config temp_dcb_cfg;
667 u8 hw_tcs;
668 u8 dcb_set_bitmap;
669 u8 dcbx_cap;
670 enum ixgbe_fc_mode last_lfc_mode;
671
672 int num_q_vectors; /* current number of q_vectors for device */
673 int max_q_vectors; /* true count of q_vectors for device */
674 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
675 struct msix_entry *msix_entries;
676
677 u32 test_icr;
678 struct ixgbe_ring test_tx_ring;
679 struct ixgbe_ring test_rx_ring;
680
681 /* structs defined in ixgbe_hw.h */
682 struct ixgbe_hw hw;
683 u16 msg_enable;
684 struct ixgbe_hw_stats stats;
685
686 u64 tx_busy;
687 unsigned int tx_ring_count;
688 unsigned int xdp_ring_count;
689 unsigned int rx_ring_count;
690
691 u32 link_speed;
692 bool link_up;
693 unsigned long sfp_poll_time;
694 unsigned long link_check_timeout;
695
696 struct timer_list service_timer;
697 struct work_struct service_task;
698
699 struct hlist_head fdir_filter_list;
700 unsigned long fdir_overflow; /* number of times ATR was backed off */
701 union ixgbe_atr_input fdir_mask;
702 int fdir_filter_count;
703 u32 fdir_pballoc;
704 u32 atr_sample_rate;
705 spinlock_t fdir_perfect_lock;
706
707 #ifdef IXGBE_FCOE
708 struct ixgbe_fcoe fcoe;
709 #endif /* IXGBE_FCOE */
710 u8 __iomem *io_addr; /* Mainly for iounmap use */
711 u32 wol;
712
713 u16 bridge_mode;
714
715 char eeprom_id[NVM_VER_SIZE];
716 u16 eeprom_cap;
717
718 u32 interrupt_event;
719 u32 led_reg;
720
721 struct ptp_clock *ptp_clock;
722 struct ptp_clock_info ptp_caps;
723 struct work_struct ptp_tx_work;
724 struct sk_buff *ptp_tx_skb;
725 struct hwtstamp_config tstamp_config;
726 unsigned long ptp_tx_start;
727 unsigned long last_overflow_check;
728 unsigned long last_rx_ptp_check;
729 unsigned long last_rx_timestamp;
730 spinlock_t tmreg_lock;
731 struct cyclecounter hw_cc;
732 struct timecounter hw_tc;
733 u32 base_incval;
734 u32 tx_hwtstamp_timeouts;
735 u32 tx_hwtstamp_skipped;
736 u32 rx_hwtstamp_cleared;
737 void (*ptp_setup_sdp)(struct ixgbe_adapter *);
738
739 /* SR-IOV */
740 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
741 unsigned int num_vfs;
742 struct vf_data_storage *vfinfo;
743 int vf_rate_link_speed;
744 struct vf_macvlans vf_mvs;
745 struct vf_macvlans *mv_list;
746
747 u32 timer_event_accumulator;
748 u32 vferr_refcount;
749 struct ixgbe_mac_addr *mac_table;
750 struct kobject *info_kobj;
751 #ifdef CONFIG_IXGBE_HWMON
752 struct hwmon_buff *ixgbe_hwmon_buff;
753 #endif /* CONFIG_IXGBE_HWMON */
754 #ifdef CONFIG_DEBUG_FS
755 struct dentry *ixgbe_dbg_adapter;
756 #endif /*CONFIG_DEBUG_FS*/
757
758 u8 default_up;
759 /* Bitmask indicating in use pools */
760 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1);
761
762 #define IXGBE_MAX_LINK_HANDLE 10
763 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE];
764 unsigned long tables;
765
766 /* maximum number of RETA entries among all devices supported by ixgbe
767 * driver: currently it's x550 device in non-SRIOV mode
768 */
769 #define IXGBE_MAX_RETA_ENTRIES 512
770 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
771
772 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
773 u32 *rss_key;
774
775 #ifdef CONFIG_IXGBE_IPSEC
776 struct ixgbe_ipsec *ipsec;
777 #endif /* CONFIG_IXGBE_IPSEC */
778 spinlock_t vfs_lock;
779 };
780
ixgbe_max_rss_indices(struct ixgbe_adapter * adapter)781 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
782 {
783 switch (adapter->hw.mac.type) {
784 case ixgbe_mac_82598EB:
785 case ixgbe_mac_82599EB:
786 case ixgbe_mac_X540:
787 return IXGBE_MAX_RSS_INDICES;
788 case ixgbe_mac_X550:
789 case ixgbe_mac_X550EM_x:
790 case ixgbe_mac_x550em_a:
791 return IXGBE_MAX_RSS_INDICES_X550;
792 default:
793 return 0;
794 }
795 }
796
797 struct ixgbe_fdir_filter {
798 struct hlist_node fdir_node;
799 union ixgbe_atr_input filter;
800 u16 sw_idx;
801 u64 action;
802 };
803
804 enum ixgbe_state_t {
805 __IXGBE_TESTING,
806 __IXGBE_RESETTING,
807 __IXGBE_DOWN,
808 __IXGBE_DISABLED,
809 __IXGBE_REMOVING,
810 __IXGBE_SERVICE_SCHED,
811 __IXGBE_SERVICE_INITED,
812 __IXGBE_IN_SFP_INIT,
813 __IXGBE_PTP_RUNNING,
814 __IXGBE_PTP_TX_IN_PROGRESS,
815 __IXGBE_RESET_REQUESTED,
816 };
817
818 struct ixgbe_cb {
819 union { /* Union defining head/tail partner */
820 struct sk_buff *head;
821 struct sk_buff *tail;
822 };
823 dma_addr_t dma;
824 u16 append_cnt;
825 bool page_released;
826 };
827 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
828
829 enum ixgbe_boards {
830 board_82598,
831 board_82599,
832 board_X540,
833 board_X550,
834 board_X550EM_x,
835 board_x550em_x_fw,
836 board_x550em_a,
837 board_x550em_a_fw,
838 };
839
840 extern const struct ixgbe_info ixgbe_82598_info;
841 extern const struct ixgbe_info ixgbe_82599_info;
842 extern const struct ixgbe_info ixgbe_X540_info;
843 extern const struct ixgbe_info ixgbe_X550_info;
844 extern const struct ixgbe_info ixgbe_X550EM_x_info;
845 extern const struct ixgbe_info ixgbe_x550em_x_fw_info;
846 extern const struct ixgbe_info ixgbe_x550em_a_info;
847 extern const struct ixgbe_info ixgbe_x550em_a_fw_info;
848 #ifdef CONFIG_IXGBE_DCB
849 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops;
850 #endif
851
852 extern char ixgbe_driver_name[];
853 #ifdef IXGBE_FCOE
854 extern char ixgbe_default_device_descr[];
855 #endif /* IXGBE_FCOE */
856
857 int ixgbe_open(struct net_device *netdev);
858 int ixgbe_close(struct net_device *netdev);
859 void ixgbe_up(struct ixgbe_adapter *adapter);
860 void ixgbe_down(struct ixgbe_adapter *adapter);
861 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
862 void ixgbe_reset(struct ixgbe_adapter *adapter);
863 void ixgbe_set_ethtool_ops(struct net_device *netdev);
864 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
865 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
866 void ixgbe_free_rx_resources(struct ixgbe_ring *);
867 void ixgbe_free_tx_resources(struct ixgbe_ring *);
868 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
869 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
870 void ixgbe_disable_rx(struct ixgbe_adapter *adapter);
871 void ixgbe_disable_tx(struct ixgbe_adapter *adapter);
872 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
873 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
874 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
875 u16 subdevice_id);
876 #ifdef CONFIG_PCI_IOV
877 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
878 #endif
879 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
880 const u8 *addr, u16 queue);
881 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
882 const u8 *addr, u16 queue);
883 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid);
884 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
885 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
886 struct ixgbe_ring *);
887 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
888 struct ixgbe_tx_buffer *);
889 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
890 void ixgbe_write_eitr(struct ixgbe_q_vector *);
891 int ixgbe_poll(struct napi_struct *napi, int budget);
892 int ethtool_ioctl(struct ifreq *ifr);
893 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
894 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
895 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
896 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
897 union ixgbe_atr_hash_dword input,
898 union ixgbe_atr_hash_dword common,
899 u8 queue);
900 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
901 union ixgbe_atr_input *input_mask);
902 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
903 union ixgbe_atr_input *input,
904 u16 soft_id, u8 queue);
905 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
906 union ixgbe_atr_input *input,
907 u16 soft_id);
908 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
909 union ixgbe_atr_input *mask);
910 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
911 struct ixgbe_fdir_filter *input,
912 u16 sw_idx);
913 void ixgbe_set_rx_mode(struct net_device *netdev);
914 #ifdef CONFIG_IXGBE_DCB
915 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
916 #endif
917 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
918 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
919 void ixgbe_do_reset(struct net_device *netdev);
920 #ifdef CONFIG_IXGBE_HWMON
921 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
922 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
923 #endif /* CONFIG_IXGBE_HWMON */
924 #ifdef IXGBE_FCOE
925 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
926 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
927 u8 *hdr_len);
928 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
929 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
930 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
931 struct scatterlist *sgl, unsigned int sgc);
932 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
933 struct scatterlist *sgl, unsigned int sgc);
934 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
935 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
936 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
937 int ixgbe_fcoe_enable(struct net_device *netdev);
938 int ixgbe_fcoe_disable(struct net_device *netdev);
939 #ifdef CONFIG_IXGBE_DCB
940 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
941 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
942 #endif /* CONFIG_IXGBE_DCB */
943 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
944 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
945 struct netdev_fcoe_hbainfo *info);
946 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
947 #endif /* IXGBE_FCOE */
948 #ifdef CONFIG_DEBUG_FS
949 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
950 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
951 void ixgbe_dbg_init(void);
952 void ixgbe_dbg_exit(void);
953 #else
ixgbe_dbg_adapter_init(struct ixgbe_adapter * adapter)954 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
ixgbe_dbg_adapter_exit(struct ixgbe_adapter * adapter)955 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
ixgbe_dbg_init(void)956 static inline void ixgbe_dbg_init(void) {}
ixgbe_dbg_exit(void)957 static inline void ixgbe_dbg_exit(void) {}
958 #endif /* CONFIG_DEBUG_FS */
txring_txq(const struct ixgbe_ring * ring)959 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
960 {
961 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
962 }
963
964 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
965 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
966 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
967 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
968 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
969 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter);
970 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *);
971 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb);
ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)972 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
973 union ixgbe_adv_rx_desc *rx_desc,
974 struct sk_buff *skb)
975 {
976 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) {
977 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb);
978 return;
979 }
980
981 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
982 return;
983
984 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
985
986 /* Update the last_rx_timestamp timer in order to enable watchdog check
987 * for error case of latched timestamp on a dropped packet.
988 */
989 rx_ring->last_rx_timestamp = jiffies;
990 }
991
992 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
993 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
994 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
995 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
996 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter);
997 #ifdef CONFIG_PCI_IOV
998 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
999 #endif
1000
1001 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
1002 struct ixgbe_adapter *adapter,
1003 struct ixgbe_ring *tx_ring);
1004 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
1005 void ixgbe_store_key(struct ixgbe_adapter *adapter);
1006 void ixgbe_store_reta(struct ixgbe_adapter *adapter);
1007 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1008 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
1009 #ifdef CONFIG_IXGBE_IPSEC
1010 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);
1011 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter);
1012 void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter);
1013 void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1014 union ixgbe_adv_rx_desc *rx_desc,
1015 struct sk_buff *skb);
1016 int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
1017 struct ixgbe_ipsec_tx_data *itd);
1018 void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf);
1019 int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1020 int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1021 #else
ixgbe_init_ipsec_offload(struct ixgbe_adapter * adapter)1022 static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { }
ixgbe_stop_ipsec_offload(struct ixgbe_adapter * adapter)1023 static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { }
ixgbe_ipsec_restore(struct ixgbe_adapter * adapter)1024 static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { }
ixgbe_ipsec_rx(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1025 static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1026 union ixgbe_adv_rx_desc *rx_desc,
1027 struct sk_buff *skb) { }
ixgbe_ipsec_tx(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,struct ixgbe_ipsec_tx_data * itd)1028 static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring,
1029 struct ixgbe_tx_buffer *first,
1030 struct ixgbe_ipsec_tx_data *itd) { return 0; }
ixgbe_ipsec_vf_clear(struct ixgbe_adapter * adapter,u32 vf)1031 static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter,
1032 u32 vf) { }
ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter * adapter,u32 * mbuf,u32 vf)1033 static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter,
1034 u32 *mbuf, u32 vf) { return -EACCES; }
ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter * adapter,u32 * mbuf,u32 vf)1035 static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter,
1036 u32 *mbuf, u32 vf) { return -EACCES; }
1037 #endif /* CONFIG_IXGBE_IPSEC */
1038
ixgbe_enabled_xdp_adapter(struct ixgbe_adapter * adapter)1039 static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter)
1040 {
1041 return !!adapter->xdp_prog;
1042 }
1043
1044 #endif /* _IXGBE_H_ */
1045