1 /* -*- mesa-c++ -*- 2 * 3 * Copyright (c) 2022 Collabora LTD 4 * 5 * Author: Gert Wollny <gert.wollny@collabora.com> 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * on the rights to use, copy, modify, merge, publish, distribute, sub 11 * license, and/or sell copies of the Software, and to permit persons to whom 12 * the Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27 #ifndef GDSINSTR_H 28 #define GDSINSTR_H 29 30 #include "sfn_instr.h" 31 #include "sfn_valuefactory.h" 32 33 namespace r600 { 34 35 class Shader; 36 37 class GDSInstr : public Instr { 38 public: 39 40 GDSInstr(ESDOp op, Register *dest, 41 const RegisterVec4& src, int uav_base, 42 PRegister uav_id); 43 44 bool is_equal_to(const GDSInstr& lhs) const; 45 46 void accept(ConstInstrVisitor& visitor) const override; 47 void accept(InstrVisitor& visitor) override; 48 49 bool do_ready() const override; 50 opcode()51 auto opcode() const {return m_op;} src()52 auto src() const { return m_src;} 53 dest()54 const auto& dest() const { return m_dest;} dest()55 auto& dest() { return m_dest;} 56 uav_id()57 auto uav_id() const {return m_uav_id;} uav_base()58 auto uav_base() const {return m_uav_base;} 59 60 static auto from_string(std::istream& is, ValueFactory& value_factory) -> Pointer; 61 62 static bool emit_atomic_counter(nir_intrinsic_instr *intr, Shader& shader); slots()63 uint32_t slots() const override {return 1;}; 64 65 private: 66 67 static bool emit_atomic_read(nir_intrinsic_instr *intr, Shader& shader); 68 static bool emit_atomic_op2(nir_intrinsic_instr *intr, Shader& shader); 69 static bool emit_atomic_inc(nir_intrinsic_instr *intr, Shader& shader); 70 static bool emit_atomic_pre_dec(nir_intrinsic_instr *intr, Shader& shader); 71 72 void do_print(std::ostream& os) const override; 73 74 ESDOp m_op{DS_OP_INVALID}; 75 Register *m_dest; 76 77 RegisterVec4 m_src; 78 79 int m_uav_base{0}; 80 PRegister m_uav_id{nullptr}; 81 std::bitset<8> m_tex_flags; 82 }; 83 84 85 class RatInstr : public Instr { 86 87 public: 88 enum ERatOp { 89 NOP, 90 STORE_TYPED, 91 STORE_RAW, 92 STORE_RAW_FDENORM, 93 CMPXCHG_INT, 94 CMPXCHG_FLT, 95 CMPXCHG_FDENORM, 96 ADD, 97 SUB, 98 RSUB, 99 MIN_INT, 100 MIN_UINT, 101 MAX_INT, 102 MAX_UINT, 103 AND, 104 OR, 105 XOR, 106 MSKOR, 107 INC_UINT, 108 DEC_UINT, 109 NOP_RTN = 32, 110 XCHG_RTN = 34, 111 XCHG_FDENORM_RTN, 112 CMPXCHG_INT_RTN, 113 CMPXCHG_FLT_RTN, 114 CMPXCHG_FDENORM_RTN, 115 ADD_RTN, 116 SUB_RTN, 117 RSUB_RTN, 118 MIN_INT_RTN, 119 MIN_UINT_RTN, 120 MAX_INT_RTN, 121 MAX_UINT_RTN, 122 AND_RTN, 123 OR_RTN, 124 XOR_RTN, 125 MSKOR_RTN, 126 UINT_RTN, 127 UNSUPPORTED 128 }; 129 130 RatInstr(ECFOpCode cf_opcode, ERatOp rat_op, 131 const RegisterVec4& data, const RegisterVec4& index, 132 int rat_id, PRegister rat_id_offset, 133 int burst_count, int comp_mask, int element_size); 134 rat_id_offset()135 auto rat_id_offset() const { return m_rat_id_offset;} rat_id()136 int rat_id() const { return m_rat_id;} 137 rat_op()138 ERatOp rat_op() const {return m_rat_op;} 139 value()140 const auto& value() const { return m_data;} value()141 auto& value() { return m_data;} 142 addr()143 const auto& addr() const { return m_index;} addr()144 auto& addr() { return m_index;} 145 data_gpr()146 int data_gpr() const {return m_data.sel();} index_gpr()147 int index_gpr() const {return m_index.sel();} elm_size()148 int elm_size() const {return m_element_size;} 149 comp_mask()150 int comp_mask() const {return m_comp_mask;} 151 need_ack()152 bool need_ack() const {return m_need_ack;} burst_count()153 int burst_count() const {return m_burst_count;} 154 data_swz(int chan)155 int data_swz(int chan) const {return m_data[chan]->chan();} 156 cf_opcode()157 ECFOpCode cf_opcode() const { return m_cf_opcode;} 158 set_ack()159 void set_ack() {m_need_ack = true; set_mark(); } set_mark()160 void set_mark() {m_need_mark = true; } mark()161 bool mark() {return m_need_mark;} 162 163 void accept(ConstInstrVisitor& visitor) const override; 164 void accept(InstrVisitor& visitor) override; 165 166 bool is_equal_to(const RatInstr& lhs) const; 167 168 static bool emit(nir_intrinsic_instr *intr, Shader& shader); 169 170 private: 171 172 static bool emit_ssbo_load(nir_intrinsic_instr *intr, Shader& shader); 173 static bool emit_ssbo_store(nir_intrinsic_instr *intr, Shader& shader); 174 static bool emit_ssbo_atomic_op(nir_intrinsic_instr *intr, Shader& shader); 175 static bool emit_ssbo_size(nir_intrinsic_instr *intr, Shader& shader); 176 177 static bool emit_image_store(nir_intrinsic_instr *intr, Shader& shader); 178 static bool emit_image_load_or_atomic(nir_intrinsic_instr *intr, Shader& shader); 179 static bool emit_image_size(nir_intrinsic_instr *intr, Shader& shader); 180 181 bool do_ready() const override; 182 void do_print(std::ostream& os) const override; 183 184 ECFOpCode m_cf_opcode; 185 ERatOp m_rat_op; 186 187 RegisterVec4 m_data; 188 RegisterVec4 m_index; 189 PRegister m_rat_id_offset{nullptr}; 190 191 int m_rat_id{0}; 192 int m_burst_count{0}; 193 int m_comp_mask{15}; 194 int m_element_size{3}; 195 bool m_need_ack{false}; 196 bool m_need_mark{false}; 197 }; 198 199 200 } 201 202 #endif // GDSINSTR_H 203