1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_CORE_H__
34 #define __MLX5_CORE_H__
35
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/if_link.h>
40 #include <linux/firmware.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/fs.h>
43 #include <linux/mlx5/driver.h>
44
45 #define DRIVER_NAME "mlx5_core"
46 #define DRIVER_VERSION "5.0-0"
47
48 extern uint mlx5_core_debug_mask;
49
50 #define mlx5_core_dbg(__dev, format, ...) \
51 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \
52 __func__, __LINE__, current->pid, \
53 ##__VA_ARGS__)
54
55 #define mlx5_core_dbg_once(__dev, format, ...) \
56 dev_dbg_once((__dev)->device, \
57 "%s:%d:(pid %d): " format, \
58 __func__, __LINE__, current->pid, \
59 ##__VA_ARGS__)
60
61 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \
62 do { \
63 if ((mask) & mlx5_core_debug_mask) \
64 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
65 } while (0)
66
67 #define mlx5_core_err(__dev, format, ...) \
68 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \
69 __func__, __LINE__, current->pid, \
70 ##__VA_ARGS__)
71
72 #define mlx5_core_err_rl(__dev, format, ...) \
73 dev_err_ratelimited((__dev)->device, \
74 "%s:%d:(pid %d): " format, \
75 __func__, __LINE__, current->pid, \
76 ##__VA_ARGS__)
77
78 #define mlx5_core_warn(__dev, format, ...) \
79 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \
80 __func__, __LINE__, current->pid, \
81 ##__VA_ARGS__)
82
83 #define mlx5_core_warn_once(__dev, format, ...) \
84 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \
85 __func__, __LINE__, current->pid, \
86 ##__VA_ARGS__)
87
88 #define mlx5_core_warn_rl(__dev, format, ...) \
89 dev_warn_ratelimited((__dev)->device, \
90 "%s:%d:(pid %d): " format, \
91 __func__, __LINE__, current->pid, \
92 ##__VA_ARGS__)
93
94 #define mlx5_core_info(__dev, format, ...) \
95 dev_info((__dev)->device, format, ##__VA_ARGS__)
96
97 #define mlx5_core_info_rl(__dev, format, ...) \
98 dev_info_ratelimited((__dev)->device, \
99 "%s:%d:(pid %d): " format, \
100 __func__, __LINE__, current->pid, \
101 ##__VA_ARGS__)
102
mlx5_core_dma_dev(struct mlx5_core_dev * dev)103 static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev)
104 {
105 return &dev->pdev->dev;
106 }
107
108 enum {
109 MLX5_CMD_DATA, /* print command payload only */
110 MLX5_CMD_TIME, /* print command execution time */
111 };
112
113 enum {
114 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
115 MLX5_DRIVER_SYND = 0xbadd00de,
116 };
117
118 enum mlx5_semaphore_space_address {
119 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA,
120 MLX5_SEMAPHORE_SW_RESET = 0x20,
121 };
122
123 int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
124 int mlx5_query_board_id(struct mlx5_core_dev *dev);
125 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
126 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
127 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
128 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
129 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
130 void mlx5_error_sw_reset(struct mlx5_core_dev *dev);
131 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev);
132 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev);
133 void mlx5_disable_device(struct mlx5_core_dev *dev);
134 void mlx5_recover_device(struct mlx5_core_dev *dev);
135 int mlx5_sriov_init(struct mlx5_core_dev *dev);
136 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
137 int mlx5_sriov_attach(struct mlx5_core_dev *dev);
138 void mlx5_sriov_detach(struct mlx5_core_dev *dev);
139 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
140 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
141 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
142 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
143 void *context, u32 *element_id);
144 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
145 void *context, u32 element_id,
146 u32 modify_bitmask);
147 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
148 u32 element_id);
149 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
150
151 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev);
152 void mlx5_cmd_flush(struct mlx5_core_dev *dev);
153 void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
154 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
155
156 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
157 u8 access_reg_group);
158 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
159 u8 access_reg_group);
160 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
161 u8 feature_group, u8 access_reg_group);
162
163 void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
164 void mlx5_lag_remove(struct mlx5_core_dev *dev);
165
166 int mlx5_irq_table_init(struct mlx5_core_dev *dev);
167 void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev);
168 int mlx5_irq_table_create(struct mlx5_core_dev *dev);
169 void mlx5_irq_table_destroy(struct mlx5_core_dev *dev);
170 int mlx5_irq_attach_nb(struct mlx5_irq_table *irq_table, int vecidx,
171 struct notifier_block *nb);
172 int mlx5_irq_detach_nb(struct mlx5_irq_table *irq_table, int vecidx,
173 struct notifier_block *nb);
174 struct cpumask *
175 mlx5_irq_get_affinity_mask(struct mlx5_irq_table *irq_table, int vecidx);
176 struct cpu_rmap *mlx5_irq_get_rmap(struct mlx5_irq_table *table);
177 int mlx5_irq_get_num_comp(struct mlx5_irq_table *table);
178
179 int mlx5_events_init(struct mlx5_core_dev *dev);
180 void mlx5_events_cleanup(struct mlx5_core_dev *dev);
181 void mlx5_events_start(struct mlx5_core_dev *dev);
182 void mlx5_events_stop(struct mlx5_core_dev *dev);
183
184 void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
185 void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
186 void mlx5_attach_device(struct mlx5_core_dev *dev);
187 void mlx5_detach_device(struct mlx5_core_dev *dev);
188 bool mlx5_device_registered(struct mlx5_core_dev *dev);
189 void mlx5_register_device(struct mlx5_core_dev *dev);
190 void mlx5_unregister_device(struct mlx5_core_dev *dev);
191 void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
192 void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
193 struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev);
194 void mlx5_dev_list_lock(void);
195 void mlx5_dev_list_unlock(void);
196 int mlx5_dev_list_trylock(void);
197
198 bool mlx5_lag_intf_add(struct mlx5_interface *intf, struct mlx5_priv *priv);
199
200 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
201 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
202 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
203 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
204
205 struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev);
206 void mlx5_dm_cleanup(struct mlx5_core_dev *dev);
207
208 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
209 MLX5_CAP_GEN((mdev), pps_modify) && \
210 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
211 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
212
213 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw,
214 struct netlink_ext_ack *extack);
215 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
216 u32 *running_ver, u32 *stored_ver);
217
218 void mlx5e_init(void);
219 void mlx5e_cleanup(void);
220
mlx5_sriov_is_enabled(struct mlx5_core_dev * dev)221 static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
222 {
223 return pci_num_vf(dev->pdev) ? true : false;
224 }
225
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)226 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
227 {
228 /* LACP owner conditions:
229 * 1) Function is physical.
230 * 2) LAG is supported by FW.
231 * 3) LAG is managed by driver (currently the only option).
232 */
233 return MLX5_CAP_GEN(dev, vport_group_manager) &&
234 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
235 MLX5_CAP_GEN(dev, lag_master);
236 }
237
238 void mlx5_reload_interface(struct mlx5_core_dev *mdev, int protocol);
239 void mlx5_lag_update(struct mlx5_core_dev *dev);
240
241 enum {
242 MLX5_NIC_IFC_FULL = 0,
243 MLX5_NIC_IFC_DISABLED = 1,
244 MLX5_NIC_IFC_NO_DRAM_NIC = 2,
245 MLX5_NIC_IFC_SW_RESET = 7
246 };
247
248 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
249 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
250
251 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup);
252 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot);
253 #endif /* __MLX5_CORE_H__ */
254