1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
6 *
7 * Info:
8 * Contains standard defines and IDs for NAND flash devices
9 *
10 * Changelog:
11 * See git changelog.
12 */
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
15
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/flashchip.h>
19 #include <linux/mtd/bbm.h>
20 #include <linux/mtd/jedec.h>
21 #include <linux/mtd/nand.h>
22 #include <linux/mtd/onfi.h>
23 #include <linux/mutex.h>
24 #include <linux/of.h>
25 #include <linux/types.h>
26
27 struct nand_chip;
28
29 /* The maximum number of NAND chips in an array */
30 #define NAND_MAX_CHIPS 8
31
32 /*
33 * Constants for hardware specific CLE/ALE/NCE function
34 *
35 * These are bits which can be or'ed to set/clear multiple
36 * bits in one go.
37 */
38 /* Select the chip by setting nCE to low */
39 #define NAND_NCE 0x01
40 /* Select the command latch by setting CLE to high */
41 #define NAND_CLE 0x02
42 /* Select the address latch by setting ALE to high */
43 #define NAND_ALE 0x04
44
45 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
46 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
47 #define NAND_CTRL_CHANGE 0x80
48
49 /*
50 * Standard NAND flash commands
51 */
52 #define NAND_CMD_READ0 0
53 #define NAND_CMD_READ1 1
54 #define NAND_CMD_RNDOUT 5
55 #define NAND_CMD_PAGEPROG 0x10
56 #define NAND_CMD_READOOB 0x50
57 #define NAND_CMD_ERASE1 0x60
58 #define NAND_CMD_STATUS 0x70
59 #define NAND_CMD_SEQIN 0x80
60 #define NAND_CMD_RNDIN 0x85
61 #define NAND_CMD_READID 0x90
62 #define NAND_CMD_ERASE2 0xd0
63 #define NAND_CMD_PARAM 0xec
64 #define NAND_CMD_GET_FEATURES 0xee
65 #define NAND_CMD_SET_FEATURES 0xef
66 #define NAND_CMD_RESET 0xff
67
68 /* Extended commands for large page devices */
69 #define NAND_CMD_READSTART 0x30
70 #define NAND_CMD_RNDOUTSTART 0xE0
71 #define NAND_CMD_CACHEDPROG 0x15
72
73 #define NAND_CMD_NONE -1
74
75 /* Status bits */
76 #define NAND_STATUS_FAIL 0x01
77 #define NAND_STATUS_FAIL_N1 0x02
78 #define NAND_STATUS_TRUE_READY 0x20
79 #define NAND_STATUS_READY 0x40
80 #define NAND_STATUS_WP 0x80
81
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
83
84 /*
85 * Constants for Hardware ECC
86 */
87 /* Reset Hardware ECC for read */
88 #define NAND_ECC_READ 0
89 /* Reset Hardware ECC for write */
90 #define NAND_ECC_WRITE 1
91 /* Enable Hardware ECC before syndrome is read back from flash */
92 #define NAND_ECC_READSYN 2
93
94 /*
95 * Enable generic NAND 'page erased' check. This check is only done when
96 * ecc.correct() returns -EBADMSG.
97 * Set this flag if your implementation does not fix bitflips in erased
98 * pages and you want to rely on the default implementation.
99 */
100 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
101
102 /*
103 * Option constants for bizarre disfunctionality and real
104 * features.
105 */
106
107 /* Buswidth is 16 bit */
108 #define NAND_BUSWIDTH_16 BIT(1)
109
110 /*
111 * When using software implementation of Hamming, we can specify which byte
112 * ordering should be used.
113 */
114 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)
115
116 /* Chip has cache program function */
117 #define NAND_CACHEPRG BIT(3)
118 /* Options valid for Samsung large page devices */
119 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
120
121 /*
122 * Chip requires ready check on read (for auto-incremented sequential read).
123 * True only for small page devices; large page devices do not support
124 * autoincrement.
125 */
126 #define NAND_NEED_READRDY BIT(8)
127
128 /* Chip does not allow subpage writes */
129 #define NAND_NO_SUBPAGE_WRITE BIT(9)
130
131 /* Device is one of 'new' xD cards that expose fake nand command set */
132 #define NAND_BROKEN_XD BIT(10)
133
134 /* Device behaves just like nand, but is readonly */
135 #define NAND_ROM BIT(11)
136
137 /* Device supports subpage reads */
138 #define NAND_SUBPAGE_READ BIT(12)
139 /* Macros to identify the above */
140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
141
142 /*
143 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
144 * patterns.
145 */
146 #define NAND_NEED_SCRAMBLING BIT(13)
147
148 /* Device needs 3rd row address cycle */
149 #define NAND_ROW_ADDR_3 BIT(14)
150
151 /* Non chip related options */
152 /* This option skips the bbt scan during initialization. */
153 #define NAND_SKIP_BBTSCAN BIT(16)
154 /* Chip may not exist, so silence any errors in scan */
155 #define NAND_SCAN_SILENT_NODEV BIT(18)
156
157 /*
158 * Autodetect nand buswidth with readid/onfi.
159 * This suppose the driver will configure the hardware in 8 bits mode
160 * when calling nand_scan_ident, and update its configuration
161 * before calling nand_scan_tail.
162 */
163 #define NAND_BUSWIDTH_AUTO BIT(19)
164
165 /*
166 * This option could be defined by controller drivers to protect against
167 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
168 */
169 #define NAND_USES_DMA BIT(20)
170
171 /*
172 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173 * on the default ->cmdfunc() implementation, you may want to let the core
174 * handle the tCCS delay which is required when a column change (RNDIN or
175 * RNDOUT) is requested.
176 * If your controller already takes care of this delay, you don't need to set
177 * this flag.
178 */
179 #define NAND_WAIT_TCCS BIT(21)
180
181 /*
182 * Whether the NAND chip is a boot medium. Drivers might use this information
183 * to select ECC algorithms supported by the boot ROM or similar restrictions.
184 */
185 #define NAND_IS_BOOT_MEDIUM BIT(22)
186
187 /*
188 * Do not try to tweak the timings at runtime. This is needed when the
189 * controller initializes the timings on itself or when it relies on
190 * configuration done by the bootloader.
191 */
192 #define NAND_KEEP_TIMINGS BIT(23)
193
194 /*
195 * There are different places where the manufacturer stores the factory bad
196 * block markers.
197 *
198 * Position within the block: Each of these pages needs to be checked for a
199 * bad block marking pattern.
200 */
201 #define NAND_BBM_FIRSTPAGE BIT(24)
202 #define NAND_BBM_SECONDPAGE BIT(25)
203 #define NAND_BBM_LASTPAGE BIT(26)
204
205 /*
206 * Some controllers with pipelined ECC engines override the BBM marker with
207 * data or ECC bytes, thus making bad block detection through bad block marker
208 * impossible. Let's flag those chips so the core knows it shouldn't check the
209 * BBM and consider all blocks good.
210 */
211 #define NAND_NO_BBM_QUIRK BIT(27)
212
213 /* Cell info constants */
214 #define NAND_CI_CHIPNR_MSK 0x03
215 #define NAND_CI_CELLTYPE_MSK 0x0C
216 #define NAND_CI_CELLTYPE_SHIFT 2
217
218 /* Position within the OOB data of the page */
219 #define NAND_BBM_POS_SMALL 5
220 #define NAND_BBM_POS_LARGE 0
221
222 /**
223 * struct nand_parameters - NAND generic parameters from the parameter page
224 * @model: Model name
225 * @supports_set_get_features: The NAND chip supports setting/getting features
226 * @set_feature_list: Bitmap of features that can be set
227 * @get_feature_list: Bitmap of features that can be get
228 * @onfi: ONFI specific parameters
229 */
230 struct nand_parameters {
231 /* Generic parameters */
232 const char *model;
233 bool supports_set_get_features;
234 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
235 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
236
237 /* ONFI parameters */
238 struct onfi_params *onfi;
239 };
240
241 /* The maximum expected count of bytes in the NAND ID sequence */
242 #define NAND_MAX_ID_LEN 8
243
244 /**
245 * struct nand_id - NAND id structure
246 * @data: buffer containing the id bytes.
247 * @len: ID length.
248 */
249 struct nand_id {
250 u8 data[NAND_MAX_ID_LEN];
251 int len;
252 };
253
254 /**
255 * struct nand_ecc_step_info - ECC step information of ECC engine
256 * @stepsize: data bytes per ECC step
257 * @strengths: array of supported strengths
258 * @nstrengths: number of supported strengths
259 */
260 struct nand_ecc_step_info {
261 int stepsize;
262 const int *strengths;
263 int nstrengths;
264 };
265
266 /**
267 * struct nand_ecc_caps - capability of ECC engine
268 * @stepinfos: array of ECC step information
269 * @nstepinfos: number of ECC step information
270 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
271 */
272 struct nand_ecc_caps {
273 const struct nand_ecc_step_info *stepinfos;
274 int nstepinfos;
275 int (*calc_ecc_bytes)(int step_size, int strength);
276 };
277
278 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
279 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
280 static const int __name##_strengths[] = { __VA_ARGS__ }; \
281 static const struct nand_ecc_step_info __name##_stepinfo = { \
282 .stepsize = __step, \
283 .strengths = __name##_strengths, \
284 .nstrengths = ARRAY_SIZE(__name##_strengths), \
285 }; \
286 static const struct nand_ecc_caps __name = { \
287 .stepinfos = &__name##_stepinfo, \
288 .nstepinfos = 1, \
289 .calc_ecc_bytes = __calc, \
290 }
291
292 /**
293 * struct nand_ecc_ctrl - Control structure for ECC
294 * @engine_type: ECC engine type
295 * @placement: OOB bytes placement
296 * @algo: ECC algorithm
297 * @steps: number of ECC steps per page
298 * @size: data bytes per ECC step
299 * @bytes: ECC bytes per step
300 * @strength: max number of correctible bits per ECC step
301 * @total: total number of ECC bytes per page
302 * @prepad: padding information for syndrome based ECC generators
303 * @postpad: padding information for syndrome based ECC generators
304 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
305 * @priv: pointer to private ECC control data
306 * @calc_buf: buffer for calculated ECC, size is oobsize.
307 * @code_buf: buffer for ECC read from flash, size is oobsize.
308 * @hwctl: function to control hardware ECC generator. Must only
309 * be provided if an hardware ECC is available
310 * @calculate: function for ECC calculation or readback from ECC hardware
311 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
312 * Should return a positive number representing the number of
313 * corrected bitflips, -EBADMSG if the number of bitflips exceed
314 * ECC strength, or any other error code if the error is not
315 * directly related to correction.
316 * If -EBADMSG is returned the input buffers should be left
317 * untouched.
318 * @read_page_raw: function to read a raw page without ECC. This function
319 * should hide the specific layout used by the ECC
320 * controller and always return contiguous in-band and
321 * out-of-band data even if they're not stored
322 * contiguously on the NAND chip (e.g.
323 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
324 * out-of-band data).
325 * @write_page_raw: function to write a raw page without ECC. This function
326 * should hide the specific layout used by the ECC
327 * controller and consider the passed data as contiguous
328 * in-band and out-of-band data. ECC controller is
329 * responsible for doing the appropriate transformations
330 * to adapt to its specific layout (e.g.
331 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
332 * out-of-band data).
333 * @read_page: function to read a page according to the ECC generator
334 * requirements; returns maximum number of bitflips corrected in
335 * any single ECC step, -EIO hw error
336 * @read_subpage: function to read parts of the page covered by ECC;
337 * returns same as read_page()
338 * @write_subpage: function to write parts of the page covered by ECC.
339 * @write_page: function to write a page according to the ECC generator
340 * requirements.
341 * @write_oob_raw: function to write chip OOB data without ECC
342 * @read_oob_raw: function to read chip OOB data without ECC
343 * @read_oob: function to read chip OOB data
344 * @write_oob: function to write chip OOB data
345 */
346 struct nand_ecc_ctrl {
347 enum nand_ecc_engine_type engine_type;
348 enum nand_ecc_placement placement;
349 enum nand_ecc_algo algo;
350 int steps;
351 int size;
352 int bytes;
353 int total;
354 int strength;
355 int prepad;
356 int postpad;
357 unsigned int options;
358 void *priv;
359 u8 *calc_buf;
360 u8 *code_buf;
361 void (*hwctl)(struct nand_chip *chip, int mode);
362 int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
363 uint8_t *ecc_code);
364 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
365 uint8_t *calc_ecc);
366 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
367 int oob_required, int page);
368 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
369 int oob_required, int page);
370 int (*read_page)(struct nand_chip *chip, uint8_t *buf,
371 int oob_required, int page);
372 int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
373 uint32_t len, uint8_t *buf, int page);
374 int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
375 uint32_t data_len, const uint8_t *data_buf,
376 int oob_required, int page);
377 int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
378 int oob_required, int page);
379 int (*write_oob_raw)(struct nand_chip *chip, int page);
380 int (*read_oob_raw)(struct nand_chip *chip, int page);
381 int (*read_oob)(struct nand_chip *chip, int page);
382 int (*write_oob)(struct nand_chip *chip, int page);
383 };
384
385 /**
386 * struct nand_sdr_timings - SDR NAND chip timings
387 *
388 * This struct defines the timing requirements of a SDR NAND chip.
389 * These information can be found in every NAND datasheets and the timings
390 * meaning are described in the ONFI specifications:
391 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
392 * Parameters)
393 *
394 * All these timings are expressed in picoseconds.
395 *
396 * @tBERS_max: Block erase time
397 * @tCCS_min: Change column setup time
398 * @tPROG_max: Page program time
399 * @tR_max: Page read time
400 * @tALH_min: ALE hold time
401 * @tADL_min: ALE to data loading time
402 * @tALS_min: ALE setup time
403 * @tAR_min: ALE to RE# delay
404 * @tCEA_max: CE# access time
405 * @tCEH_min: CE# high hold time
406 * @tCH_min: CE# hold time
407 * @tCHZ_max: CE# high to output hi-Z
408 * @tCLH_min: CLE hold time
409 * @tCLR_min: CLE to RE# delay
410 * @tCLS_min: CLE setup time
411 * @tCOH_min: CE# high to output hold
412 * @tCS_min: CE# setup time
413 * @tDH_min: Data hold time
414 * @tDS_min: Data setup time
415 * @tFEAT_max: Busy time for Set Features and Get Features
416 * @tIR_min: Output hi-Z to RE# low
417 * @tITC_max: Interface and Timing Mode Change time
418 * @tRC_min: RE# cycle time
419 * @tREA_max: RE# access time
420 * @tREH_min: RE# high hold time
421 * @tRHOH_min: RE# high to output hold
422 * @tRHW_min: RE# high to WE# low
423 * @tRHZ_max: RE# high to output hi-Z
424 * @tRLOH_min: RE# low to output hold
425 * @tRP_min: RE# pulse width
426 * @tRR_min: Ready to RE# low (data only)
427 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
428 * rising edge of R/B#.
429 * @tWB_max: WE# high to SR[6] low
430 * @tWC_min: WE# cycle time
431 * @tWH_min: WE# high hold time
432 * @tWHR_min: WE# high to RE# low
433 * @tWP_min: WE# pulse width
434 * @tWW_min: WP# transition to WE# low
435 */
436 struct nand_sdr_timings {
437 u64 tBERS_max;
438 u32 tCCS_min;
439 u64 tPROG_max;
440 u64 tR_max;
441 u32 tALH_min;
442 u32 tADL_min;
443 u32 tALS_min;
444 u32 tAR_min;
445 u32 tCEA_max;
446 u32 tCEH_min;
447 u32 tCH_min;
448 u32 tCHZ_max;
449 u32 tCLH_min;
450 u32 tCLR_min;
451 u32 tCLS_min;
452 u32 tCOH_min;
453 u32 tCS_min;
454 u32 tDH_min;
455 u32 tDS_min;
456 u32 tFEAT_max;
457 u32 tIR_min;
458 u32 tITC_max;
459 u32 tRC_min;
460 u32 tREA_max;
461 u32 tREH_min;
462 u32 tRHOH_min;
463 u32 tRHW_min;
464 u32 tRHZ_max;
465 u32 tRLOH_min;
466 u32 tRP_min;
467 u32 tRR_min;
468 u64 tRST_max;
469 u32 tWB_max;
470 u32 tWC_min;
471 u32 tWH_min;
472 u32 tWHR_min;
473 u32 tWP_min;
474 u32 tWW_min;
475 };
476
477 /**
478 * struct nand_nvddr_timings - NV-DDR NAND chip timings
479 *
480 * This struct defines the timing requirements of a NV-DDR NAND data interface.
481 * These information can be found in every NAND datasheets and the timings
482 * meaning are described in the ONFI specifications:
483 * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf
484 * (chapter 4.18.2 NV-DDR)
485 *
486 * All these timings are expressed in picoseconds.
487 *
488 * @tBERS_max: Block erase time
489 * @tCCS_min: Change column setup time
490 * @tPROG_max: Page program time
491 * @tR_max: Page read time
492 * @tAC_min: Access window of DQ[7:0] from CLK
493 * @tAC_max: Access window of DQ[7:0] from CLK
494 * @tADL_min: ALE to data loading time
495 * @tCAD_min: Command, Address, Data delay
496 * @tCAH_min: Command/Address DQ hold time
497 * @tCALH_min: W/R_n, CLE and ALE hold time
498 * @tCALS_min: W/R_n, CLE and ALE setup time
499 * @tCAS_min: Command/address DQ setup time
500 * @tCEH_min: CE# high hold time
501 * @tCH_min: CE# hold time
502 * @tCK_min: Average clock cycle time
503 * @tCS_min: CE# setup time
504 * @tDH_min: Data hold time
505 * @tDQSCK_min: Start of the access window of DQS from CLK
506 * @tDQSCK_max: End of the access window of DQS from CLK
507 * @tDQSD_min: Min W/R_n low to DQS/DQ driven by device
508 * @tDQSD_max: Max W/R_n low to DQS/DQ driven by device
509 * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
510 * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
511 * @tDS_min: Data setup time
512 * @tDSC_min: DQS cycle time
513 * @tFEAT_max: Busy time for Set Features and Get Features
514 * @tITC_max: Interface and Timing Mode Change time
515 * @tQHS_max: Data hold skew factor
516 * @tRHW_min: Data output cycle to command, address, or data input cycle
517 * @tRR_min: Ready to RE# low (data only)
518 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
519 * rising edge of R/B#.
520 * @tWB_max: WE# high to SR[6] low
521 * @tWHR_min: WE# high to RE# low
522 * @tWRCK_min: W/R_n low to data output cycle
523 * @tWW_min: WP# transition to WE# low
524 */
525 struct nand_nvddr_timings {
526 u64 tBERS_max;
527 u32 tCCS_min;
528 u64 tPROG_max;
529 u64 tR_max;
530 u32 tAC_min;
531 u32 tAC_max;
532 u32 tADL_min;
533 u32 tCAD_min;
534 u32 tCAH_min;
535 u32 tCALH_min;
536 u32 tCALS_min;
537 u32 tCAS_min;
538 u32 tCEH_min;
539 u32 tCH_min;
540 u32 tCK_min;
541 u32 tCS_min;
542 u32 tDH_min;
543 u32 tDQSCK_min;
544 u32 tDQSCK_max;
545 u32 tDQSD_min;
546 u32 tDQSD_max;
547 u32 tDQSHZ_max;
548 u32 tDQSQ_max;
549 u32 tDS_min;
550 u32 tDSC_min;
551 u32 tFEAT_max;
552 u32 tITC_max;
553 u32 tQHS_max;
554 u32 tRHW_min;
555 u32 tRR_min;
556 u32 tRST_max;
557 u32 tWB_max;
558 u32 tWHR_min;
559 u32 tWRCK_min;
560 u32 tWW_min;
561 };
562
563 /**
564 * enum nand_interface_type - NAND interface type
565 * @NAND_SDR_IFACE: Single Data Rate interface
566 * @NAND_NVDDR_IFACE: Double Data Rate interface
567 */
568 enum nand_interface_type {
569 NAND_SDR_IFACE,
570 NAND_NVDDR_IFACE,
571 };
572
573 /**
574 * struct nand_interface_config - NAND interface timing
575 * @type: type of the timing
576 * @timings: The timing information
577 * @timings.mode: Timing mode as defined in the specification
578 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
579 * @timings.nvddr: Use it when @type is %NAND_NVDDR_IFACE.
580 */
581 struct nand_interface_config {
582 enum nand_interface_type type;
583 struct nand_timings {
584 unsigned int mode;
585 union {
586 struct nand_sdr_timings sdr;
587 struct nand_nvddr_timings nvddr;
588 };
589 } timings;
590 };
591
592 /**
593 * nand_interface_is_sdr - get the interface type
594 * @conf: The data interface
595 */
nand_interface_is_sdr(const struct nand_interface_config * conf)596 static bool nand_interface_is_sdr(const struct nand_interface_config *conf)
597 {
598 return conf->type == NAND_SDR_IFACE;
599 }
600
601 /**
602 * nand_interface_is_nvddr - get the interface type
603 * @conf: The data interface
604 */
nand_interface_is_nvddr(const struct nand_interface_config * conf)605 static bool nand_interface_is_nvddr(const struct nand_interface_config *conf)
606 {
607 return conf->type == NAND_NVDDR_IFACE;
608 }
609
610 /**
611 * nand_get_sdr_timings - get SDR timing from data interface
612 * @conf: The data interface
613 */
614 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_interface_config * conf)615 nand_get_sdr_timings(const struct nand_interface_config *conf)
616 {
617 if (!nand_interface_is_sdr(conf))
618 return ERR_PTR(-EINVAL);
619
620 return &conf->timings.sdr;
621 }
622
623 /**
624 * nand_get_nvddr_timings - get NV-DDR timing from data interface
625 * @conf: The data interface
626 */
627 static inline const struct nand_nvddr_timings *
nand_get_nvddr_timings(const struct nand_interface_config * conf)628 nand_get_nvddr_timings(const struct nand_interface_config *conf)
629 {
630 if (!nand_interface_is_nvddr(conf))
631 return ERR_PTR(-EINVAL);
632
633 return &conf->timings.nvddr;
634 }
635
636 /**
637 * struct nand_op_cmd_instr - Definition of a command instruction
638 * @opcode: the command to issue in one cycle
639 */
640 struct nand_op_cmd_instr {
641 u8 opcode;
642 };
643
644 /**
645 * struct nand_op_addr_instr - Definition of an address instruction
646 * @naddrs: length of the @addrs array
647 * @addrs: array containing the address cycles to issue
648 */
649 struct nand_op_addr_instr {
650 unsigned int naddrs;
651 const u8 *addrs;
652 };
653
654 /**
655 * struct nand_op_data_instr - Definition of a data instruction
656 * @len: number of data bytes to move
657 * @buf: buffer to fill
658 * @buf.in: buffer to fill when reading from the NAND chip
659 * @buf.out: buffer to read from when writing to the NAND chip
660 * @force_8bit: force 8-bit access
661 *
662 * Please note that "in" and "out" are inverted from the ONFI specification
663 * and are from the controller perspective, so a "in" is a read from the NAND
664 * chip while a "out" is a write to the NAND chip.
665 */
666 struct nand_op_data_instr {
667 unsigned int len;
668 union {
669 void *in;
670 const void *out;
671 } buf;
672 bool force_8bit;
673 };
674
675 /**
676 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
677 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
678 */
679 struct nand_op_waitrdy_instr {
680 unsigned int timeout_ms;
681 };
682
683 /**
684 * enum nand_op_instr_type - Definition of all instruction types
685 * @NAND_OP_CMD_INSTR: command instruction
686 * @NAND_OP_ADDR_INSTR: address instruction
687 * @NAND_OP_DATA_IN_INSTR: data in instruction
688 * @NAND_OP_DATA_OUT_INSTR: data out instruction
689 * @NAND_OP_WAITRDY_INSTR: wait ready instruction
690 */
691 enum nand_op_instr_type {
692 NAND_OP_CMD_INSTR,
693 NAND_OP_ADDR_INSTR,
694 NAND_OP_DATA_IN_INSTR,
695 NAND_OP_DATA_OUT_INSTR,
696 NAND_OP_WAITRDY_INSTR,
697 };
698
699 /**
700 * struct nand_op_instr - Instruction object
701 * @type: the instruction type
702 * @ctx: extra data associated to the instruction. You'll have to use the
703 * appropriate element depending on @type
704 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
705 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
706 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
707 * or %NAND_OP_DATA_OUT_INSTR
708 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
709 * @delay_ns: delay the controller should apply after the instruction has been
710 * issued on the bus. Most modern controllers have internal timings
711 * control logic, and in this case, the controller driver can ignore
712 * this field.
713 */
714 struct nand_op_instr {
715 enum nand_op_instr_type type;
716 union {
717 struct nand_op_cmd_instr cmd;
718 struct nand_op_addr_instr addr;
719 struct nand_op_data_instr data;
720 struct nand_op_waitrdy_instr waitrdy;
721 } ctx;
722 unsigned int delay_ns;
723 };
724
725 /*
726 * Special handling must be done for the WAITRDY timeout parameter as it usually
727 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
728 * tBERS (during an erase) which all of them are u64 values that cannot be
729 * divided by usual kernel macros and must be handled with the special
730 * DIV_ROUND_UP_ULL() macro.
731 *
732 * Cast to type of dividend is needed here to guarantee that the result won't
733 * be an unsigned long long when the dividend is an unsigned long (or smaller),
734 * which is what the compiler does when it sees ternary operator with 2
735 * different return types (picks the largest type to make sure there's no
736 * loss).
737 */
738 #define __DIVIDE(dividend, divisor) ({ \
739 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
740 DIV_ROUND_UP(dividend, divisor) : \
741 DIV_ROUND_UP_ULL(dividend, divisor)); \
742 })
743 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
744 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
745
746 #define NAND_OP_CMD(id, ns) \
747 { \
748 .type = NAND_OP_CMD_INSTR, \
749 .ctx.cmd.opcode = id, \
750 .delay_ns = ns, \
751 }
752
753 #define NAND_OP_ADDR(ncycles, cycles, ns) \
754 { \
755 .type = NAND_OP_ADDR_INSTR, \
756 .ctx.addr = { \
757 .naddrs = ncycles, \
758 .addrs = cycles, \
759 }, \
760 .delay_ns = ns, \
761 }
762
763 #define NAND_OP_DATA_IN(l, b, ns) \
764 { \
765 .type = NAND_OP_DATA_IN_INSTR, \
766 .ctx.data = { \
767 .len = l, \
768 .buf.in = b, \
769 .force_8bit = false, \
770 }, \
771 .delay_ns = ns, \
772 }
773
774 #define NAND_OP_DATA_OUT(l, b, ns) \
775 { \
776 .type = NAND_OP_DATA_OUT_INSTR, \
777 .ctx.data = { \
778 .len = l, \
779 .buf.out = b, \
780 .force_8bit = false, \
781 }, \
782 .delay_ns = ns, \
783 }
784
785 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \
786 { \
787 .type = NAND_OP_DATA_IN_INSTR, \
788 .ctx.data = { \
789 .len = l, \
790 .buf.in = b, \
791 .force_8bit = true, \
792 }, \
793 .delay_ns = ns, \
794 }
795
796 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
797 { \
798 .type = NAND_OP_DATA_OUT_INSTR, \
799 .ctx.data = { \
800 .len = l, \
801 .buf.out = b, \
802 .force_8bit = true, \
803 }, \
804 .delay_ns = ns, \
805 }
806
807 #define NAND_OP_WAIT_RDY(tout_ms, ns) \
808 { \
809 .type = NAND_OP_WAITRDY_INSTR, \
810 .ctx.waitrdy.timeout_ms = tout_ms, \
811 .delay_ns = ns, \
812 }
813
814 /**
815 * struct nand_subop - a sub operation
816 * @cs: the CS line to select for this NAND sub-operation
817 * @instrs: array of instructions
818 * @ninstrs: length of the @instrs array
819 * @first_instr_start_off: offset to start from for the first instruction
820 * of the sub-operation
821 * @last_instr_end_off: offset to end at (excluded) for the last instruction
822 * of the sub-operation
823 *
824 * Both @first_instr_start_off and @last_instr_end_off only apply to data or
825 * address instructions.
826 *
827 * When an operation cannot be handled as is by the NAND controller, it will
828 * be split by the parser into sub-operations which will be passed to the
829 * controller driver.
830 */
831 struct nand_subop {
832 unsigned int cs;
833 const struct nand_op_instr *instrs;
834 unsigned int ninstrs;
835 unsigned int first_instr_start_off;
836 unsigned int last_instr_end_off;
837 };
838
839 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
840 unsigned int op_id);
841 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
842 unsigned int op_id);
843 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
844 unsigned int op_id);
845 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
846 unsigned int op_id);
847
848 /**
849 * struct nand_op_parser_addr_constraints - Constraints for address instructions
850 * @maxcycles: maximum number of address cycles the controller can issue in a
851 * single step
852 */
853 struct nand_op_parser_addr_constraints {
854 unsigned int maxcycles;
855 };
856
857 /**
858 * struct nand_op_parser_data_constraints - Constraints for data instructions
859 * @maxlen: maximum data length that the controller can handle in a single step
860 */
861 struct nand_op_parser_data_constraints {
862 unsigned int maxlen;
863 };
864
865 /**
866 * struct nand_op_parser_pattern_elem - One element of a pattern
867 * @type: the instructuction type
868 * @optional: whether this element of the pattern is optional or mandatory
869 * @ctx: address or data constraint
870 * @ctx.addr: address constraint (number of cycles)
871 * @ctx.data: data constraint (data length)
872 */
873 struct nand_op_parser_pattern_elem {
874 enum nand_op_instr_type type;
875 bool optional;
876 union {
877 struct nand_op_parser_addr_constraints addr;
878 struct nand_op_parser_data_constraints data;
879 } ctx;
880 };
881
882 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
883 { \
884 .type = NAND_OP_CMD_INSTR, \
885 .optional = _opt, \
886 }
887
888 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
889 { \
890 .type = NAND_OP_ADDR_INSTR, \
891 .optional = _opt, \
892 .ctx.addr.maxcycles = _maxcycles, \
893 }
894
895 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
896 { \
897 .type = NAND_OP_DATA_IN_INSTR, \
898 .optional = _opt, \
899 .ctx.data.maxlen = _maxlen, \
900 }
901
902 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
903 { \
904 .type = NAND_OP_DATA_OUT_INSTR, \
905 .optional = _opt, \
906 .ctx.data.maxlen = _maxlen, \
907 }
908
909 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
910 { \
911 .type = NAND_OP_WAITRDY_INSTR, \
912 .optional = _opt, \
913 }
914
915 /**
916 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
917 * @elems: array of pattern elements
918 * @nelems: number of pattern elements in @elems array
919 * @exec: the function that will issue a sub-operation
920 *
921 * A pattern is a list of elements, each element reprensenting one instruction
922 * with its constraints. The pattern itself is used by the core to match NAND
923 * chip operation with NAND controller operations.
924 * Once a match between a NAND controller operation pattern and a NAND chip
925 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
926 * hook is called so that the controller driver can issue the operation on the
927 * bus.
928 *
929 * Controller drivers should declare as many patterns as they support and pass
930 * this list of patterns (created with the help of the following macro) to
931 * the nand_op_parser_exec_op() helper.
932 */
933 struct nand_op_parser_pattern {
934 const struct nand_op_parser_pattern_elem *elems;
935 unsigned int nelems;
936 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
937 };
938
939 #define NAND_OP_PARSER_PATTERN(_exec, ...) \
940 { \
941 .exec = _exec, \
942 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
943 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
944 sizeof(struct nand_op_parser_pattern_elem), \
945 }
946
947 /**
948 * struct nand_op_parser - NAND controller operation parser descriptor
949 * @patterns: array of supported patterns
950 * @npatterns: length of the @patterns array
951 *
952 * The parser descriptor is just an array of supported patterns which will be
953 * iterated by nand_op_parser_exec_op() everytime it tries to execute an
954 * NAND operation (or tries to determine if a specific operation is supported).
955 *
956 * It is worth mentioning that patterns will be tested in their declaration
957 * order, and the first match will be taken, so it's important to order patterns
958 * appropriately so that simple/inefficient patterns are placed at the end of
959 * the list. Usually, this is where you put single instruction patterns.
960 */
961 struct nand_op_parser {
962 const struct nand_op_parser_pattern *patterns;
963 unsigned int npatterns;
964 };
965
966 #define NAND_OP_PARSER(...) \
967 { \
968 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
969 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
970 sizeof(struct nand_op_parser_pattern), \
971 }
972
973 /**
974 * struct nand_operation - NAND operation descriptor
975 * @cs: the CS line to select for this NAND operation
976 * @instrs: array of instructions to execute
977 * @ninstrs: length of the @instrs array
978 *
979 * The actual operation structure that will be passed to chip->exec_op().
980 */
981 struct nand_operation {
982 unsigned int cs;
983 const struct nand_op_instr *instrs;
984 unsigned int ninstrs;
985 };
986
987 #define NAND_OPERATION(_cs, _instrs) \
988 { \
989 .cs = _cs, \
990 .instrs = _instrs, \
991 .ninstrs = ARRAY_SIZE(_instrs), \
992 }
993
994 int nand_op_parser_exec_op(struct nand_chip *chip,
995 const struct nand_op_parser *parser,
996 const struct nand_operation *op, bool check_only);
997
nand_op_trace(const char * prefix,const struct nand_op_instr * instr)998 static inline void nand_op_trace(const char *prefix,
999 const struct nand_op_instr *instr)
1000 {
1001 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
1002 switch (instr->type) {
1003 case NAND_OP_CMD_INSTR:
1004 pr_debug("%sCMD [0x%02x]\n", prefix,
1005 instr->ctx.cmd.opcode);
1006 break;
1007 case NAND_OP_ADDR_INSTR:
1008 pr_debug("%sADDR [%d cyc: %*ph]\n", prefix,
1009 instr->ctx.addr.naddrs,
1010 instr->ctx.addr.naddrs < 64 ?
1011 instr->ctx.addr.naddrs : 64,
1012 instr->ctx.addr.addrs);
1013 break;
1014 case NAND_OP_DATA_IN_INSTR:
1015 pr_debug("%sDATA_IN [%d B%s]\n", prefix,
1016 instr->ctx.data.len,
1017 instr->ctx.data.force_8bit ?
1018 ", force 8-bit" : "");
1019 break;
1020 case NAND_OP_DATA_OUT_INSTR:
1021 pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
1022 instr->ctx.data.len,
1023 instr->ctx.data.force_8bit ?
1024 ", force 8-bit" : "");
1025 break;
1026 case NAND_OP_WAITRDY_INSTR:
1027 pr_debug("%sWAITRDY [max %d ms]\n", prefix,
1028 instr->ctx.waitrdy.timeout_ms);
1029 break;
1030 }
1031 #endif
1032 }
1033
1034 /**
1035 * struct nand_controller_ops - Controller operations
1036 *
1037 * @attach_chip: this method is called after the NAND detection phase after
1038 * flash ID and MTD fields such as erase size, page size and OOB
1039 * size have been set up. ECC requirements are available if
1040 * provided by the NAND chip or device tree. Typically used to
1041 * choose the appropriate ECC configuration and allocate
1042 * associated resources.
1043 * This hook is optional.
1044 * @detach_chip: free all resources allocated/claimed in
1045 * nand_controller_ops->attach_chip().
1046 * This hook is optional.
1047 * @exec_op: controller specific method to execute NAND operations.
1048 * This method replaces chip->legacy.cmdfunc(),
1049 * chip->legacy.{read,write}_{buf,byte,word}(),
1050 * chip->legacy.dev_ready() and chip->legacy.waifunc().
1051 * @setup_interface: setup the data interface and timing. If chipnr is set to
1052 * %NAND_DATA_IFACE_CHECK_ONLY this means the configuration
1053 * should not be applied but only checked.
1054 * This hook is optional.
1055 */
1056 struct nand_controller_ops {
1057 int (*attach_chip)(struct nand_chip *chip);
1058 void (*detach_chip)(struct nand_chip *chip);
1059 int (*exec_op)(struct nand_chip *chip,
1060 const struct nand_operation *op,
1061 bool check_only);
1062 int (*setup_interface)(struct nand_chip *chip, int chipnr,
1063 const struct nand_interface_config *conf);
1064 };
1065
1066 /**
1067 * struct nand_controller - Structure used to describe a NAND controller
1068 *
1069 * @lock: lock used to serialize accesses to the NAND controller
1070 * @ops: NAND controller operations.
1071 */
1072 struct nand_controller {
1073 struct mutex lock;
1074 const struct nand_controller_ops *ops;
1075 };
1076
nand_controller_init(struct nand_controller * nfc)1077 static inline void nand_controller_init(struct nand_controller *nfc)
1078 {
1079 mutex_init(&nfc->lock);
1080 }
1081
1082 /**
1083 * struct nand_legacy - NAND chip legacy fields/hooks
1084 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device
1085 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device
1086 * @select_chip: select/deselect a specific target/die
1087 * @read_byte: read one byte from the chip
1088 * @write_byte: write a single byte to the chip on the low 8 I/O lines
1089 * @write_buf: write data from the buffer to the chip
1090 * @read_buf: read data from the chip into the buffer
1091 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used
1092 * to write command and address
1093 * @cmdfunc: hardware specific function for writing commands to the chip.
1094 * @dev_ready: hardware specific function for accessing device ready/busy line.
1095 * If set to NULL no access to ready/busy is available and the
1096 * ready/busy information is read from the chip status register.
1097 * @waitfunc: hardware specific function for wait on ready.
1098 * @block_bad: check if a block is bad, using OOB markers
1099 * @block_markbad: mark a block bad
1100 * @set_features: set the NAND chip features
1101 * @get_features: get the NAND chip features
1102 * @chip_delay: chip dependent delay for transferring data from array to read
1103 * regs (tR).
1104 * @dummy_controller: dummy controller implementation for drivers that can
1105 * only control a single chip
1106 *
1107 * If you look at this structure you're already wrong. These fields/hooks are
1108 * all deprecated.
1109 */
1110 struct nand_legacy {
1111 void __iomem *IO_ADDR_R;
1112 void __iomem *IO_ADDR_W;
1113 void (*select_chip)(struct nand_chip *chip, int cs);
1114 u8 (*read_byte)(struct nand_chip *chip);
1115 void (*write_byte)(struct nand_chip *chip, u8 byte);
1116 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
1117 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);
1118 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
1119 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
1120 int page_addr);
1121 int (*dev_ready)(struct nand_chip *chip);
1122 int (*waitfunc)(struct nand_chip *chip);
1123 int (*block_bad)(struct nand_chip *chip, loff_t ofs);
1124 int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
1125 int (*set_features)(struct nand_chip *chip, int feature_addr,
1126 u8 *subfeature_para);
1127 int (*get_features)(struct nand_chip *chip, int feature_addr,
1128 u8 *subfeature_para);
1129 int chip_delay;
1130 struct nand_controller dummy_controller;
1131 };
1132
1133 /**
1134 * struct nand_chip_ops - NAND chip operations
1135 * @suspend: Suspend operation
1136 * @resume: Resume operation
1137 * @lock_area: Lock operation
1138 * @unlock_area: Unlock operation
1139 * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1140 * @choose_interface_config: Choose the best interface configuration
1141 */
1142 struct nand_chip_ops {
1143 int (*suspend)(struct nand_chip *chip);
1144 void (*resume)(struct nand_chip *chip);
1145 int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1146 int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1147 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
1148 int (*choose_interface_config)(struct nand_chip *chip,
1149 struct nand_interface_config *iface);
1150 };
1151
1152 /**
1153 * struct nand_manufacturer - NAND manufacturer structure
1154 * @desc: The manufacturer description
1155 * @priv: Private information for the manufacturer driver
1156 */
1157 struct nand_manufacturer {
1158 const struct nand_manufacturer_desc *desc;
1159 void *priv;
1160 };
1161
1162 /**
1163 * struct nand_chip - NAND Private Flash Chip Data
1164 * @base: Inherit from the generic NAND device
1165 * @id: Holds NAND ID
1166 * @parameters: Holds generic parameters under an easily readable form
1167 * @manufacturer: Manufacturer information
1168 * @ops: NAND chip operations
1169 * @legacy: All legacy fields/hooks. If you develop a new driver, don't even try
1170 * to use any of these fields/hooks, and if you're modifying an
1171 * existing driver that is using those fields/hooks, you should
1172 * consider reworking the driver and avoid using them.
1173 * @options: Various chip options. They can partly be set to inform nand_scan
1174 * about special functionality. See the defines for further
1175 * explanation.
1176 * @current_interface_config: The currently used NAND interface configuration
1177 * @best_interface_config: The best NAND interface configuration which fits both
1178 * the NAND chip and NAND controller constraints. If
1179 * unset, the default reset interface configuration must
1180 * be used.
1181 * @bbt_erase_shift: Number of address bits in a bbt entry
1182 * @bbt_options: Bad block table specific options. All options used here must
1183 * come from bbm.h. By default, these options will be copied to
1184 * the appropriate nand_bbt_descr's.
1185 * @badblockpos: Bad block marker position in the oob area
1186 * @badblockbits: Minimum number of set bits in a good block's bad block marker
1187 * position; i.e., BBM = 11110111b is good when badblockbits = 7
1188 * @bbt_td: Bad block table descriptor for flash lookup
1189 * @bbt_md: Bad block table mirror descriptor
1190 * @badblock_pattern: Bad block scan pattern used for initial bad block scan
1191 * @bbt: Bad block table pointer
1192 * @page_shift: Number of address bits in a page (column address bits)
1193 * @phys_erase_shift: Number of address bits in a physical eraseblock
1194 * @chip_shift: Number of address bits in one chip
1195 * @pagemask: Page number mask = number of (pages / chip) - 1
1196 * @subpagesize: Holds the subpagesize
1197 * @data_buf: Buffer for data, size is (page size + oobsize)
1198 * @oob_poi: pointer on the OOB area covered by data_buf
1199 * @pagecache: Structure containing page cache related fields
1200 * @pagecache.bitflips: Number of bitflips of the cached page
1201 * @pagecache.page: Page number currently in the cache. -1 means no page is
1202 * currently cached
1203 * @buf_align: Minimum buffer alignment required by a platform
1204 * @lock: Lock protecting the suspended field. Also used to serialize accesses
1205 * to the NAND device
1206 * @suspended: Set to 1 when the device is suspended, 0 when it's not
1207 * @resume_wq: wait queue to sleep if rawnand is in suspended state.
1208 * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1209 * should always have cur_cs >= 0 && cur_cs < nanddev_ntargets().
1210 * NAND Controller drivers should not modify this value, but they're
1211 * allowed to read it.
1212 * @read_retries: The number of read retry modes supported
1213 * @controller: The hardware controller structure which is shared among multiple
1214 * independent devices
1215 * @ecc: The ECC controller structure
1216 * @priv: Chip private data
1217 */
1218 struct nand_chip {
1219 struct nand_device base;
1220 struct nand_id id;
1221 struct nand_parameters parameters;
1222 struct nand_manufacturer manufacturer;
1223 struct nand_chip_ops ops;
1224 struct nand_legacy legacy;
1225 unsigned int options;
1226
1227 /* Data interface */
1228 const struct nand_interface_config *current_interface_config;
1229 struct nand_interface_config *best_interface_config;
1230
1231 /* Bad block information */
1232 unsigned int bbt_erase_shift;
1233 unsigned int bbt_options;
1234 unsigned int badblockpos;
1235 unsigned int badblockbits;
1236 struct nand_bbt_descr *bbt_td;
1237 struct nand_bbt_descr *bbt_md;
1238 struct nand_bbt_descr *badblock_pattern;
1239 u8 *bbt;
1240
1241 /* Device internal layout */
1242 unsigned int page_shift;
1243 unsigned int phys_erase_shift;
1244 unsigned int chip_shift;
1245 unsigned int pagemask;
1246 unsigned int subpagesize;
1247
1248 /* Buffers */
1249 u8 *data_buf;
1250 u8 *oob_poi;
1251 struct {
1252 unsigned int bitflips;
1253 int page;
1254 } pagecache;
1255 unsigned long buf_align;
1256
1257 /* Internals */
1258 struct mutex lock;
1259 unsigned int suspended : 1;
1260 wait_queue_head_t resume_wq;
1261 int cur_cs;
1262 int read_retries;
1263
1264 /* Externals */
1265 struct nand_controller *controller;
1266 struct nand_ecc_ctrl ecc;
1267 void *priv;
1268 };
1269
mtd_to_nand(struct mtd_info * mtd)1270 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1271 {
1272 return container_of(mtd, struct nand_chip, base.mtd);
1273 }
1274
nand_to_mtd(struct nand_chip * chip)1275 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1276 {
1277 return &chip->base.mtd;
1278 }
1279
nand_get_controller_data(struct nand_chip * chip)1280 static inline void *nand_get_controller_data(struct nand_chip *chip)
1281 {
1282 return chip->priv;
1283 }
1284
nand_set_controller_data(struct nand_chip * chip,void * priv)1285 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1286 {
1287 chip->priv = priv;
1288 }
1289
nand_set_manufacturer_data(struct nand_chip * chip,void * priv)1290 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1291 void *priv)
1292 {
1293 chip->manufacturer.priv = priv;
1294 }
1295
nand_get_manufacturer_data(struct nand_chip * chip)1296 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1297 {
1298 return chip->manufacturer.priv;
1299 }
1300
nand_set_flash_node(struct nand_chip * chip,struct device_node * np)1301 static inline void nand_set_flash_node(struct nand_chip *chip,
1302 struct device_node *np)
1303 {
1304 mtd_set_of_node(nand_to_mtd(chip), np);
1305 }
1306
nand_get_flash_node(struct nand_chip * chip)1307 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1308 {
1309 return mtd_get_of_node(nand_to_mtd(chip));
1310 }
1311
1312 /**
1313 * nand_get_interface_config - Retrieve the current interface configuration
1314 * of a NAND chip
1315 * @chip: The NAND chip
1316 */
1317 static inline const struct nand_interface_config *
nand_get_interface_config(struct nand_chip * chip)1318 nand_get_interface_config(struct nand_chip *chip)
1319 {
1320 return chip->current_interface_config;
1321 }
1322
1323 /*
1324 * A helper for defining older NAND chips where the second ID byte fully
1325 * defined the chip, including the geometry (chip size, eraseblock size, page
1326 * size). All these chips have 512 bytes NAND page size.
1327 */
1328 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1329 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1330 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1331
1332 /*
1333 * A helper for defining newer chips which report their page size and
1334 * eraseblock size via the extended ID bytes.
1335 *
1336 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1337 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1338 * device ID now only represented a particular total chip size (and voltage,
1339 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1340 * using the same device ID.
1341 */
1342 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1343 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1344 .options = (opts) }
1345
1346 #define NAND_ECC_INFO(_strength, _step) \
1347 { .strength_ds = (_strength), .step_ds = (_step) }
1348 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1349 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1350
1351 /**
1352 * struct nand_flash_dev - NAND Flash Device ID Structure
1353 * @name: a human-readable name of the NAND chip
1354 * @dev_id: the device ID (the second byte of the full chip ID array)
1355 * @mfr_id: manufacturer ID part of the full chip ID array (refers the same
1356 * memory address as ``id[0]``)
1357 * @dev_id: device ID part of the full chip ID array (refers the same memory
1358 * address as ``id[1]``)
1359 * @id: full device ID array
1360 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1361 * well as the eraseblock size) is determined from the extended NAND
1362 * chip ID array)
1363 * @chipsize: total chip size in MiB
1364 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1365 * @options: stores various chip bit options
1366 * @id_len: The valid length of the @id.
1367 * @oobsize: OOB size
1368 * @ecc: ECC correctability and step information from the datasheet.
1369 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1370 * @ecc_strength_ds in nand_chip{}.
1371 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1372 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1373 * For example, the "4bit ECC for each 512Byte" can be set with
1374 * NAND_ECC_INFO(4, 512).
1375 */
1376 struct nand_flash_dev {
1377 char *name;
1378 union {
1379 struct {
1380 uint8_t mfr_id;
1381 uint8_t dev_id;
1382 };
1383 uint8_t id[NAND_MAX_ID_LEN];
1384 };
1385 unsigned int pagesize;
1386 unsigned int chipsize;
1387 unsigned int erasesize;
1388 unsigned int options;
1389 uint16_t id_len;
1390 uint16_t oobsize;
1391 struct {
1392 uint16_t strength_ds;
1393 uint16_t step_ds;
1394 } ecc;
1395 };
1396
1397 int nand_create_bbt(struct nand_chip *chip);
1398
1399 /*
1400 * Check if it is a SLC nand.
1401 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1402 * We do not distinguish the MLC and TLC now.
1403 */
nand_is_slc(struct nand_chip * chip)1404 static inline bool nand_is_slc(struct nand_chip *chip)
1405 {
1406 WARN(nanddev_bits_per_cell(&chip->base) == 0,
1407 "chip->bits_per_cell is used uninitialized\n");
1408 return nanddev_bits_per_cell(&chip->base) == 1;
1409 }
1410
1411 /**
1412 * Check if the opcode's address should be sent only on the lower 8 bits
1413 * @command: opcode to check
1414 */
nand_opcode_8bits(unsigned int command)1415 static inline int nand_opcode_8bits(unsigned int command)
1416 {
1417 switch (command) {
1418 case NAND_CMD_READID:
1419 case NAND_CMD_PARAM:
1420 case NAND_CMD_GET_FEATURES:
1421 case NAND_CMD_SET_FEATURES:
1422 return 1;
1423 default:
1424 break;
1425 }
1426 return 0;
1427 }
1428
1429 int nand_check_erased_ecc_chunk(void *data, int datalen,
1430 void *ecc, int ecclen,
1431 void *extraoob, int extraooblen,
1432 int threshold);
1433
1434 int nand_ecc_choose_conf(struct nand_chip *chip,
1435 const struct nand_ecc_caps *caps, int oobavail);
1436
1437 /* Default write_oob implementation */
1438 int nand_write_oob_std(struct nand_chip *chip, int page);
1439
1440 /* Default read_oob implementation */
1441 int nand_read_oob_std(struct nand_chip *chip, int page);
1442
1443 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1444 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
1445 u8 *subfeature_param);
1446
1447 /* read_page_raw implementations */
1448 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
1449 int page);
1450 int nand_monolithic_read_page_raw(struct nand_chip *chip, uint8_t *buf,
1451 int oob_required, int page);
1452
1453 /* write_page_raw implementations */
1454 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1455 int oob_required, int page);
1456 int nand_monolithic_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1457 int oob_required, int page);
1458
1459 /* Reset and initialize a NAND device */
1460 int nand_reset(struct nand_chip *chip, int chipnr);
1461
1462 /* NAND operation helpers */
1463 int nand_reset_op(struct nand_chip *chip);
1464 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1465 unsigned int len);
1466 int nand_status_op(struct nand_chip *chip, u8 *status);
1467 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1468 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1469 unsigned int offset_in_page, void *buf, unsigned int len);
1470 int nand_change_read_column_op(struct nand_chip *chip,
1471 unsigned int offset_in_page, void *buf,
1472 unsigned int len, bool force_8bit);
1473 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1474 unsigned int offset_in_page, void *buf, unsigned int len);
1475 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1476 unsigned int offset_in_page, const void *buf,
1477 unsigned int len);
1478 int nand_prog_page_end_op(struct nand_chip *chip);
1479 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1480 unsigned int offset_in_page, const void *buf,
1481 unsigned int len);
1482 int nand_change_write_column_op(struct nand_chip *chip,
1483 unsigned int offset_in_page, const void *buf,
1484 unsigned int len, bool force_8bit);
1485 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1486 bool force_8bit, bool check_only);
1487 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1488 unsigned int len, bool force_8bit);
1489
1490 /* Scan and identify a NAND device */
1491 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips,
1492 struct nand_flash_dev *ids);
1493
nand_scan(struct nand_chip * chip,unsigned int max_chips)1494 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips)
1495 {
1496 return nand_scan_with_ids(chip, max_chips, NULL);
1497 }
1498
1499 /* Internal helper for board drivers which need to override command function */
1500 void nand_wait_ready(struct nand_chip *chip);
1501
1502 /*
1503 * Free resources held by the NAND device, must be called on error after a
1504 * sucessful nand_scan().
1505 */
1506 void nand_cleanup(struct nand_chip *chip);
1507
1508 /*
1509 * External helper for controller drivers that have to implement the WAITRDY
1510 * instruction and have no physical pin to check it.
1511 */
1512 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1513 struct gpio_desc;
1514 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
1515 unsigned long timeout_ms);
1516
1517 /* Select/deselect a NAND target. */
1518 void nand_select_target(struct nand_chip *chip, unsigned int cs);
1519 void nand_deselect_target(struct nand_chip *chip);
1520
1521 /* Bitops */
1522 void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
1523 unsigned int src_off, unsigned int nbits);
1524
1525 /**
1526 * nand_get_data_buf() - Get the internal page buffer
1527 * @chip: NAND chip object
1528 *
1529 * Returns the pre-allocated page buffer after invalidating the cache. This
1530 * function should be used by drivers that do not want to allocate their own
1531 * bounce buffer and still need such a buffer for specific operations (most
1532 * commonly when reading OOB data only).
1533 *
1534 * Be careful to never call this function in the write/write_oob path, because
1535 * the core may have placed the data to be written out in this buffer.
1536 *
1537 * Return: pointer to the page cache buffer
1538 */
nand_get_data_buf(struct nand_chip * chip)1539 static inline void *nand_get_data_buf(struct nand_chip *chip)
1540 {
1541 chip->pagecache.page = -1;
1542
1543 return chip->data_buf;
1544 }
1545
1546 #endif /* __LINUX_MTD_RAWNAND_H */
1547