1@/* 2@ * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved. 3@ * 4@ * UniProton is licensed under Mulan PSL v2. 5@ * You can use this software according to the terms and conditions of the Mulan PSL v2. 6@ * You may obtain a copy of Mulan PSL v2 at: 7@ * http://license.coscl.org.cn/MulanPSL2 8@ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 9@ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 10@ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 11@ * See the Mulan PSL v2 for more details. 12@ * Create: 2009-12-22 13@ * Description: exc汇编文件 14@ */ 15 .align 8 16 17 .section .text, "ax" 18 .thumb 19 .syntax unified 20 21 .global OsExcNmi 22 .global OsExcHardFault 23 .global OsExcMemFault 24 .global OsExcBusFault 25 .global OsExcUsageFault 26 .global OsExcSvcCall 27 28 .type OsExcNmi, function 29 .type OsExcHardFault, function 30 .type OsExcMemFault, function 31 .type OsExcBusFault, function 32 .type OsExcUsageFault, function 33 .type OsExcSvcCall, function 34 35 .extern OsExcHandleEntryM4 36 .extern g_uniFlag 37 .extern g_curNestCount 38 39OS_FLG_BGD_ACTIVE = 0x0002 40OS_FLG_MSP_ACTIVE = 0x001D 41 42@exc return using floating-point state flag 43OS_FPU_SAVE_FLAG = 0x10 44 45@hardware push SP len 46OS_FPU_PUSH_SP_AUTO = 104 @auto save 18 float registers(S0~S15,CPSR,REV,SP 8bytes align) add 8 normal R registers,(18 + 8) * 4 47OS_NORMAL_PUSH_SP_AUTO = 32 @auto save 8 normal R registers(xPSR, PC, LR, R12,R0~R3),8*4 48 49@exception type 50NO_BMU_FAULT = 0 51BF_STKERR = 1 52BF_UNSTKERR = 2 53BF_IMPRECISERR = 3 54BF_PRECISERR = 4 55BF_IBUSERR = 5 56 57MF_MSTKERR = 6 58MF_MUNSTKERR = 7 59MF_DACCVIOL = 8 60MF_IACCVIOL = 9 61 62UF_DIVBYZERO = 10 63UF_UNALIGNED = 11 64UF_NOCP = 12 65UF_INVPC = 13 66UF_INVSTATE = 14 67UF_UNDEFINSTR = 15 68 69OS_EXC_CAUSE_NMI = 16 70OS_EXC_CAUSE_HARDFAULT = 17 71 72HF_DBGEVT = 19 73HF_VECTBL = 20 74 75FLAG_ADDR_VALID = 0x10000 76 77@if bit2 = 1,then ret use psp 78OS_FALG_EXC_RET_PSP_STATUS = 0x4 79 80@UsageFault:0x030F; BusFault:0x1F(clear BFARVALID bit); MemFault:0x1B(clear MMARVALID bit) 81OS_BMU_FAULT_CLEAR_BIT = 0x030F1F1B 82 83@Fault Reg valid exception bit 84OS_BMU_FAULT_VALID_BIT = 0x030F9F9B 85OS_HARD_FAULT_VAILD_BIT = 0xC0000002 86 87OS_NVIC_FSR = 0xE000ED28 @include BusFault/MemFault/UsageFault State Regeister 88OS_NVIC_HFSR = 0xE000ED2C @HardFault State Regeister 89OS_NVIC_BFAR = 0xE000ED38 90OS_NVIC_MMAR = 0xE000ED34 91OS_NVIC_ACT_BASE = 0xE000E300 92 93excTbl: 94 .byte 0,0,0,0,0,0,UF_DIVBYZERO,UF_UNALIGNED 95 .byte 0,0,0,0,UF_NOCP,UF_INVPC,UF_INVSTATE,UF_UNDEFINSTR 96 .byte 0,0,0,BF_STKERR,BF_UNSTKERR,BF_IMPRECISERR,BF_PRECISERR,BF_IBUSERR 97 .byte 0,0,0,MF_MSTKERR,MF_MUNSTKERR,0,MF_DACCVIOL,MF_IACCVIOL 98 .byte NO_BMU_FAULT,0,0,0 99 100OsExcNmi: 101 MOV R0, #OS_EXC_CAUSE_NMI 102 MOV R1, #0 103 B OsExcDispatch 104 105OsExcHardFault: 106 MOV R0, #OS_EXC_CAUSE_HARDFAULT 107 LDR R2, =OS_NVIC_HFSR 108 LDR R2, [R2] 109 110 MOV R1, #HF_DBGEVT 111 LSL R1, R1, #0x8 112 ORR R0, R1 113 TST R2, #0x80000000 114 BNE OsExcDispatch @ DBGEVT 115 116 AND R0, #0x000000FF 117 MOV R1, #HF_VECTBL 118 LSL R1, R1, #0x8 119 ORR R0, R1 120 TST R2, #0x00000002 @ bit1 indicates the fault of VECTBL 121 BNE OsExcDispatch @ VECTBL 122 123 @if not DBGEVT and VECTBL then is FORCED 124 AND R0, #0x000000FF 125 126 LDR R2, =OS_NVIC_FSR 127 LDR R2, [R2] 128 129 TST R2, #0x8000 @ BFARVALID 130 BNE _HFBusFault @ BusFault 131 132 TST R2, #0x80 @ MMARVALID 133 BNE _HFMemFault @ MemFault 134 135 MOV R12,#0 136 B OsHFExcCommonBMU 137 138_HFBusFault: 139 LDR R1, =OS_NVIC_BFAR 140 LDR R1, [R1] 141 MOV R12, #FLAG_ADDR_VALID 142 B OsHFExcCommonBMU 143 144_HFMemFault: 145 LDR R1, =OS_NVIC_MMAR 146 LDR R1, [R1] 147 MOV R12, #FLAG_ADDR_VALID 148 149OsHFExcCommonBMU: 150 LDR R3, =OS_BMU_FAULT_CLEAR_BIT 151 AND R2, R3 152 CLZ R2, R2 @ NO_BMU_FAULT,when hard fault happen, no BMU fault(CFSR(R2) = 0, CLZ R2, R2 -> R2 = 32) 153 LDR R3, =excTbl 154 ADD R3, R3, R2 155 LDRB R2, [R3] 156 LSL R2, R2, #0x8 @ORR R0, R2, LSL #0x8 157 ORR R0, R2 158 ORR R0, R12 159 B OsExcDispatch 160 161OsExcSvcCall: 162 TST LR, #0x4 @exc_return bit2 163 MRSEQ R0, MSP @msp->R0 164 MRSNE R0, PSP @psp->R0 165 LDR R1, [R0,#24] @exc pc->R1 166 LDRB R0, [R1,#-2] @get para0 from instrution SVC 167 MOV R1, #0 168 B OsExcDispatch 169 170OsExcBusFault: 171 LDR R0, =OS_NVIC_FSR 172 LDR R0, [R0] 173 174 TST R0, #0x8000 @ BFARVALID 175 BEQ _ExcBusNoADDR 176 LDR R1, =OS_NVIC_BFAR 177 LDR R1, [R1] 178 MOV R12, #FLAG_ADDR_VALID 179 180 B OsExcCommonBMU 181 182_ExcBusNoADDR: 183 MOV R12,#0 184 B OsExcCommonBMU 185 186OsExcMemFault: 187 LDR R0, =OS_NVIC_FSR 188 LDR R0, [R0] 189 190 TST R0, #0x80 @ MMARVALID 191 BEQ _ExcMemNoADDR 192 LDR R1, =OS_NVIC_MMAR 193 LDR R1, [R1] 194 MOV R12, #FLAG_ADDR_VALID 195 196 B OsExcCommonBMU 197 198_ExcMemNoADDR: 199 MOV R12,#0 200 B OsExcCommonBMU 201 202OsExcUsageFault: 203 LDR R0, =OS_NVIC_FSR 204 LDR R0, [R0] 205 206 @clear UsageFault invalid bit 207 MOV R12, #0 208 209OsExcCommonBMU: 210 LDR R3, =OS_BMU_FAULT_CLEAR_BIT 211 AND R0, R3 212 CLZ R0, R0 213 LDR R3, =excTbl 214 ADD R3, R3, R0 215 LDRB R0, [R3] 216 ORR R0, R0, R12 217 218@ R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid), R1 -- EXCADDR 219OsExcDispatch: 220 @ Clear Exeption status Reg 221 LDR R2, =OS_NVIC_FSR 222 LDR R3, =OS_BMU_FAULT_VALID_BIT 223 STR R3, [R2] 224 225 @Clear Hardfault status Reg 226 LDR R2, =OS_NVIC_HFSR 227 LDR R3, =OS_HARD_FAULT_VAILD_BIT 228 STR R3, [R2] 229 230 @ exc occured in Task or Init ,interrupt, or exc 231 @ reserved for register info from task stack 232 MOV R2, R14 @MSP:LR bit2 is 0; PSP:LR bit2 is 1 233 TST R2, #OS_FALG_EXC_RET_PSP_STATUS 234 BEQ _ExcInMSP @ exc occured in MSP stack 235 B _ExcInPSP @ exc occured in PSP stack 236 237_ExcInMSP: 238 ADD R3, R13, #OS_NORMAL_PUSH_SP_AUTO @ xPSR, PC, LR, R12,R0~R3 hardware save,8*4 bytes 239 TST LR, #OS_FPU_SAVE_FLAG @ Is the MSP using the floating-point state? 240 BNE _MspStoreExcReg 241 ADD R3, R13, #OS_FPU_PUSH_SP_AUTO @ xPSR, PC, LR, R12,R0~R3 and float register hardware save 242 243_MspStoreExcReg: 244 PUSH {R3} @ store message-->exc: MSP(R13),save IRQ SP 245 MRS R12, BASEPRI @ store message-->exc: disable int? 246 PUSH {R4-R12} @ store message-->exc: {R4-R12} 247 248 B _handleEntry 249 250_ExcInPSP: 251 @ exc occured in Task 252 MOV R2, R13 253 SUB R13, #OS_NORMAL_PUSH_SP_AUTO @ first add 8*4 Bytes Revs (for Reg. STMFD xPSR, PC, LR, R12,R0~R3) 254 255 MRS R3, PSP @ get psp 256 257 ADD R12, R3, #OS_NORMAL_PUSH_SP_AUTO @ xPSR, PC, LR, R12,R0~R3 hardware save,8*4 bytes 258 TST LR, #OS_FPU_SAVE_FLAG @ Is the PSP using the floating-point state? 259 BNE _PspStoreExcReg 260 ADD R12, R3, #OS_FPU_PUSH_SP_AUTO @ xPSR, PC, LR, R12,R0~R3 and float register hardware save 261 262_PspStoreExcReg: 263 PUSH {R12} @ save task SP 264 265 MRS R12, BASEPRI 266 PUSH {R4-R12} @ save R4~R11,BASEPRI to MSP 267 268 @ copy auto saved task register(xPSR, PC, LR, R12,R0~R3)from psp stack 269 LDMFD R3, {R4-R11} @ R4-R11 store PSP reg(auto push xPSR, PC, LR, R12,R0~R3 when exc in task) 270 STMFD R2!, {R4-R11} 271 272_handleEntry: 273 MOV R2, R13 @ R13:the 3th param 274 B OsExcHandleEntryM4 275 276 NOP 277 .align 278 .end 279