1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 *
5 * vineetg: May 2011
6 * -Folded PAGE_PRESENT (used by VM) and PAGE_VALID (used by MMU) into 1.
7 * They are semantically the same although in different contexts
8 * VALID marks a TLB entry exists and it will only happen if PRESENT
9 * - Utilise some unused free bits to confine PTE flags to 12 bits
10 * This is a must for 4k pg-sz
11 *
12 * vineetg: Mar 2011 - changes to accommodate MMU TLB Page Descriptor mods
13 * -TLB Locking never really existed, except for initial specs
14 * -SILENT_xxx not needed for our port
15 * -Per my request, MMU V3 changes the layout of some of the bits
16 * to avoid a few shifts in TLB Miss handlers.
17 *
18 * vineetg: April 2010
19 * -PGD entry no longer contains any flags. If empty it is 0, otherwise has
20 * Pg-Tbl ptr. Thus pmd_present(), pmd_valid(), pmd_set( ) become simpler
21 *
22 * vineetg: April 2010
23 * -Switched form 8:11:13 split for page table lookup to 11:8:13
24 * -this speeds up page table allocation itself as we now have to memset 1K
25 * instead of 8k per page table.
26 * -TODO: Right now page table alloc is 8K and rest 7K is unused
27 * need to optimise it
28 *
29 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
30 */
31
32 #ifndef _ASM_ARC_PGTABLE_H
33 #define _ASM_ARC_PGTABLE_H
34
35 #include <linux/bits.h>
36 #include <asm-generic/pgtable-nopmd.h>
37 #include <asm/page.h>
38 #include <asm/mmu.h> /* to propagate CONFIG_ARC_MMU_VER <n> */
39
40 /**************************************************************************
41 * Page Table Flags
42 *
43 * ARC700 MMU only deals with softare managed TLB entries.
44 * Page Tables are purely for Linux VM's consumption and the bits below are
45 * suited to that (uniqueness). Hence some are not implemented in the TLB and
46 * some have different value in TLB.
47 * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible because they live in
48 * seperate PD0 and PD1, which combined forms a translation entry)
49 * while for PTE perspective, they are 8 and 9 respectively
50 * with MMU v3: Most bits (except SHARED) represent the exact hardware pos
51 * (saves some bit shift ops in TLB Miss hdlrs)
52 */
53
54 #if (CONFIG_ARC_MMU_VER <= 2)
55
56 #define _PAGE_ACCESSED (1<<1) /* Page is accessed (S) */
57 #define _PAGE_CACHEABLE (1<<2) /* Page is cached (H) */
58 #define _PAGE_EXECUTE (1<<3) /* Page has user execute perm (H) */
59 #define _PAGE_WRITE (1<<4) /* Page has user write perm (H) */
60 #define _PAGE_READ (1<<5) /* Page has user read perm (H) */
61 #define _PAGE_DIRTY (1<<6) /* Page modified (dirty) (S) */
62 #define _PAGE_SPECIAL (1<<7)
63 #define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
64 #define _PAGE_PRESENT (1<<10) /* TLB entry is valid (H) */
65
66 #else /* MMU v3 onwards */
67
68 #define _PAGE_CACHEABLE (1<<0) /* Page is cached (H) */
69 #define _PAGE_EXECUTE (1<<1) /* Page has user execute perm (H) */
70 #define _PAGE_WRITE (1<<2) /* Page has user write perm (H) */
71 #define _PAGE_READ (1<<3) /* Page has user read perm (H) */
72 #define _PAGE_ACCESSED (1<<4) /* Page is accessed (S) */
73 #define _PAGE_DIRTY (1<<5) /* Page modified (dirty) (S) */
74 #define _PAGE_SPECIAL (1<<6)
75
76 #if (CONFIG_ARC_MMU_VER >= 4)
77 #define _PAGE_WTHRU (1<<7) /* Page cache mode write-thru (H) */
78 #endif
79
80 #define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
81 #define _PAGE_PRESENT (1<<9) /* TLB entry is valid (H) */
82
83 #if (CONFIG_ARC_MMU_VER >= 4)
84 #define _PAGE_HW_SZ (1<<10) /* Page Size indicator (H): 0 normal, 1 super */
85 #endif
86
87 #define _PAGE_SHARED_CODE (1<<11) /* Shared Code page with cmn vaddr
88 usable for shared TLB entries (H) */
89
90 #define _PAGE_UNUSED_BIT (1<<12)
91 #endif
92
93 /* vmalloc permissions */
94 #define _K_PAGE_PERMS (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ | \
95 _PAGE_GLOBAL | _PAGE_PRESENT)
96
97 #ifndef CONFIG_ARC_CACHE_PAGES
98 #undef _PAGE_CACHEABLE
99 #define _PAGE_CACHEABLE 0
100 #endif
101
102 #ifndef _PAGE_HW_SZ
103 #define _PAGE_HW_SZ 0
104 #endif
105
106 /* Defaults for every user page */
107 #define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)
108
109 /* Set of bits not changed in pte_modify */
110 #define _PAGE_CHG_MASK (PAGE_MASK_PHYS | _PAGE_ACCESSED | _PAGE_DIRTY | \
111 _PAGE_SPECIAL)
112 /* More Abbrevaited helpers */
113 #define PAGE_U_NONE __pgprot(___DEF)
114 #define PAGE_U_R __pgprot(___DEF | _PAGE_READ)
115 #define PAGE_U_W_R __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE)
116 #define PAGE_U_X_R __pgprot(___DEF | _PAGE_READ | _PAGE_EXECUTE)
117 #define PAGE_U_X_W_R __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE | \
118 _PAGE_EXECUTE)
119
120 #define PAGE_SHARED PAGE_U_W_R
121
122 /* While kernel runs out of unstranslated space, vmalloc/modules use a chunk of
123 * user vaddr space - visible in all addr spaces, but kernel mode only
124 * Thus Global, all-kernel-access, no-user-access, cached
125 */
126 #define PAGE_KERNEL __pgprot(_K_PAGE_PERMS | _PAGE_CACHEABLE)
127
128 /* ioremap */
129 #define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
130
131 /* Masks for actual TLB "PD"s */
132 #define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ)
133 #define PTE_BITS_RWX (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
134
135 #define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS | _PAGE_CACHEABLE)
136
137 /**************************************************************************
138 * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
139 *
140 * Certain cases have 1:1 mapping
141 * e.g. __P101 means VM_READ, VM_EXEC and !VM_SHARED
142 * which directly corresponds to PAGE_U_X_R
143 *
144 * Other rules which cause the divergence from 1:1 mapping
145 *
146 * 1. Although ARC700 can do exclusive execute/write protection (meaning R
147 * can be tracked independet of X/W unlike some other CPUs), still to
148 * keep things consistent with other archs:
149 * -Write implies Read: W => R
150 * -Execute implies Read: X => R
151 *
152 * 2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
153 * This is to enable COW mechanism
154 */
155 /* xwr */
156 #define __P000 PAGE_U_NONE
157 #define __P001 PAGE_U_R
158 #define __P010 PAGE_U_R /* Pvt-W => !W */
159 #define __P011 PAGE_U_R /* Pvt-W => !W */
160 #define __P100 PAGE_U_X_R /* X => R */
161 #define __P101 PAGE_U_X_R
162 #define __P110 PAGE_U_X_R /* Pvt-W => !W and X => R */
163 #define __P111 PAGE_U_X_R /* Pvt-W => !W */
164
165 #define __S000 PAGE_U_NONE
166 #define __S001 PAGE_U_R
167 #define __S010 PAGE_U_W_R /* W => R */
168 #define __S011 PAGE_U_W_R
169 #define __S100 PAGE_U_X_R /* X => R */
170 #define __S101 PAGE_U_X_R
171 #define __S110 PAGE_U_X_W_R /* X => R */
172 #define __S111 PAGE_U_X_W_R
173
174 /****************************************************************
175 * 2 tier (PGD:PTE) software page walker
176 *
177 * [31] 32 bit virtual address [0]
178 * -------------------------------------------------------
179 * | | <------------ PGDIR_SHIFT ----------> |
180 * | | |
181 * | BITS_FOR_PGD | BITS_FOR_PTE | <-- PAGE_SHIFT --> |
182 * -------------------------------------------------------
183 * | | |
184 * | | --> off in page frame
185 * | ---> index into Page Table
186 * ----> index into Page Directory
187 *
188 * In a single page size configuration, only PAGE_SHIFT is fixed
189 * So both PGD and PTE sizing can be tweaked
190 * e.g. 8K page (PAGE_SHIFT 13) can have
191 * - PGDIR_SHIFT 21 -> 11:8:13 address split
192 * - PGDIR_SHIFT 24 -> 8:11:13 address split
193 *
194 * If Super Page is configured, PGDIR_SHIFT becomes fixed too,
195 * so the sizing flexibility is gone.
196 */
197
198 #if defined(CONFIG_ARC_HUGEPAGE_16M)
199 #define PGDIR_SHIFT 24
200 #elif defined(CONFIG_ARC_HUGEPAGE_2M)
201 #define PGDIR_SHIFT 21
202 #else
203 /*
204 * Only Normal page support so "hackable" (see comment above)
205 * Default value provides 11:8:13 (8K), 11:9:12 (4K)
206 */
207 #define PGDIR_SHIFT 21
208 #endif
209
210 #define BITS_FOR_PTE (PGDIR_SHIFT - PAGE_SHIFT)
211 #define BITS_FOR_PGD (32 - PGDIR_SHIFT)
212
213 #define PGDIR_SIZE BIT(PGDIR_SHIFT) /* vaddr span, not PDG sz */
214 #define PGDIR_MASK (~(PGDIR_SIZE-1))
215
216 #define PTRS_PER_PTE BIT(BITS_FOR_PTE)
217 #define PTRS_PER_PGD BIT(BITS_FOR_PGD)
218
219 /*
220 * Number of entries a user land program use.
221 * TASK_SIZE is the maximum vaddr that can be used by a userland program.
222 */
223 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
224
225 /*
226 * No special requirements for lowest virtual address we permit any user space
227 * mapping to be mapped at.
228 */
229 #define FIRST_USER_ADDRESS 0UL
230
231
232 /****************************************************************
233 * Bucket load of VM Helpers
234 */
235
236 #ifndef __ASSEMBLY__
237
238 #define pte_ERROR(e) \
239 pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
240 #define pgd_ERROR(e) \
241 pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
242
243 /* the zero page used for uninitialized and anonymous pages */
244 extern char empty_zero_page[PAGE_SIZE];
245 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
246
247 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
248 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
249
250 /* find the page descriptor of the Page Tbl ref by PMD entry */
251 #define pmd_page(pmd) virt_to_page(pmd_val(pmd) & PAGE_MASK)
252
253 /* find the logical addr (phy for ARC) of the Page Tbl ref by PMD entry */
254 #define pmd_page_vaddr(pmd) (pmd_val(pmd) & PAGE_MASK)
255
256 /* In a 2 level sys, setup the PGD entry with PTE value */
pmd_set(pmd_t * pmdp,pte_t * ptep)257 static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
258 {
259 pmd_val(*pmdp) = (unsigned long)ptep;
260 }
261
262 #define pte_none(x) (!pte_val(x))
263 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
264 #define pte_clear(mm, addr, ptep) set_pte_at(mm, addr, ptep, __pte(0))
265
266 #define pmd_none(x) (!pmd_val(x))
267 #define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK))
268 #define pmd_present(x) (pmd_val(x))
269 #define pmd_leaf(x) (pmd_val(x) & _PAGE_HW_SZ)
270 #define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
271
272 #define pte_page(pte) pfn_to_page(pte_pfn(pte))
273 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
274 #define pfn_pte(pfn, prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
275
276 /* Don't use virt_to_pfn for macros below: could cause truncations for PAE40*/
277 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
278
279 /* Zoo of pte_xxx function */
280 #define pte_read(pte) (pte_val(pte) & _PAGE_READ)
281 #define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
282 #define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
283 #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
284 #define pte_special(pte) (pte_val(pte) & _PAGE_SPECIAL)
285
286 #define PTE_BIT_FUNC(fn, op) \
287 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
288
289 PTE_BIT_FUNC(mknotpresent, &= ~(_PAGE_PRESENT));
290 PTE_BIT_FUNC(wrprotect, &= ~(_PAGE_WRITE));
291 PTE_BIT_FUNC(mkwrite, |= (_PAGE_WRITE));
292 PTE_BIT_FUNC(mkclean, &= ~(_PAGE_DIRTY));
293 PTE_BIT_FUNC(mkdirty, |= (_PAGE_DIRTY));
294 PTE_BIT_FUNC(mkold, &= ~(_PAGE_ACCESSED));
295 PTE_BIT_FUNC(mkyoung, |= (_PAGE_ACCESSED));
296 PTE_BIT_FUNC(exprotect, &= ~(_PAGE_EXECUTE));
297 PTE_BIT_FUNC(mkexec, |= (_PAGE_EXECUTE));
298 PTE_BIT_FUNC(mkspecial, |= (_PAGE_SPECIAL));
299 PTE_BIT_FUNC(mkhuge, |= (_PAGE_HW_SZ));
300
pte_modify(pte_t pte,pgprot_t newprot)301 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
302 {
303 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
304 }
305
306 /* Macro to mark a page protection as uncacheable */
307 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))
308
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pteval)309 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
310 pte_t *ptep, pte_t pteval)
311 {
312 set_pte(ptep, pteval);
313 }
314
315 /*
316 * Macro to quickly access the PGD entry, utlising the fact that some
317 * arch may cache the pointer to Page Directory of "current" task
318 * in a MMU register
319 *
320 * Thus task->mm->pgd (3 pointer dereferences, cache misses etc simply
321 * becomes read a register
322 *
323 * ********CAUTION*******:
324 * Kernel code might be dealing with some mm_struct of NON "current"
325 * Thus use this macro only when you are certain that "current" is current
326 * e.g. when dealing with signal frame setup code etc
327 */
328 #ifdef ARC_USE_SCRATCH_REG
329 #define pgd_offset_fast(mm, addr) \
330 ({ \
331 pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0); \
332 pgd_base + pgd_index(addr); \
333 })
334 #else
335 #define pgd_offset_fast(mm, addr) pgd_offset(mm, addr)
336 #endif
337
338 extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE);
339 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
340 pte_t *ptep);
341
342 /* Encode swap {type,off} tuple into PTE
343 * We reserve 13 bits for 5-bit @type, keeping bits 12-5 zero, ensuring that
344 * PAGE_PRESENT is zero in a PTE holding swap "identifier"
345 */
346 #define __swp_entry(type, off) ((swp_entry_t) { \
347 ((type) & 0x1f) | ((off) << 13) })
348
349 /* Decode a PTE containing swap "identifier "into constituents */
350 #define __swp_type(pte_lookalike) (((pte_lookalike).val) & 0x1f)
351 #define __swp_offset(pte_lookalike) ((pte_lookalike).val >> 13)
352
353 /* NOPs, to keep generic kernel happy */
354 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
355 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
356
357 #define kern_addr_valid(addr) (1)
358
359 /*
360 * remap a physical page `pfn' of size `size' with page protection `prot'
361 * into virtual address `from'
362 */
363 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
364 #include <asm/hugepage.h>
365 #endif
366
367 /* to cope with aliasing VIPT cache */
368 #define HAVE_ARCH_UNMAPPED_AREA
369
370 #endif /* __ASSEMBLY__ */
371
372 #endif
373