1 /* 2 * Copyright © 2022 Imagination Technologies Ltd. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #ifndef PVR_ROGUE_PDS_DEFS_H 25 #define PVR_ROGUE_PDS_DEFS_H 26 27 #include <stdint.h> 28 29 /* Instruction type C */ 30 #define PVR_ROGUE_PDSINST_OPCODEC_MASK (0x0000000FU) 31 /* 64 bit add*/ 32 #define PVR_ROGUE_PDSINST_OPCODEC_ADD64 UINT32_C(0x00000008) 33 /* 32 bit add*/ 34 #define PVR_ROGUE_PDSINST_OPCODEC_ADD32 UINT32_C(0x00000009) 35 /* Shift and/or Logic Operation (64 bit)*/ 36 #define PVR_ROGUE_PDSINST_OPCODEC_SFTLP64 UINT32_C(0x0000000a) 37 /* Compare and set predicate*/ 38 #define PVR_ROGUE_PDSINST_OPCODEC_CMP UINT32_C(0x0000000b) 39 /* Branch and/or select predicate*/ 40 #define PVR_ROGUE_PDSINST_OPCODEC_BRA UINT32_C(0x0000000c) 41 /* Umbrella OpcodeSP instructions*/ 42 #define PVR_ROGUE_PDSINST_OPCODEC_SP UINT32_C(0x0000000d) 43 /* Multiply Accumulate with DOUD*/ 44 #define PVR_ROGUE_PDSINST_OPCODEC_DDMAD UINT32_C(0x0000000e) 45 /* DOUT Command*/ 46 #define PVR_ROGUE_PDSINST_OPCODEC_DOUT UINT32_C(0x0000000f) 47 48 /* Logical Operation */ 49 #define PVR_ROGUE_PDSINST_LOP_MASK (0x00000007U) 50 #define PVR_ROGUE_PDSINST_LOP_NONE (0x00000000U) 51 #define PVR_ROGUE_PDSINST_LOP_NOT (0x00000001U) 52 #define PVR_ROGUE_PDSINST_LOP_AND (0x00000002U) 53 #define PVR_ROGUE_PDSINST_LOP_OR (0x00000003U) 54 #define PVR_ROGUE_PDSINST_LOP_XOR (0x00000004U) 55 #define PVR_ROGUE_PDSINST_LOP_XNOR (0x00000005U) 56 #define PVR_ROGUE_PDSINST_LOP_NAND (0x00000006U) 57 #define PVR_ROGUE_PDSINST_LOP_NOR (0x00000007U) 58 59 /* 64-bit Source Temps and Persistent Temps. */ 60 #define PVR_ROGUE_PDSINST_REGS64TP_MASK (0x0000001FU) 61 #define PVR_ROGUE_PDSINST_REGS64TP_TEMP64 (0U) 62 #define PVR_ROGUE_PDSINST_REGS64TP_TEMP64_LOWER (0U) 63 #define PVR_ROGUE_PDSINST_REGS64TP_TEMP64_UPPER (15U) 64 #define PVR_ROGUE_PDSINST_REGS64TP_PTEMP64 (1U) 65 #define PVR_ROGUE_PDSINST_REGS64TP_PTEMP64_LOWER (16U) 66 #define PVR_ROGUE_PDSINST_REGS64TP_PTEMP64_UPPER (31U) 67 68 /* 32-bit Registers - 32-bit aligned. */ 69 #define PVR_ROGUE_PDSINST_REGS32_MASK (0x000000FFU) 70 #define PVR_ROGUE_PDSINST_REGS32_CONST32 (0U) 71 #define PVR_ROGUE_PDSINST_REGS32_CONST32_LOWER (0U) 72 #define PVR_ROGUE_PDSINST_REGS32_CONST32_UPPER (127U) 73 #define PVR_ROGUE_PDSINST_REGS32_TEMP32 (1U) 74 #define PVR_ROGUE_PDSINST_REGS32_TEMP32_LOWER (128U) 75 #define PVR_ROGUE_PDSINST_REGS32_TEMP32_UPPER (159U) 76 #define PVR_ROGUE_PDSINST_REGS32_PTEMP32 (2U) 77 #define PVR_ROGUE_PDSINST_REGS32_PTEMP32_LOWER (192U) 78 #define PVR_ROGUE_PDSINST_REGS32_PTEMP32_UPPER (223U) 79 80 /* cc ? if im then 81 * cc ? dst = (*src0 lop *src1) << src2 82 * cc ? else 83 * cc ? dst = (*src0 lop *src1) << *src2 84 * 85 * Take the logical operation of the 2 sources, and shift to a 64 bit result. 86 * For unary operator NOT, *src0 is taken as the logical operand; for operator 87 * NONE, an unmodified *src0 is shifted. If IM is set use SFT as a direct shift 88 * value, otherwise use an address to obtain the shift value. The shift value 89 * (SRC2) is treated as a 2's complement encoded signed value. A negative value 90 * encodes a right shift. Values are clamped to the range [-63,63]. 91 */ 92 #define PVR_ROGUE_PDSINST_SFTLP64_OPCODE_SHIFT (28U) 93 #define PVR_ROGUE_PDSINST_SFTLP64_OPCODE_CLRMSK (0x0FFFFFFFU) 94 #define PVR_ROGUE_PDSINST_SFTLP64_OPCODE_DEFAULT (0xA0000000U) /* SFTLP64 */ 95 #define PVR_ROGUE_PDSINST_SFTLP64_CC_SHIFT (27U) 96 #define PVR_ROGUE_PDSINST_SFTLP64_CC_CLRMSK (0xF7FFFFFFU) 97 #define PVR_ROGUE_PDSINST_SFTLP64_CC_ENABLE (0x08000000U) 98 #define PVR_ROGUE_PDSINST_SFTLP64_LOP_SHIFT (24U) 99 #define PVR_ROGUE_PDSINST_SFTLP64_IM_SHIFT (23U) 100 #define PVR_ROGUE_PDSINST_SFTLP64_IM_ENABLE (0x00800000U) 101 #define PVR_ROGUE_PDSINST_SFTLP64_SRC0_SHIFT (18U) 102 #define PVR_ROGUE_PDSINST_SFTLP64_SRC1_SHIFT (13U) 103 #define PVR_ROGUE_PDSINST_SFTLP64_SRC2_SHIFT (5U) 104 #define PVR_ROGUE_PDSINST_SFTLP64_DST_SHIFT (0U) 105 106 /* Instruction type B */ 107 #define PVR_ROGUE_PDSINST_OPCODEB_MASK (0x00000007U) 108 /* Shift and/or Logic Operation (32 bit) */ 109 #define PVR_ROGUE_PDSINST_OPCODEB_SFTLP32 UINT32_C(0x00000002) 110 /* Vertex Stream Out DMA Command */ 111 #define PVR_ROGUE_PDSINST_OPCODEB_STM UINT32_C(0x00000003) 112 113 /* 32-bit Source Temps. */ 114 #define PVR_ROGUE_PDSINST_REGS32T_MASK (0x0000001FU) 115 #define PVR_ROGUE_PDSINST_REGS32T_TEMP32 (0U) 116 #define PVR_ROGUE_PDSINST_REGS32T_TEMP32_LOWER (0U) 117 #define PVR_ROGUE_PDSINST_REGS32T_TEMP32_UPPER (31U) 118 119 /* 32-bit Source Temps and Persistent Temps. */ 120 #define PVR_ROGUE_PDSINST_REGS32TP_MASK (0x0000003FU) 121 #define PVR_ROGUE_PDSINST_REGS32TP_TEMP32 (0U) 122 #define PVR_ROGUE_PDSINST_REGS32TP_TEMP32_LOWER (0U) 123 #define PVR_ROGUE_PDSINST_REGS32TP_TEMP32_UPPER (31U) 124 #define PVR_ROGUE_PDSINST_REGS32TP_PTEMP32 (1U) 125 #define PVR_ROGUE_PDSINST_REGS32TP_PTEMP32_LOWER (32U) 126 #define PVR_ROGUE_PDSINST_REGS32TP_PTEMP32_UPPER (63U) 127 128 /* cc ? if im then 129 * cc ? dst = (*src0 lop *src1) << src2 130 * cc ? else 131 * cc ? dst = (*src0 lop *src1) << *src2 132 * 133 * Take the logical operation of the 2 sources, and shift to a 32 bit result. 134 * For unary operator NOT, *src0 is taken as the logical operand; for operator 135 * NONE, an unmodified *src0 is shifted.If IM is set, use the shift value SFT 136 * (SRC2) as a direct shift value, otherwise use an address to obtain the shift 137 * value. SFT (SRC2) is treated as a 2's complement encoded signed value. A 138 * negative value encodes a right shift. Values are clamped to the range 139 * [-31,31]. 140 */ 141 #define PVR_ROGUE_PDSINST_SFTLP32_OPCODE_SHIFT (29U) 142 #define PVR_ROGUE_PDSINST_SFTLP32_OPCODE_CLRMSK (0x1FFFFFFFU) 143 #define PVR_ROGUE_PDSINST_SFTLP32_OPCODE_DEFAULT (0x40000000U) /* SFTLP32 */ 144 #define PVR_ROGUE_PDSINST_SFTLP32_IM_SHIFT (28U) 145 #define PVR_ROGUE_PDSINST_SFTLP32_IM_ENABLE (0x10000000U) 146 #define PVR_ROGUE_PDSINST_SFTLP32_CC_SHIFT (27U) 147 #define PVR_ROGUE_PDSINST_SFTLP32_CC_ENABLE (0x08000000U) 148 #define PVR_ROGUE_PDSINST_SFTLP32_LOP_SHIFT (24U) 149 #define PVR_ROGUE_PDSINST_SFTLP32_SRC0_SHIFT (19U) 150 #define PVR_ROGUE_PDSINST_SFTLP32_SRC1_SHIFT (11U) 151 #define PVR_ROGUE_PDSINST_SFTLP32_SRC2_SHIFT (5U) 152 #define PVR_ROGUE_PDSINST_SFTLP32_DST_SHIFT (0U) 153 154 /* The stream being processed within the vertex, selects 1 of 4 streams. */ 155 #define PVR_ROGUE_PDSINST_SO_MASK (0x00000003U) 156 157 /* An instruction to enable the 'Streaming Out' of data to memory. 158 * 159 * This instruction can only be used when called from a Stream Output Program 160 * (see 161 * 162 * Stream output configuration words, as it reads its source data from unified 163 * vertex store within the TA. 164 * 165 * Stream Out programs use the vertex data master, but are called from the TA. 166 * They do not execute on the USC. If synchronization is required with the 167 * control stream to the next draw call, a DOUTV command must be used when 168 * stream out finishes for the current draw call. The VDM must have a 169 * corresponding entry in the control stream indicating when it should wait for 170 * the PDS. 171 * 172 * As SRC0, SRC1 needs to be held from program to program it is assumed these 173 * are in persistent temps. There are 32 (dword) persistent temps, 8 of which 174 * are required to support 4 streams. The driver needs to manage the allocation 175 * of these. If the value needs to be carried from one geometry job to another, 176 * it will need to be loaded from memory at the start of the geometry job, and 177 * stored at the end of it (using a state program in the input control stream). 178 * 179 * When a new buffer is altered which was in use, the driver will need to fence 180 * in order to make sure that the preceding operation have completed before the 181 * persistent temps are updated. 182 * 183 * It is assumed that the USC compiler will optimize the stream order to keep 184 * data which is contiguous in the output vertex (going to memory) 185 * together. This will enable multiple words to be streamed out in a single 186 * DMA. This will reduce the processing load on the TA. 187 * 188 * The sources are read from within the constant, temporary stores of the PDS, 189 * and have the following meaning. 190 * 191 * If the buffer is being appended to then persistent constants need to be 192 * stored to memory at the end of the geometry job, and reloaded at the start 193 * of the next job (as another context may be run). 194 * 195 * ccs ? if (so_address + (so_vosize * so_primtype)) <= so_limit then 196 * 197 * dma the data from the vbg, and write it into memory. so_vioff is 198 * an offset into the current vertex. 199 * ccs ? for (so_vertex=0 ; so_vertex < so_primtype; so_vertex++) 200 * ccs ? for (i=0 ; i < so_dmasize; i++) 201 * ccs ? *(so_address + so_vooff + i + (so_vertex * so_vosize)) = 202 * readvertexvbg(so_vioff + i + (so_vertex * stream_size)) 203 * 204 * ccs ? if so_eop then 205 * ccs ? so_address = so_address + (so_vosize * so_primtype) 206 * ccs ? so_primwritten = so_primwritten + 1 207 * ccs ? 208 * end if 209 * 210 * ccs ? else 211 * 212 * ccs ? setp(so_overflow_predicate[so]) 213 * ccs ? [so_overflow_predicate[global]] 214 * 215 * ccs ? end if 216 * 217 * if so_eop then 218 * so_primneeded = so_primneeded + 1 219 * end if 220 * 221 * The VBG presents a stream when outputted from the shader. A bit is set in the 222 * input register indicating which stream is present. The PDS is called on a per 223 * primitive basis. In simple geometry this is per input triangle, strip etc., 224 * in geometry shader land this is per output primitive from the geometry 225 * shader. Primitives are unraveled to remove vertex sharing. The PDS is called 226 * in submission order. The PDS program needs to be written for the primitive 227 * which is being emitted. 228 * 229 * Example 230 * 231 * Data is actually going into three buffers (this is defined elsewhere). 232 * SO_VERTEX0.Pos.XY -> buffer0 233 * SO_VERTEX0.Mult.XY -> buffer0 234 * SO_VERTEX1.Add.XY -> buffer1 235 * 236 * SO_VERTEX0.Pos.ZW -> buffer2 237 * 238 * Persistent temps: 239 * pt0 = Buffer0 start address; 240 * pt1 = Buffer1 start address; 241 * pt2 = Buffer2 start address; 242 * pt3 = 0 (buffer0 primwritten/needed) 243 * pt4 = 0 (buffer1 primwritten/needed) 244 * pt5 = 0 (buffer2 primwritten/needed) 245 * 246 * Constants: 247 * c0 = Buffer 0 top 248 * c1 = Buffer 1 top 249 * c2 = Buffer 2 top 250 * c3 = SRC2,3 for Pos.XY: VOOFF = 0, DMASIZE = 2, SO_VIOFF = 0, EOP = 0 251 * c4 = SRC2,3 for Mult: VOSIZE = 4, VOOFF = 2, DMASIZE = 2, SO_VIOFF = 2, EOP = 252 * 1 c5 = SRC2,3 for Pos.ZW: VOSIZE=2, VOOFF = 0, DMASIZE = 2, SO_VIOFF = 0, EOP 253 * = 1 c6 = SRC2,3 for Add: VOSIZE=2, VOOFF = 0, DMASIZE = 2, SO_VIOFF = 0, EOP 254 * = 1 255 * 256 * ifstream0 { 257 * 258 * # Write Pos.XY 259 * STM SO=0, SRC3=c0, SRC2=c3, SRC1=pt3, SRC0=pt0 260 * STM SO=0, SRC3=c0, SRC2=c4, SRC1=pt3, SRC0=pt0 261 * #Write Pos.ZW to buffer 1 and advance 262 * STM SO=0, SRC3=c2, SRC2=c5, SRC1=pt5, SRC0=pt2 263 * 264 * } 265 * 266 * else if stream1 { 267 * 268 * #Write Add to buffer 1 and advance 269 * STM S0=1, SRC3=c1, SRC2=c6, SRC1=pt4, SRC0=pt1 270 * 271 * } 272 */ 273 #define PVR_ROGUE_PDSINST_STM_OPCODE_SHIFT (29U) 274 #define PVR_ROGUE_PDSINST_STM_CCS_CCS_GLOBAL_SHIFT (28U) 275 #define PVR_ROGUE_PDSINST_STM_CCS_CCS_SO_SHIFT (27U) 276 #define PVR_ROGUE_PDSINST_STM_CCS_CCS_CC_SHIFT (26U) 277 #define PVR_ROGUE_PDSINST_STM_SO_TST_SHIFT (25U) 278 #define PVR_ROGUE_PDSINST_STM_SO_SHIFT (23U) 279 #define PVR_ROGUE_PDSINST_STM_SO_SRC0_SHIFT (18U) 280 #define PVR_ROGUE_PDSINST_STM_SO_SRC1_SHIFT (13U) 281 #define PVR_ROGUE_PDSINST_STM_SO_SRC2_SHIFT (5U) 282 #define PVR_ROGUE_PDSINST_STM_SO_SRC3_SHIFT (0U) 283 284 /* Multiple Accumulate */ 285 #define PVR_ROGUE_PDSINST_OPCODEA_MAD UINT32_C(0x00000000) 286 287 /* ALU Mode */ 288 289 /* ALU will perform unsigned math.*/ 290 #define PVR_ROGUE_PDSINST_ALUM_UNSIGNED (0x00000000U) 291 292 /* 64-bit Registers - 64-bit aligned */ 293 #define PVR_ROGUE_PDSINST_REGS64_MASK (0x0000007FU) 294 #define PVR_ROGUE_PDSINST_REGS64_CONST64 (0U) 295 #define PVR_ROGUE_PDSINST_REGS64_CONST64_LOWER (0U) 296 #define PVR_ROGUE_PDSINST_REGS64_CONST64_UPPER (63U) 297 #define PVR_ROGUE_PDSINST_REGS64_TEMP64 (1U) 298 #define PVR_ROGUE_PDSINST_REGS64_TEMP64_LOWER (64U) 299 #define PVR_ROGUE_PDSINST_REGS64_TEMP64_UPPER (79U) 300 #define PVR_ROGUE_PDSINST_REGS64_PTEMP64 (2U) 301 #define PVR_ROGUE_PDSINST_REGS64_PTEMP64_LOWER (96U) 302 #define PVR_ROGUE_PDSINST_REGS64_PTEMP64_UPPER (111U) 303 304 /* 64-bit Temps 0-15 Destination */ 305 #define PVR_ROGUE_PDSINST_REGS64T_MASK (0x0000000FU) 306 #define PVR_ROGUE_PDSINST_REGS64T_TEMP64 (0U) 307 #define PVR_ROGUE_PDSINST_REGS64T_TEMP64_LOWER (0U) 308 #define PVR_ROGUE_PDSINST_REGS64T_TEMP64_UPPER (15U) 309 310 /* cc ? dst = (src0 * src1) + (src2 * -1sna) + cin 311 * 312 * Multiply 2 source 32 bit numbers to generate a 64 bit result, then add or 313 * subtract a third source. Conditionally takes in a carry in. Always generates 314 * a carry out which is held in the status register. 315 */ 316 #define PVR_ROGUE_PDSINST_MAD_OPCODE_SHIFT (30U) 317 #define PVR_ROGUE_PDSINST_MAD_SNA_SHIFT (29U) 318 #define PVR_ROGUE_PDSINST_MAD_SNA_ADD (0x00000000U) 319 #define PVR_ROGUE_PDSINST_MAD_SNA_SUB (0x20000000U) 320 #define PVR_ROGUE_PDSINST_MAD_ALUM_SHIFT (28U) 321 #define PVR_ROGUE_PDSINST_MAD_ALUM_SIGNED (0x10000000U) 322 #define PVR_ROGUE_PDSINST_MAD_CC_SHIFT (27U) 323 #define PVR_ROGUE_PDSINST_MAD_CC_ENABLE (0x08000000U) 324 /* 32-bit source to multiply - 32-bit range. */ 325 #define PVR_ROGUE_PDSINST_MAD_SRC0_SHIFT (19U) 326 /* 32-bit source to multiply - 32-bit range */ 327 #define PVR_ROGUE_PDSINST_MAD_SRC1_SHIFT (11U) 328 /* 64-bit source to add - 64-bit range */ 329 #define PVR_ROGUE_PDSINST_MAD_SRC2_SHIFT (4U) 330 #define PVR_ROGUE_PDSINST_MAD_DST_SHIFT (0U) 331 332 /* cc ? dst = src0 + (src1 * -1sna) + cin 333 * 334 * Add or subtract 2 64 bit numbers. Conditionally takes in a carry in. Always 335 * generates a carry out which is held in the status register. 336 */ 337 #define PVR_ROGUE_PDSINST_ADD64_OPCODE_SHIFT (28U) 338 #define PVR_ROGUE_PDSINST_ADD64_CC_SHIFT (27U) 339 #define PVR_ROGUE_PDSINST_ADD64_CC_ENABLE (0x08000000U) 340 #define PVR_ROGUE_PDSINST_ADD64_ALUM_SHIFT (26U) 341 #define PVR_ROGUE_PDSINST_ADD64_ALUM_SIGNED (0x04000000U) 342 #define PVR_ROGUE_PDSINST_ADD64_SNA_SHIFT (24U) 343 #define PVR_ROGUE_PDSINST_ADD64_SNA_SUB (0x01000000U) 344 345 /* 64-bit source to add. */ 346 #define PVR_ROGUE_PDSINST_ADD64_SRC0_SHIFT (12U) 347 348 /* 64-bit source to add */ 349 #define PVR_ROGUE_PDSINST_ADD64_SRC1_SHIFT (5U) 350 351 /* 64-bit temp or persistent temp */ 352 #define PVR_ROGUE_PDSINST_ADD64_DST_SHIFT (0U) 353 /* cc ? dst = src0 + (src1 * -1sna) + cin 354 * 355 * Add or subtract 2 32 bit numbers. Conditionally takes in a carry in. Always 356 * generates a carry out which is held in the status register. 357 */ 358 #define PVR_ROGUE_PDSINST_ADD32_OPCODE_SHIFT (28U) 359 #define PVR_ROGUE_PDSINST_ADD32_CC_SHIFT (27U) 360 #define PVR_ROGUE_PDSINST_ADD32_CC_ENABLE (0x08000000U) 361 #define PVR_ROGUE_PDSINST_ADD32_ALUM_SHIFT (26U) 362 #define PVR_ROGUE_PDSINST_ADD32_ALUM_SIGNED (0x04000000U) 363 #define PVR_ROGUE_PDSINST_ADD32_SNA_SHIFT (24U) 364 #define PVR_ROGUE_PDSINST_ADD32_SNA_SUB (0x01000000U) 365 /* 32-bit source to add */ 366 #define PVR_ROGUE_PDSINST_ADD32_SRC0_SHIFT (14U) 367 #define PVR_ROGUE_PDSINST_ADD32_SRC0_CLRMSK (0xFFC03FFFU) 368 /* 32-bit source to add */ 369 #define PVR_ROGUE_PDSINST_ADD32_SRC1_SHIFT (6U) 370 #define PVR_ROGUE_PDSINST_ADD32_SRC1_CLRMSK (0xFFFFC03FU) 371 /* 32-bit temp or persistent temp */ 372 #define PVR_ROGUE_PDSINST_ADD32_DST_SHIFT (0U) 373 #define PVR_ROGUE_PDSINST_ADD32_DST_CLRMSK (0xFFFFFFC0U) 374 375 /* Comparison Operation */ 376 #define PVR_ROGUE_PDSINST_COP_MASK (0x00000003U) 377 378 /* = */ 379 #define PVR_ROGUE_PDSINST_COP_EQ (0x00000000U) 380 381 /* > */ 382 #define PVR_ROGUE_PDSINST_COP_GT (0x00000001U) 383 384 /* < */ 385 #define PVR_ROGUE_PDSINST_COP_LT (0x00000002U) 386 387 /* != */ 388 #define PVR_ROGUE_PDSINST_COP_NE (0x00000003U) 389 390 /* Compare Instruction with 2 sources (IM=0) 391 * 392 * im = 0; 393 * cc ? dst = src0 op src1 394 * 395 * Test source 0 against source 1. The result is written to the destination 396 * predicate (P0). All arguments are treated as unsigned. 397 */ 398 #define PVR_ROGUE_PDSINST_CMP_OPCODE_SHIFT (28U) 399 #define PVR_ROGUE_PDSINST_CMP_OPCODE_CLRMSK (0x0FFFFFFFU) 400 #define PVR_ROGUE_PDSINST_CMP_OPCODE_DEFAULT (0xB0000000U) /* CMP */ 401 #define PVR_ROGUE_PDSINST_CMP_CC_SHIFT (27U) 402 #define PVR_ROGUE_PDSINST_CMP_CC_CLRMSK (0xF7FFFFFFU) 403 #define PVR_ROGUE_PDSINST_CMP_CC_DISABLE (0x00000000U) 404 #define PVR_ROGUE_PDSINST_CMP_CC_ENABLE (0x08000000U) 405 #define PVR_ROGUE_PDSINST_CMP_COP_SHIFT (25U) 406 #define PVR_ROGUE_PDSINST_CMP_COP_CLRMSK (0xF9FFFFFFU) 407 #define PVR_ROGUE_PDSINST_CMP_COP_EQ (0x00000000U) 408 #define PVR_ROGUE_PDSINST_CMP_COP_GT (0x02000000U) 409 #define PVR_ROGUE_PDSINST_CMP_COP_LT (0x04000000U) 410 #define PVR_ROGUE_PDSINST_CMP_COP_NE (0x06000000U) 411 #define PVR_ROGUE_PDSINST_CMP_SETCP_SHIFT (24U) 412 #define PVR_ROGUE_PDSINST_CMP_SETCP_CLRMSK (0xFEFFFFFFU) 413 #define PVR_ROGUE_PDSINST_CMP_SETCP_EN (0x01000000U) 414 #define PVR_ROGUE_PDSINST_CMP_IM_SHIFT (23U) 415 #define PVR_ROGUE_PDSINST_CMP_IM_CLRMSK (0xFF7FFFFFU) 416 #define PVR_ROGUE_PDSINST_CMP_IM_DISABLE (0x00000000U) 417 #define PVR_ROGUE_PDSINST_CMP_IM_ENABLE (0x00800000U) 418 #define PVR_ROGUE_PDSINST_CMP_SRC0_SHIFT (18U) 419 #define PVR_ROGUE_PDSINST_CMP_SRC0_CLRMSK (0xFF83FFFFU) 420 #define PVR_ROGUE_PDSINST_CMP_SRC1_SHIFT (2U) 421 #define PVR_ROGUE_PDSINST_CMP_SRC1_CLRMSK (0xFFFFFE03U) 422 423 /* 16-bit signed immediate. */ 424 #define PVR_ROGUE_PDSINST_IMM16_MASK (0x0000FFFFU) 425 426 /* Compare Instruction with Immediate (IM=1) 427 * 428 * im = 1; 429 * cc ? dst = src0 op imm16 430 * 431 * Test source 0 against an immediate. The result is written to the destination 432 * predicate (P0). All arguments are treated as unsigned. 433 */ 434 #define PVR_ROGUE_PDSINST_CMPI_OPCODE_SHIFT (28U) 435 #define PVR_ROGUE_PDSINST_CMPI_OPCODE_CLRMSK (0x0FFFFFFFU) 436 #define PVR_ROGUE_PDSINST_CMPI_OPCODE_DEFAULT (0xB0000000U) /* CMP */ 437 #define PVR_ROGUE_PDSINST_CMPI_CC_SHIFT (27U) 438 #define PVR_ROGUE_PDSINST_CMPI_CC_CLRMSK (0xF7FFFFFFU) 439 #define PVR_ROGUE_PDSINST_CMPI_CC_DISABLE (0x00000000U) 440 #define PVR_ROGUE_PDSINST_CMPI_CC_ENABLE (0x08000000U) 441 #define PVR_ROGUE_PDSINST_CMPI_COP_SHIFT (25U) 442 #define PVR_ROGUE_PDSINST_CMPI_COP_CLRMSK (0xF9FFFFFFU) 443 #define PVR_ROGUE_PDSINST_CMPI_COP_EQ (0x00000000U) 444 #define PVR_ROGUE_PDSINST_CMPI_COP_GT (0x02000000U) 445 #define PVR_ROGUE_PDSINST_CMPI_COP_LT (0x04000000U) 446 #define PVR_ROGUE_PDSINST_CMPI_COP_NE (0x06000000U) 447 #define PVR_ROGUE_PDSINST_CMPI_SETCP_SHIFT (24U) 448 #define PVR_ROGUE_PDSINST_CMPI_SETCP_CLRMSK (0xFEFFFFFFU) 449 #define PVR_ROGUE_PDSINST_CMPI_SETCP_EN (0x01000000U) 450 #define PVR_ROGUE_PDSINST_CMPI_IM_SHIFT (23U) 451 #define PVR_ROGUE_PDSINST_CMPI_IM_CLRMSK (0xFF7FFFFFU) 452 #define PVR_ROGUE_PDSINST_CMPI_IM_DISABLE (0x00000000U) 453 #define PVR_ROGUE_PDSINST_CMPI_IM_ENABLE (0x00800000U) 454 #define PVR_ROGUE_PDSINST_CMPI_SRC0_SHIFT (18U) 455 #define PVR_ROGUE_PDSINST_CMPI_SRC0_CLRMSK (0xFF83FFFFU) 456 #define PVR_ROGUE_PDSINST_CMPI_IM16_SHIFT (2U) 457 #define PVR_ROGUE_PDSINST_CMPI_IM16_CLRMSK (0xFFFC0003U) 458 459 /* Condition codes */ 460 #define PVR_ROGUE_PDSINST_PREDICATE_MASK (0x0000000FU) 461 462 /* Use programmable predicate 0 */ 463 #define PVR_ROGUE_PDSINST_PREDICATE_P0 (0x00000000U) 464 /* Input Predicate 0 - When DM Pixel Start/End Program End of Tile, When DM 465 * Pixel State Program indicates load Uniforms, When DM Vertex Last Vertex In 466 * Task, When DM Compute indicates shared or kernel task (compute thread barrier 467 * mode) or Last In Task (normal mode), When DM Tessellator TBD. 468 */ 469 #define PVR_ROGUE_PDSINST_PREDICATE_IF0 (0x00000001U) 470 /* Input Predicate 1 - When DM Pixel Start/End Program End Render, When DM Pixel 471 * State Program indicates load Texture, When DM vertex First In Task, When DM 472 * Compute indicates synchronization task (compute thread barrier mode) or First 473 * In Task (normal mode), When DM Tessellator TBD. 474 */ 475 #define PVR_ROGUE_PDSINST_PREDICATE_IF1 (0x00000002U) 476 /* Stream 0 Out has overflowed. Note this is per stream not per buffer. */ 477 #define PVR_ROGUE_PDSINST_PREDICATE_SO_OVERFLOW_PREDICATE_0 (0x00000003U) 478 /* Stream 1 Out has overflowed. Note this is per stream not per buffer. */ 479 #define PVR_ROGUE_PDSINST_PREDICATE_SO_OVERFLOW_PREDICATE_1 (0x00000004U) 480 /* Stream 2 Out has overflowed. Note this is per stream not per buffer. */ 481 #define PVR_ROGUE_PDSINST_PREDICATE_SO_OVERFLOW_PREDICATE_2 (0x00000005U) 482 /* Stream 3 Out has overflowed. Note this is per stream not per buffer. */ 483 #define PVR_ROGUE_PDSINST_PREDICATE_SO_OVERFLOW_PREDICATE_3 (0x00000006U) 484 /* A Stream Out has overflowed. Note this is per stream not per buffer. */ 485 #define PVR_ROGUE_PDSINST_PREDICATE_SO_OVERFLOW_PREDICATE_GLOBAL (0x00000007U) 486 /* For SETC Don't set a new predicate, KEEP the existing one. For BRA 487 * instruction where this is the source predicate, KEEP the instruction, don't 488 * predicate it out. 489 */ 490 #define PVR_ROGUE_PDSINST_PREDICATE_KEEP (0x00000008U) 491 /* DMA Out of Bounds predicate - set by DDMAT instruction when DMA is out of 492 * bounds. 493 */ 494 #define PVR_ROGUE_PDSINST_PREDICATE_OOB (0x00000009U) 495 496 /* Negate condition. */ 497 498 /* Do not negate condition. */ 499 #define PVR_ROGUE_PDSINST_NEG_DISABLE (0x00000000U) 500 /* Negate condition. */ 501 #define PVR_ROGUE_PDSINST_NEG_ENABLE (0x00000001U) 502 503 /* Branch Address. */ 504 #define PVR_ROGUE_PDSINST_BRAADDR_MASK (0x0007FFFFU) 505 506 /* Branch and Set Selected Predicate Instruction 507 * 508 * im = 1; 509 * cc xor neg ? pc = dst; 510 * 511 * Conditionally branch to an address (ADDR), depending upon the predicate. The 512 * meaning of the predicate can be negated using NEG. This instruction also 513 * allows the current predicate referenced by other instructions to be set by 514 * the SETC field. The current predicate is available by all instructions. This 515 * is a signed offset from the current PC. BRA ADDR=0 would be an infinite loop 516 * of the instruction. 517 */ 518 519 #define PVR_ROGUE_PDSINST_BRA_OPCODE_SHIFT (28U) 520 #define PVR_ROGUE_PDSINST_BRA_OPCODE_CLRMSK (0x0FFFFFFFU) 521 #define PVR_ROGUE_PDSINST_BRA_OPCODE_DEFAULT (0xC0000000U) /* BRA */ 522 #define PVR_ROGUE_PDSINST_BRA_SRCC_SHIFT (24U) 523 #define PVR_ROGUE_PDSINST_BRA_SRCC_CLRMSK (0xF0FFFFFFU) 524 #define PVR_ROGUE_PDSINST_BRA_SRCC_P0 (0x00000000U) 525 #define PVR_ROGUE_PDSINST_BRA_SRCC_IF0 (0x01000000U) 526 #define PVR_ROGUE_PDSINST_BRA_SRCC_IF1 (0x02000000U) 527 #define PVR_ROGUE_PDSINST_BRA_SRCC_SO_OVERFLOW_PREDICATE_0 (0x03000000U) 528 #define PVR_ROGUE_PDSINST_BRA_SRCC_SO_OVERFLOW_PREDICATE_1 (0x04000000U) 529 #define PVR_ROGUE_PDSINST_BRA_SRCC_SO_OVERFLOW_PREDICATE_2 (0x05000000U) 530 #define PVR_ROGUE_PDSINST_BRA_SRCC_SO_OVERFLOW_PREDICATE_3 (0x06000000U) 531 #define PVR_ROGUE_PDSINST_BRA_SRCC_SO_OVERFLOW_PREDICATE_GLOBAL (0x07000000U) 532 #define PVR_ROGUE_PDSINST_BRA_SRCC_KEEP (0x08000000U) 533 #define PVR_ROGUE_PDSINST_BRA_SRCC_OOB (0x09000000U) 534 #define PVR_ROGUE_PDSINST_BRA_NEG_SHIFT (23U) 535 #define PVR_ROGUE_PDSINST_BRA_NEG_CLRMSK (0xFF7FFFFFU) 536 #define PVR_ROGUE_PDSINST_BRA_NEG_DISABLE (0x00000000U) 537 #define PVR_ROGUE_PDSINST_BRA_NEG_ENABLE (0x00800000U) 538 #define PVR_ROGUE_PDSINST_BRA_SETC_SHIFT (19U) 539 #define PVR_ROGUE_PDSINST_BRA_SETC_CLRMSK (0xFF87FFFFU) 540 #define PVR_ROGUE_PDSINST_BRA_SETC_P0 (0x00000000U) 541 #define PVR_ROGUE_PDSINST_BRA_SETC_IF0 (0x00080000U) 542 #define PVR_ROGUE_PDSINST_BRA_SETC_IF1 (0x00100000U) 543 #define PVR_ROGUE_PDSINST_BRA_SETC_SO_OVERFLOW_PREDICATE_0 (0x00180000U) 544 #define PVR_ROGUE_PDSINST_BRA_SETC_SO_OVERFLOW_PREDICATE_1 (0x00200000U) 545 #define PVR_ROGUE_PDSINST_BRA_SETC_SO_OVERFLOW_PREDICATE_2 (0x00280000U) 546 #define PVR_ROGUE_PDSINST_BRA_SETC_SO_OVERFLOW_PREDICATE_3 (0x00300000U) 547 #define PVR_ROGUE_PDSINST_BRA_SETC_SO_OVERFLOW_PREDICATE_GLOBAL (0x00380000U) 548 #define PVR_ROGUE_PDSINST_BRA_SETC_KEEP (0x00400000U) 549 #define PVR_ROGUE_PDSINST_BRA_SETC_OOB (0x00480000U) 550 #define PVR_ROGUE_PDSINST_BRA_ADDR_SHIFT (0U) 551 #define PVR_ROGUE_PDSINST_BRA_ADDR_CLRMSK (0xFFF80000U) 552 553 /* SLC_MODE_LD SLC Cache Policy for loads. */ 554 #define PVR_ROGUE_PDSINST_SLC_MODE_LD_MASK (0x00000003U) 555 /* Bypass Policy */ 556 #define PVR_ROGUE_PDSINST_SLC_MODE_LD_BYPASS (0x00000000U) 557 /* Standard Cached Read */ 558 #define PVR_ROGUE_PDSINST_SLC_MODE_LD_CACHED (0x00000001U) 559 /* Cached Read no allocate */ 560 #define PVR_ROGUE_PDSINST_SLC_MODE_LD_CACHED_RD_NA (0x00000003U) 561 562 /* CMODE_LD MCU (SLC) Cache Mode for Loads. */ 563 #define PVR_ROGUE_PDSINST_CMODE_LD_MASK (0x00000003U) 564 565 /* Normal cache operation. */ 566 #define PVR_ROGUE_PDSINST_CMODE_LD_CACHED (0x00000000U) 567 568 /* Bypass L0 and L1. */ 569 #define PVR_ROGUE_PDSINST_CMODE_LD_BYPASS (0x00000001U) 570 571 /* Force line fill of L0 and L1. */ 572 #define PVR_ROGUE_PDSINST_CMODE_LD_FORCE_LINE_FILL (0x00000002U) 573 574 /* ld: Number of 64 bit words to load. */ 575 #define PVR_ROGUE_PDSINST_LD_COUNT8_MASK (0x00000007U) 576 577 /* Source Base Address for memory fetch in DWORDS - MUST BE 128 BIT ALIGNED. */ 578 #define PVR_ROGUE_PDSINST_LD_SRCADD_MASK (UINT64_C(0x0000003FFFFFFFFF)) 579 580 /* Load Instruction DMA : Src0 */ 581 582 /* SLC cache policy. */ 583 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_SLCMODE_SHIFT (62U) 584 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_SLCMODE_CLRMSK \ 585 (UINT64_C(0x3FFFFFFFFFFFFFFF)) 586 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_SLCMODE_BYPASS \ 587 (UINT64_C(0x0000000000000000)) 588 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_SLCMODE_CACHED \ 589 (UINT64_C(0x4000000000000000)) 590 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_SLCMODE_CACHED_RD_NA \ 591 (UINT64_C(0xc000000000000000)) 592 593 /* The destination address in the temps (persistent or not) for the read data - 594 * MUST BE 128 BIT ALIGNED. 595 */ 596 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_DEST_SHIFT (47U) 597 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_DEST_CLRMSK (UINT64_C(0xFFF07FFFFFFFFFFF)) 598 599 /* Cache Mode */ 600 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_CMODE_SHIFT (44U) 601 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_CMODE_CLRMSK (UINT64_C(0xFFFFCFFFFFFFFFFF)) 602 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_CMODE_CACHED (UINT64_C(0x0000000000000000)) 603 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_CMODE_BYPASS (UINT64_C(0x0000100000000000)) 604 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_CMODE_FORCE_LINE_FILL \ 605 (UINT64_C(0x0000200000000000)) 606 607 /* ld: Number of 64 bit words to load. */ 608 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_COUNT8_SHIFT (41U) 609 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_COUNT8_CLRMSK \ 610 (UINT64_C(0xFFFFF1FFFFFFFFFF)) 611 612 /* Source Base Address for memory fetch - MUST BE 128 BIT ALIGNED. */ 613 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_SRCADD_SHIFT (2U) 614 #define PVR_ROGUE_PDSINST_LD_LD_SRC0_SRCADD_CLRMSK \ 615 (UINT64_C(0xFFFFFF0000000003)) 616 617 /* Special Instructions Op-code. */ 618 #define PVR_ROGUE_PDSINST_OPCODESP_MASK (0x0000000FU) 619 620 /* Data Load from memory. */ 621 #define PVR_ROGUE_PDSINST_OPCODESP_LD UINT32_C(0x00000000) 622 623 /* Data Store to memory. */ 624 #define PVR_ROGUE_PDSINST_OPCODESP_ST UINT32_C(0x00000001) 625 626 /* Wait read or write data operations to complete. */ 627 #define PVR_ROGUE_PDSINST_OPCODESP_WDF UINT32_C(0x00000002) 628 629 /* Load 16 bit immediate. */ 630 #define PVR_ROGUE_PDSINST_OPCODESP_LIMM UINT32_C(0x00000003) 631 632 /* Lock the execute so only this instance can execute for this data master. */ 633 #define PVR_ROGUE_PDSINST_OPCODESP_LOCK UINT32_C(0x00000004) 634 635 /* Release the lock taken by lock. */ 636 #define PVR_ROGUE_PDSINST_OPCODESP_RELEASE UINT32_C(0x00000005) 637 638 /* Halt execution (program termination). */ 639 #define PVR_ROGUE_PDSINST_OPCODESP_HALT UINT32_C(0x00000006) 640 641 /* Clear stream out predicate. */ 642 #define PVR_ROGUE_PDSINST_OPCODESP_STMC UINT32_C(0x00000007) 643 644 /* Parallel Stream Out. */ 645 #define PVR_ROGUE_PDSINST_OPCODESP_STMP UINT32_C(0x00000008) 646 647 /* Integer Divide. */ 648 #define PVR_ROGUE_PDSINST_OPCODESP_IDIV UINT32_C(0x00000009) 649 650 /* Atomic Access. */ 651 #define PVR_ROGUE_PDSINST_OPCODESP_AA UINT32_C(0x0000000a) 652 653 /* Issue Data Fence. */ 654 #define PVR_ROGUE_PDSINST_OPCODESP_IDF UINT32_C(0x0000000b) 655 656 /* Issue Data Fence. */ 657 #define PVR_ROGUE_PDSINST_OPCODESP_POL (0x0000000cU) 658 659 /*No Operation. */ 660 #define PVR_ROGUE_PDSINST_OPCODESP_NOP (0x0000000fU) 661 662 /* Data Load Instruction (Opcode SP) 663 * 664 * for (i=0; i < count;i++) { 665 * cc ? *(src0 + i) = mem(src1 + i) 666 * } 667 * 668 * Load count 32 bit words from memory to the temporaries reading from the 669 * address in memory pointed to by SRCADD. If the final destination address 670 * (DEST + COUNT - 1) exceeds the amount of temps available the entire load is 671 * discarded. 672 */ 673 #define PVR_ROGUE_PDSINST_LD_OPCODE_SHIFT (28U) 674 #define PVR_ROGUE_PDSINST_LD_OPCODE_CLRMSK (0x0FFFFFFFU) 675 #define PVR_ROGUE_PDSINST_LD_OPCODE_DEFAULT (0xD0000000U) /* SP */ 676 #define PVR_ROGUE_PDSINST_LD_CC_SHIFT (27U) 677 #define PVR_ROGUE_PDSINST_LD_CC_CLRMSK (0xF7FFFFFFU) 678 #define PVR_ROGUE_PDSINST_LD_CC_DISABLE (0x00000000U) 679 #define PVR_ROGUE_PDSINST_LD_CC_ENABLE (0x08000000U) 680 #define PVR_ROGUE_PDSINST_LD_OP_SHIFT (23U) 681 #define PVR_ROGUE_PDSINST_LD_OP_CLRMSK (0xF87FFFFFU) 682 #define PVR_ROGUE_PDSINST_LD_OP_DEFAULT (0x00000000U) /* ld */ 683 #define PVR_ROGUE_PDSINST_LD_SRC0_SHIFT (0U) 684 #define PVR_ROGUE_PDSINST_LD_SRC0_CLRMSK (0xFFFFFF80U) 685 686 /* CMODE_ST MCU (SLC) Cache Mode for stores. */ 687 #define PVR_ROGUE_PDSINST_CMODE_ST_MASK (0x00000003U) 688 689 /* Write-through Policy */ 690 #define PVR_ROGUE_PDSINST_CMODE_ST_WRITE_THROUGH (0x00000000U) 691 692 /* Write-back Policy. */ 693 #define PVR_ROGUE_PDSINST_CMODE_ST_WRITE_BACK (0x00000001U) 694 695 /* Lazy write-back policy. */ 696 #define PVR_ROGUE_PDSINST_CMODE_ST_LAZY_WRITE_BACK (0x00000002U) 697 698 /* ST: Number of 32 bit Words to store. */ 699 #define PVR_ROGUE_PDSINST_ST_COUNT4_MASK (0x0000000FU) 700 701 /* Source Base Address for memory fetch in DWORDS. */ 702 #define PVR_ROGUE_PDSINST_ST_SRCADD_MASK (UINT64_C(0x0000003FFFFFFFFF)) 703 704 /* Store Instruction DMA : Src0 */ 705 706 /* SLC cache policy. */ 707 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_SLCMODE_SHIFT (62U) 708 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_SLCMODE_CLRMSK \ 709 (UINT64_C(0x3FFFFFFFFFFFFFFF)) 710 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_SLCMODE_WRITE_THROUGH \ 711 (UINT64_C(0x0000000000000000)) 712 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_SLCMODE_WRITE_BACK \ 713 (UINT64_C(0x4000000000000000)) 714 715 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_SRC_SHIFT (46U) 716 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_SRC_CLRMSK (UINT64_C(0xFFF03FFFFFFFFFFF)) 717 718 /* Cache Mode. */ 719 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_CMODE_SHIFT (44U) 720 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_CMODE_CLRMSK (UINT64_C(0xFFFFCFFFFFFFFFFF)) 721 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_CMODE_WRITE_THROUGH \ 722 (UINT64_C(0x0000000000000000)) 723 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_CMODE_WRITE_BACK \ 724 (UINT64_C(0x0000100000000000)) 725 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_CMODE_LAZY_WRITE_BACK \ 726 (UINT64_C(0x0000200000000000)) 727 728 /* ST: Number of 32 bit Words to store. */ 729 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_COUNT4_SHIFT (40U) 730 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_COUNT4_CLRMSK \ 731 (UINT64_C(0xFFFFF0FFFFFFFFFF)) 732 733 /* Destination Base Address for memory write. */ 734 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_DSTADD_SHIFT (2U) 735 #define PVR_ROGUE_PDSINST_ST_ST_SRC0_DSTADD_CLRMSK \ 736 (UINT64_C(0xFFFFFF0000000003)) 737 738 /* Data Store Instruction (Opcode SP) 739 * 740 * for (i=0; i < count;i++) { 741 * cc ? mem(src1 + i) = *(src0 + i) 742 * } 743 * 744 * Store count 64 bit words from temporaries to memory (memory address starts at 745 * src1). If the instruction attempts to read data (in temps) outside of it's 746 * allocated region the entire store is discarded. 747 */ 748 #define PVR_ROGUE_PDSINST_ST_OPCODE_SHIFT (28U) 749 #define PVR_ROGUE_PDSINST_ST_OPCODE_CLRMSK (0x0FFFFFFFU) 750 #define PVR_ROGUE_PDSINST_ST_OPCODE_DEFAULT (0xD0000000U) /* SP */ 751 #define PVR_ROGUE_PDSINST_ST_CC_SHIFT (27U) 752 #define PVR_ROGUE_PDSINST_ST_CC_CLRMSK (0xF7FFFFFFU) 753 #define PVR_ROGUE_PDSINST_ST_CC_DISABLE (0x00000000U) 754 #define PVR_ROGUE_PDSINST_ST_CC_ENABLE (0x08000000U) 755 #define PVR_ROGUE_PDSINST_ST_OP_SHIFT (23U) 756 #define PVR_ROGUE_PDSINST_ST_OP_CLRMSK (0xF87FFFFFU) 757 #define PVR_ROGUE_PDSINST_ST_OP_DEFAULT (0x00800000U) /* ST */ 758 #define PVR_ROGUE_PDSINST_ST_SRC0_SHIFT (0U) 759 #define PVR_ROGUE_PDSINST_ST_SRC0_CLRMSK (0xFFFFFF80U) 760 761 /* Data Fence Instruction (Opcode SP) 762 * 763 * Cc ? wdf 764 * 765 * The data fence instruction gives the ability to track the return of dependent 766 * read data and to determine when data written from the core has made it to the 767 * MCU. This is required on reads as there is no implicit synchronization 768 * between read accesses to the primary attribute bank and data returned by 769 * dependent reads. For writes it is required where the program is enforcing 770 * synchronization with another program (which could be on the PDS or any other 771 * processor in the system). Note, this only guarantees order within the 772 * PDS. For order elsewhere reads need to be issued, and flush commands may have 773 * to be issued to the MCU 774 * 775 * The fence mechanism takes the form of a counter that is incremented whenever 776 * a read (ld) or write (ST) instruction is encountered by the instruction fetch 777 * decoder. When the read or write instruction returns, or writes all its data 778 * the counter is decremented. There is 1 counter per thread. Prior to accessing 779 * return data a WDF instruction must be issued, when this is seen by the 780 * instruction decoder it will check the current count value and will suspend 781 * execution if it is currently non zero, execution being resumed as soon as the 782 * counter reaches zero, and a slot is available. 783 * 784 * Example 785 * Do a dependent read for data 786 * 787 * ldr0,#2,r3 Issue read 788 * ... Try and do some other stuff 789 * wdf Make sure read data has come back 790 * add32 r2,r1,r0 And use the returned result 791 * 792 */ 793 #define PVR_ROGUE_PDSINST_WDF_OPCODE_SHIFT (28U) 794 #define PVR_ROGUE_PDSINST_WDF_OPCODE_CLRMSK (0x0FFFFFFFU) 795 #define PVR_ROGUE_PDSINST_WDF_OPCODE_DEFAULT (0xD0000000U) /* SP */ 796 #define PVR_ROGUE_PDSINST_WDF_CC_SHIFT (27U) 797 #define PVR_ROGUE_PDSINST_WDF_CC_CLRMSK (0xF7FFFFFFU) 798 #define PVR_ROGUE_PDSINST_WDF_CC_DISABLE (0x00000000U) 799 #define PVR_ROGUE_PDSINST_WDF_CC_ENABLE (0x08000000U) 800 #define PVR_ROGUE_PDSINST_WDF_OP_SHIFT (23U) 801 #define PVR_ROGUE_PDSINST_WDF_OP_CLRMSK (0xF87FFFFFU) 802 #define PVR_ROGUE_PDSINST_WDF_OP_DEFAULT (0x01000000U) /* WDF */ 803 804 /* PDS Global Register access control */ 805 806 /* Disable global register access */ 807 #define PVR_ROGUE_PDSINST_GR_DISABLE (0x00000000U) 808 809 /* Enable global register access, global register specified by IMM16.*/ 810 #define PVR_ROGUE_PDSINST_GR_ENABLE (0x00000001U) 811 812 /* Load Immediate (Opcode SP) 813 * 814 * cc ? GR = DISABLE : *src1 = src0 815 * cc ? GR = ENABLE : *src1 = greg[IMM16] 816 * 817 * Load an immediate value (src0) into the temporary registers. If the GR flag 818 * is set, the PDS global register specified by IMM16 will be loaded instead. 819 * greg[0] = cluster number greg[1] = instance number 820 * 821 */ 822 #define PVR_ROGUE_PDSINST_LIMM_OPCODE_SHIFT (28U) 823 #define PVR_ROGUE_PDSINST_LIMM_OPCODE_CLRMSK (0x0FFFFFFFU) 824 #define PVR_ROGUE_PDSINST_LIMM_OPCODE_DEFAULT (0xD0000000U) /* SP */ 825 #define PVR_ROGUE_PDSINST_LIMM_CC_SHIFT (27U) 826 #define PVR_ROGUE_PDSINST_LIMM_CC_CLRMSK (0xF7FFFFFFU) 827 #define PVR_ROGUE_PDSINST_LIMM_CC_DISABLE (0x00000000U) 828 #define PVR_ROGUE_PDSINST_LIMM_CC_ENABLE (0x08000000U) 829 #define PVR_ROGUE_PDSINST_LIMM_OP_SHIFT (23U) 830 #define PVR_ROGUE_PDSINST_LIMM_OP_CLRMSK (0xF87FFFFFU) 831 #define PVR_ROGUE_PDSINST_LIMM_OP_DEFAULT (0x01800000U) /* LIMM */ 832 #define PVR_ROGUE_PDSINST_LIMM_SRC1_SHIFT (18U) 833 #define PVR_ROGUE_PDSINST_LIMM_SRC1_CLRMSK (0xFF83FFFFU) 834 #define PVR_ROGUE_PDSINST_LIMM_SRC0_SHIFT (2U) 835 #define PVR_ROGUE_PDSINST_LIMM_SRC0_CLRMSK (0xFFFC0003U) 836 #define PVR_ROGUE_PDSINST_LIMM_GR_SHIFT (1U) 837 #define PVR_ROGUE_PDSINST_LIMM_GR_CLRMSK (0xFFFFFFFDU) 838 #define PVR_ROGUE_PDSINST_LIMM_GR_DISABLE (0x00000000U) 839 #define PVR_ROGUE_PDSINST_LIMM_GR_ENABLE (0x00000002U) 840 841 /* Lock Instruction (Opcode SP) 842 * 843 * cc ? lock 844 * 845 * The hardware contains an internal mutex per data master. When the lock 846 * instruction is issued, the thread will attempt to take control of the mutex 847 * (for the current data master). If it is already taken by another thread, then 848 * the thread is descheduled until it is available. 849 * 850 * The purpose of the lock (and release) instructions is to allow critical 851 * sections of code to execute serially to other code for the same data 852 * master. This is particularly useful when accessing the persistent (cross 853 * thread) temporaries. Note that there is no communication possible across data 854 * masters. 855 * 856 * It is illegal to place a DOUT instruction inside a LOCK, RELEASE section of 857 * code. 858 */ 859 #define PVR_ROGUE_PDSINST_LOCK_OPCODE_SHIFT (28U) 860 #define PVR_ROGUE_PDSINST_LOCK_OPCODE_CLRMSK (0x0FFFFFFFU) 861 #define PVR_ROGUE_PDSINST_LOCK_OPCODE_DEFAULT (0xD0000000U) /* SP */ 862 #define PVR_ROGUE_PDSINST_LOCK_CC_SHIFT (27U) 863 #define PVR_ROGUE_PDSINST_LOCK_CC_CLRMSK (0xF7FFFFFFU) 864 #define PVR_ROGUE_PDSINST_LOCK_CC_DISABLE (0x00000000U) 865 #define PVR_ROGUE_PDSINST_LOCK_CC_ENABLE (0x08000000U) 866 #define PVR_ROGUE_PDSINST_LOCK_OP_SHIFT (23U) 867 #define PVR_ROGUE_PDSINST_LOCK_OP_CLRMSK (0xF87FFFFFU) 868 #define PVR_ROGUE_PDSINST_LOCK_OP_DEFAULT (0x02000000U) /* LOCK */ 869 870 /* Release Lock (Opcode SP) 871 * 872 * cc ? release 873 * 874 * The hardware contains an internal mutex per data master. If a thread has 875 * issued a lock instruction, then a release instruction must be issued to 876 * release the lock. See the corresponding lock instruction for more details 877 * 878 * It is illegal to place a DOUT instruction inside a LOCK, RELEASE section of 879 * code. 880 */ 881 #define PVR_ROGUE_PDSINST_RELEASE_OPCODE_SHIFT (28U) 882 #define PVR_ROGUE_PDSINST_RELEASE_OPCODE_CLRMSK (0x0FFFFFFFU) 883 #define PVR_ROGUE_PDSINST_RELEASE_OPCODE_DEFAULT (0xD0000000U) /* SP */ 884 #define PVR_ROGUE_PDSINST_RELEASE_CC_SHIFT (27U) 885 #define PVR_ROGUE_PDSINST_RELEASE_CC_CLRMSK (0xF7FFFFFFU) 886 #define PVR_ROGUE_PDSINST_RELEASE_CC_DISABLE (0x00000000U) 887 #define PVR_ROGUE_PDSINST_RELEASE_CC_ENABLE (0x08000000U) 888 #define PVR_ROGUE_PDSINST_RELEASE_OP_SHIFT (23U) 889 #define PVR_ROGUE_PDSINST_RELEASE_OP_CLRMSK (0xF87FFFFFU) 890 #define PVR_ROGUE_PDSINST_RELEASE_OP_DEFAULT (0x02800000U) /* RELEASE */ 891 892 /* Special instruction - Halt 893 * Halt Execution (Opcode SP) 894 * 895 * cc ? halt 896 * 897 * The last instruction in a program must always be a halt instruction, or a 898 * DOUT/DDMAD instruction with the END flag set. This is required in order to 899 * indicate the end of the program. 900 */ 901 #define PVR_ROGUE_PDSINST_HALT_OPCODE_SHIFT (28U) 902 #define PVR_ROGUE_PDSINST_HALT_OPCODE_CLRMSK (0x0FFFFFFFU) 903 #define PVR_ROGUE_PDSINST_HALT_OPCODE_DEFAULT (0xD0000000U) /* SP */ 904 #define PVR_ROGUE_PDSINST_HALT_CC_SHIFT (27U) 905 #define PVR_ROGUE_PDSINST_HALT_CC_CLRMSK (0xF7FFFFFFU) 906 #define PVR_ROGUE_PDSINST_HALT_CC_DISABLE (0x00000000U) 907 #define PVR_ROGUE_PDSINST_HALT_CC_ENABLE (0x08000000U) 908 #define PVR_ROGUE_PDSINST_HALT_OP_SHIFT (23U) 909 #define PVR_ROGUE_PDSINST_HALT_OP_CLRMSK (0xF87FFFFFU) 910 #define PVR_ROGUE_PDSINST_HALT_OP_DEFAULT (0x03000000U) /* HALT */ 911 912 /* Special instruction - Nop 913 * No Operation (Opcode SP) 914 * 915 * cc ? NOP 916 * 917 * This instruction does no operation, and introduces a wait cycle into the 918 * pipeline. 919 * 920 */ 921 #define PVR_ROGUE_PDSINST_NOP_OPCODE_SHIFT (28U) 922 #define PVR_ROGUE_PDSINST_NOP_OPCODE_CLRMSK (0x0FFFFFFFU) 923 #define PVR_ROGUE_PDSINST_NOP_OPCODE_DEFAULT (0xD0000000U) /* SP */ 924 #define PVR_ROGUE_PDSINST_NOP_CC_SHIFT (27U) 925 #define PVR_ROGUE_PDSINST_NOP_CC_CLRMSK (0xF7FFFFFFU) 926 #define PVR_ROGUE_PDSINST_NOP_CC_DISABLE (0x00000000U) 927 #define PVR_ROGUE_PDSINST_NOP_CC_ENABLE (0x08000000U) 928 #define PVR_ROGUE_PDSINST_NOP_OP_SHIFT (23U) 929 #define PVR_ROGUE_PDSINST_NOP_OP_CLRMSK (0xF87FFFFFU) 930 #define PVR_ROGUE_PDSINST_NOP_OP_DEFAULT (0x07800000U) /* NOP */ 931 932 /* The SO bits to clear 0-3 streams 0-3, bit 4-global */ 933 #define PVR_ROGUE_PDSINST_SOMASK_MASK (0x0000001FU) 934 935 /* Special instruction - Stream out predicate clear 936 * (Opcode SP) 937 * 938 * cc ? NOP 939 * 940 * This instruction clears the stream out predicates to 0, according to the 941 * clear bits. 942 * 943 */ 944 #define PVR_ROGUE_PDSINST_STMC_OPCODE_SHIFT (28U) 945 #define PVR_ROGUE_PDSINST_STMC_OPCODE_CLRMSK (0x0FFFFFFFU) 946 #define PVR_ROGUE_PDSINST_STMC_OPCODE_DEFAULT (0xD0000000U) /* SP */ 947 #define PVR_ROGUE_PDSINST_STMC_CC_SHIFT (27U) 948 #define PVR_ROGUE_PDSINST_STMC_CC_CLRMSK (0xF7FFFFFFU) 949 #define PVR_ROGUE_PDSINST_STMC_CC_DISABLE (0x00000000U) 950 #define PVR_ROGUE_PDSINST_STMC_CC_ENABLE (0x08000000U) 951 #define PVR_ROGUE_PDSINST_STMC_OP_SHIFT (23U) 952 #define PVR_ROGUE_PDSINST_STMC_OP_CLRMSK (0xF87FFFFFU) 953 #define PVR_ROGUE_PDSINST_STMC_OP_DEFAULT (0x03800000U) /* STMC */ 954 #define PVR_ROGUE_PDSINST_STMC_SOMASK_SHIFT (0U) 955 #define PVR_ROGUE_PDSINST_STMC_SOMASK_CLRMSK (0xFFFFFFE0U) 956 957 /* A 1 TB address, with byte granularity. Address must be dword aligned when 958 * repeat is 0. 959 */ 960 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_ADDRESS_MASK \ 961 (UINT64_C(0x000000FFFFFFFFFF)) 962 963 /* SLC cache policy */ 964 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRCADD_SLCMODE_SHIFT (62U) 965 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRCADD_SLCMODE_CLRMSK \ 966 (UINT64_C(0x3FFFFFFFFFFFFFFF)) 967 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRCADD_SLCMODE_BYPASS \ 968 (UINT64_C(0x0000000000000000)) 969 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRCADD_SLCMODE_CACHED \ 970 (UINT64_C(0x4000000000000000)) 971 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRCADD_SLCMODE_CACHED_RD_NA \ 972 (UINT64_C(0xc000000000000000)) 973 974 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRCADD_ADDRESS_SHIFT (0U) 975 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRCADD_ADDRESS_CLRMSK \ 976 (UINT64_C(0xFFFFFF0000000000)) 977 978 /* Size of external memory buffer in bytes (0 is 0 bytes) */ 979 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_MSIZE_MASK (0x7FFFFFFFU) 980 981 /* When repeat is enabled the size of the DMA in bytes */ 982 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_WORDSIZE_MASK (0x00000003U) 983 /* DMA of 1 byte */ 984 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_WORDSIZE_ONE (0x00000000U) 985 /* DMA of 2 byte */ 986 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_WORDSIZE_TWO (0x00000001U) 987 /* DMA of 3 byte */ 988 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_WORDSIZE_THREE (0x00000002U) 989 /* DMA of 4 byte */ 990 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_WORDSIZE_FOUR (0x00000003U) 991 992 /* DMA to unified store */ 993 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_DEST_UNIFIED_STORE (0x00000000U) 994 995 /* DMA to common store */ 996 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_DEST_COMMON_STORE (0x00000001U) 997 998 /* Primary instance data offset in 32 bit words (offset into the current 999 * instance). 1000 */ 1001 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_AO_MASK (0x00001FFFU) 1002 1003 /* Only applies to unified store DMAs, must be clear for common store. 1004 * 1005 * DMA is issued natively, in its entirety. 1006 */ 1007 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_REPEAT_NOREPEAT (0x00000000U) 1008 /* BSIZE is the number of times the DMA is repeated. Word size is the size of 1009 * the DMA. The DMA is expanded into BSIZE DMAs. 1010 */ 1011 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_REPEAT_REPEAT (0x00000001U) 1012 1013 /* Size of fetch in dwords (0 is 0 dwords). */ 1014 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_BSIZE_MASK (0x00000FFFU) 1015 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_BSIZE_RANGE (0U) 1016 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_BSIZE_LOWER (0U) 1017 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_BSIZE_UPPER (255U) 1018 1019 /* Size of external buffer in bytes. */ 1020 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_MSIZE_SHIFT (33U) 1021 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_MSIZE_CLRMSK \ 1022 (UINT64_C(0x00000001FFFFFFFF)) 1023 1024 /* Perform OOB checking. */ 1025 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_TEST_SHIFT (32U) 1026 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_TEST_CLRMSK \ 1027 (UINT64_C(0xFFFFFFFEFFFFFFFF)) 1028 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_TEST_EN \ 1029 (UINT64_C(0x0000000100000000)) 1030 1031 /* Last DMA in program. */ 1032 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_LAST_SHIFT (31U) 1033 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_LAST_CLRMSK \ 1034 (UINT64_C(0xFFFFFFFF7FFFFFFF)) 1035 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_LAST_EN \ 1036 (UINT64_C(0x0000000080000000)) 1037 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_WORDSIZE_SHIFT (29U) 1038 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_WORDSIZE_CLRMSK \ 1039 (UINT64_C(0xFFFFFFFF9FFFFFFF)) 1040 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_WORDSIZE_ONE \ 1041 (UINT64_C(0x0000000000000000)) 1042 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_WORDSIZE_TWO \ 1043 (UINT64_C(0x0000000020000000)) 1044 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_WORDSIZE_THREE \ 1045 (UINT64_C(0x0000000040000000)) 1046 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_WORDSIZE_FOUR \ 1047 (UINT64_C(0x0000000060000000)) 1048 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_DEST_SHIFT (28U) 1049 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_DEST_CLRMSK \ 1050 (UINT64_C(0xFFFFFFFFEFFFFFFF)) 1051 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_DEST_UNIFIED_STORE \ 1052 (UINT64_C(0x0000000000000000)) 1053 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_DEST_COMMON_STORE \ 1054 (UINT64_C(0x0000000010000000)) 1055 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_CMODE_SHIFT (26U) 1056 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_CMODE_CLRMSK \ 1057 (UINT64_C(0xFFFFFFFFF3FFFFFF)) 1058 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_CMODE_CACHED \ 1059 (UINT64_C(0x0000000000000000)) 1060 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_CMODE_BYPASS \ 1061 (UINT64_C(0x0000000004000000)) 1062 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_CMODE_FORCE_LINE_FILL \ 1063 (UINT64_C(0x0000000008000000)) 1064 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_AO_SHIFT (13U) 1065 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_AO_CLRMSK \ 1066 (UINT64_C(0xFFFFFFFFFC001FFF)) 1067 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_REPEAT_SHIFT (12U) 1068 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_REPEAT_CLRMSK \ 1069 (UINT64_C(0xFFFFFFFFFFFFEFFF)) 1070 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_REPEAT_NOREPEAT \ 1071 (UINT64_C(0x0000000000000000)) 1072 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_REPEAT_REPEAT \ 1073 (UINT64_C(0x0000000000001000)) 1074 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_BSIZE_SHIFT (0U) 1075 #define PVR_ROGUE_PDSINST_DDMAD_FIELDS_SRC3_BSIZE_CLRMSK \ 1076 (UINT64_C(0xFFFFFFFFFFFFF000)) 1077 1078 /* Stop execution flag 1079 * 1080 * Continue execution after this instruction. 1081 */ 1082 #define PVR_ROGUE_PDSINST_END_DISABLE (0x00000000U) 1083 1084 /* Halt execution after this instruction. */ 1085 #define PVR_ROGUE_PDSINST_END_ENABLE (0x00000001U) 1086 1087 /* 64-bit Consts 0-63 Destination. */ 1088 #define PVR_ROGUE_PDSINST_REGS64C_MASK (0x0000003FU) 1089 #define PVR_ROGUE_PDSINST_REGS64C_CONST64 (0U) 1090 #define PVR_ROGUE_PDSINST_REGS64C_CONST64_LOWER (0U) 1091 #define PVR_ROGUE_PDSINST_REGS64C_CONST64_UPPER (63U) 1092 1093 /* Multiply-add then send to DOUTD (Opcode SP). Optionally perform out-of-bounds 1094 * checking (DDMAD(T)). Multiply-add then send to DOUTD (Opcode SP). 1095 * 1096 * cc ? if ( test == 1 ) then 1097 * cc ? if ( ((src0 * src1) + src2)[39:0] + (src3[11:0]<<2) <= src2[39:0] + 1098 * src3[63:33] ) then cc ? OOB = 0 cc ? doutd = (src0 * src1) + src2, src3 cc 1099 * ? else cc ? OOB = 1 cc ? endif cc ? else cc ? doutd = (src0 * src1) + 1100 * src2 src3 cc ? endif 1101 * 1102 * cc ? doutd = (src0 * src1) + src2, src3 1103 * 1104 * This instruction performs a 32 bit multiply, followed by a 64 bit add. This 1105 * result is combined with a 4th source and used to create the data for an DOUTD 1106 * emit. A DOUTD is a command to a DMA engine, which reads data from memory and 1107 * writes it into the USC Unified or Common Store. 1108 * 1109 * Additionally the DDMAD performs an out-of-bounds check on the DMA when the 1110 * test flag is set . If a buffer overflow is predicated, the DMA is skipped and 1111 * the OOB (DMA out of bounds) predicate is set. 1112 */ 1113 #define PVR_ROGUE_PDSINST_DDMAD_OPCODE_SHIFT (28U) 1114 #define PVR_ROGUE_PDSINST_DDMAD_OPCODE_CLRMSK (0x0FFFFFFFU) 1115 #define PVR_ROGUE_PDSINST_DDMAD_OPCODE_DEFAULT (0xE0000000U) /* DDMAD */ 1116 #define PVR_ROGUE_PDSINST_DDMAD_CC_SHIFT (27U) 1117 #define PVR_ROGUE_PDSINST_DDMAD_CC_CLRMSK (0xF7FFFFFFU) 1118 #define PVR_ROGUE_PDSINST_DDMAD_CC_DISABLE (0x00000000U) 1119 #define PVR_ROGUE_PDSINST_DDMAD_CC_ENABLE (0x08000000U) 1120 #define PVR_ROGUE_PDSINST_DDMAD_END_SHIFT (26U) 1121 #define PVR_ROGUE_PDSINST_DDMAD_END_CLRMSK (0xFBFFFFFFU) 1122 #define PVR_ROGUE_PDSINST_DDMAD_END_DISABLE (0x00000000U) 1123 #define PVR_ROGUE_PDSINST_DDMAD_END_ENABLE (0x04000000U) 1124 1125 /* 32-bit source to multiply - 32-bit range. */ 1126 #define PVR_ROGUE_PDSINST_DDMAD_SRC0_SHIFT (18U) 1127 #define PVR_ROGUE_PDSINST_DDMAD_SRC0_CLRMSK (0xFC03FFFFU) 1128 1129 /* 32-bit source to multiply - 32-bit range. */ 1130 #define PVR_ROGUE_PDSINST_DDMAD_SRC1_SHIFT (13U) 1131 #define PVR_ROGUE_PDSINST_DDMAD_SRC1_CLRMSK (0xFFFC1FFFU) 1132 1133 /* 64-bit source to add - 64-bit range */ 1134 #define PVR_ROGUE_PDSINST_DDMAD_SRC2_SHIFT (6U) 1135 #define PVR_ROGUE_PDSINST_DDMAD_SRC2_CLRMSK (0xFFFFE03FU) 1136 1137 /* 64-bit constant register destination */ 1138 #define PVR_ROGUE_PDSINST_DDMAD_SRC3_SHIFT (0U) 1139 #define PVR_ROGUE_PDSINST_DDMAD_SRC3_CLRMSK (0xFFFFFFC0U) 1140 1141 /* When DOUTU_SAMPLE_RATE is INSTANCE or SELECTIVE - 32 bit temps per instance 1142 * at 4 word granularity. When DOUTU_SAMPLE_RATE is FULL - 32 bit temps per 1143 * sample at 4 word granularity. 1144 */ 1145 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_TEMPS_MASK (0x0000003FU) 1146 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_TEMPS_ALIGNSHIFT (2U) 1147 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_TEMPS_ALIGNSIZE (4U) 1148 1149 /* Sample rate */ 1150 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SAMPLE_RATE_MASK (0x00000003U) 1151 1152 /* Instance rate */ 1153 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SAMPLE_RATE_INSTANCE (0x00000000U) 1154 1155 /* Selective sample rate */ 1156 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SAMPLE_RATE_SELECTIVE (0x00000001U) 1157 1158 /* Full sample rate */ 1159 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SAMPLE_RATE_FULL (0x00000002U) 1160 1161 /* Code base address (4 byte alignment). */ 1162 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_EXE_OFF_MASK (0x3FFFFFFFU) 1163 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_EXE_OFF_ALIGNSHIFT (2U) 1164 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_EXE_OFF_ALIGNSIZE (4U) 1165 1166 /* Use Interface doutu : Src0 */ 1167 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_DUAL_PHASE_SHIFT (41U) 1168 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_DUAL_PHASE_CLRMSK \ 1169 (UINT64_C(0xFFFFFDFFFFFFFFFF)) 1170 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_DUAL_PHASE_EN \ 1171 (UINT64_C(0x0000020000000000)) 1172 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_TEMPS_SHIFT (35U) 1173 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_TEMPS_CLRMSK \ 1174 (UINT64_C(0xFFFFFE07FFFFFFFF)) 1175 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_TEMPS_ALIGNSHIFT (2U) 1176 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_TEMPS_ALIGNSIZE (4U) 1177 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_SAMPLE_RATE_SHIFT (33U) 1178 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_SAMPLE_RATE_CLRMSK \ 1179 (UINT64_C(0xFFFFFFF9FFFFFFFF)) 1180 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_SAMPLE_RATE_INSTANCE \ 1181 (UINT64_C(0x0000000000000000)) 1182 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_SAMPLE_RATE_SELECTIVE \ 1183 (UINT64_C(0x0000000200000000)) 1184 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_SAMPLE_RATE_FULL \ 1185 (UINT64_C(0x0000000400000000)) 1186 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_EXE_OFF_SHIFT (2U) 1187 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_EXE_OFF_CLRMSK \ 1188 (UINT64_C(0xFFFFFFFF00000003)) 1189 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_EXE_OFF_ALIGNSHIFT (2U) 1190 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTU_SRC0_EXE_OFF_ALIGNSIZE (4U) 1191 1192 /* Use Interface doutu : Src1. */ 1193 1194 /* Secondary instance data offset in 32 bit words (offset of the instance). */ 1195 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_DOFFSET_MASK (0x00001FFFU) 1196 1197 /* Source Base Address for memory fetch. Address must be dword aligned when 1198 * repeat is 0. 1199 */ 1200 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SBASE_MASK \ 1201 (UINT64_C(0x000000FFFFFFFFFF)) 1202 1203 /* DMA Interface DOutD : Src0 */ 1204 1205 /* SLC cache policy */ 1206 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_SLCMODE_SHIFT (62U) 1207 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_SLCMODE_CLRMSK \ 1208 (UINT64_C(0x3FFFFFFFFFFFFFFF)) 1209 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_SLCMODE_BYPASS \ 1210 (UINT64_C(0x0000000000000000)) 1211 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_SLCMODE_CACHED \ 1212 (UINT64_C(0x4000000000000000)) 1213 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_SLCMODE_CACHED_RD_NA \ 1214 (UINT64_C(0xc000000000000000)) 1215 1216 /* Secondary instance data offset in 32 bit words (offset of the instance). */ 1217 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_DOFFSET_SHIFT (40U) 1218 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_DOFFSET_CLRMSK \ 1219 (UINT64_C(0xFFE000FFFFFFFFFF)) 1220 1221 /* Source Base Address for memory fetch. */ 1222 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_SBASE_SHIFT (0U) 1223 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_SBASE_CLRMSK \ 1224 (UINT64_C(0xFFFFFF0000000000)) 1225 1226 /* When repeat is enabled the size of the DMA in bytes. */ 1227 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_WORDSIZE_MASK (0x00000003U) 1228 1229 /* DMA of 1 byte */ 1230 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_WORDSIZE_ONE (0x00000000U) 1231 1232 /* DMA of 2 byte */ 1233 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_WORDSIZE_TWO (0x00000001U) 1234 1235 /* DMA of 3 byte */ 1236 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_WORDSIZE_THREE (0x00000002U) 1237 1238 /* DMA of 4 byte */ 1239 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_WORDSIZE_FOUR (0x00000003U) 1240 1241 /* Unified Store */ 1242 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_DEST_UNIFIED_STORE (0x00000000U) 1243 1244 /* Common Store */ 1245 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_DEST_COMMON_STORE (0x00000001U) 1246 1247 /* Primary instance data offset in 32 bit words (offset into the current 1248 * instance). 1249 */ 1250 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_AO_MASK (0x00001FFFU) 1251 1252 /* Only applies to unified store DMAs, ignore for common store. */ 1253 1254 /* DMA is issued natively, in its entirety. */ 1255 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_REPEAT_NOREPEAT (0x00000000U) 1256 1257 /* BSIZE is the number of times the DMA is repeated. Word size is the size of 1258 * the DMA. The DMA is expanded into BSIZE DMAs. 1259 */ 1260 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_REPEAT_REPEAT (0x00000001U) 1261 1262 /* Size of fetch in dwords (0 means don't DMA, 1=1 etc.) */ 1263 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_BSIZE_MASK (0x00000FFFU) 1264 1265 /* DMA Interface DOutD : Src1 */ 1266 1267 /* Last Write or DMA in program (This needs to only be set once on with the last 1268 * DMA or last direct write, which ever is last). 1269 */ 1270 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_LAST_SHIFT (31U) 1271 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_LAST_CLRMSK (0x7FFFFFFFU) 1272 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_LAST_EN (0x80000000U) 1273 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_WORDSIZE_SHIFT (29U) 1274 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_WORDSIZE_CLRMSK (0x9FFFFFFFU) 1275 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_WORDSIZE_ONE (0x00000000U) 1276 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_WORDSIZE_TWO (0x20000000U) 1277 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_WORDSIZE_THREE (0x40000000U) 1278 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_WORDSIZE_FOUR (0x60000000U) 1279 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_DEST_SHIFT (28U) 1280 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_DEST_CLRMSK (0xEFFFFFFFU) 1281 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_DEST_UNIFIED_STORE \ 1282 (0x00000000U) 1283 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_DEST_COMMON_STORE (0x10000000U) 1284 1285 /* CMODE Cache Mode */ 1286 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_CMODE_SHIFT (26U) 1287 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_CMODE_CLRMSK (0xF3FFFFFFU) 1288 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_CMODE_CACHED (0x00000000U) 1289 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_CMODE_BYPASS (0x04000000U) 1290 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_CMODE_FORCE_LINE_FILL \ 1291 (0x08000000U) 1292 1293 /* Primary instance data offset in 32 bit words (offset into the current 1294 * instance). 1295 */ 1296 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_AO_SHIFT (13U) 1297 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_AO_CLRMSK (0xFC001FFFU) 1298 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_REPEAT_SHIFT (12U) 1299 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_REPEAT_CLRMSK (0xFFFFEFFFU) 1300 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_REPEAT_NOREPEAT (0x00000000U) 1301 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_REPEAT_REPEAT (0x00001000U) 1302 1303 /* Size of fetch in dwords (0 means don't DMA, 1=1 etc.) */ 1304 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_BSIZE_SHIFT (0U) 1305 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_BSIZE_CLRMSK (0xFFFFF000U) 1306 1307 /* Lower 64-bit (63:0) data to be written. */ 1308 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SBASE0_MASK \ 1309 (UINT64_C(0xFFFFFFFFFFFFFFFF)) 1310 1311 /* Direct Write Interface doutw : Src0. */ 1312 1313 /* Lower 64-bit (63:0) data to be written */ 1314 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC0_DATA_SHIFT (0U) 1315 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC0_DATA_CLRMSK \ 1316 (UINT64_C(0x0000000000000000)) 1317 1318 /* Unified Store */ 1319 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_DEST_UNIFIED_STORE (0x00000000U) 1320 1321 /* Common Store */ 1322 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_DEST_COMMON_STORE (0x00000001U) 1323 1324 /* Primary instance data offset in 128 bit words (offset into the current 1325 * instance). 1326 */ 1327 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_AO_MASK (0x00001FFFU) 1328 1329 /* DMA Interface DOutD : Src1. */ 1330 1331 /* Last Write or DMA in program (This needs to only be set once on with the last 1332 * DMA or last direct write, which ever is last). 1333 */ 1334 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_LAST_SHIFT (31U) 1335 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_LAST_CLRMSK (0x7FFFFFFFU) 1336 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_LAST_EN (0x80000000U) 1337 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_DEST_SHIFT (28U) 1338 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_DEST_CLRMSK (0xEFFFFFFFU) 1339 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_DEST_UNIFIED_STORE \ 1340 (0x00000000U) 1341 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_DEST_COMMON_STORE (0x10000000U) 1342 1343 /* CMODE Cache Mode */ 1344 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_CMODE_SHIFT (26U) 1345 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_CMODE_CLRMSK (0xF3FFFFFFU) 1346 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_CMODE_CACHED (0x00000000U) 1347 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_CMODE_BYPASS (0x04000000U) 1348 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_CMODE_FORCE_LINE_FILL \ 1349 (0x08000000U) 1350 1351 /* Primary instance data offset in 32 bit words (offset into the current 1352 * instance). For 64 bit writes the address needs to be 64 bit aligned. 1353 */ 1354 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_AO_SHIFT (13U) 1355 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_AO_CLRMSK (0xFC001FFFU) 1356 1357 /* 2-bit dword write mask. */ 1358 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_BSIZE_SHIFT (0U) 1359 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_BSIZE_CLRMSK (0xFFFFFFFCU) 1360 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_BSIZE_LOWER (0x00000000U) 1361 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_BSIZE_UPPER (0x00000001U) 1362 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_BSIZE_ALL64 (0x00000002U) 1363 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTW_SRC1_BSIZE_NONE (0x00000003U) 1364 1365 /* VDM Writeback Interface Doutv : Src0 */ 1366 1367 /* Number of Indices to use in Draw Indirect (0 = 0) */ 1368 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTV_SBASE_MASK (0xFFFFFFFFU) 1369 1370 /* VDM Writeback Interface Doutv : Src1 */ 1371 1372 /* Number of Indices to use in Draw Indirect (0 = 0) */ 1373 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTV_SRC1_SBASE_SHIFT (0U) 1374 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTV_SRC1_SBASE_CLRMSK (0x00000000U) 1375 1376 /* Shade Model Control */ 1377 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SHADEMODEL_MASK (0x00000003U) 1378 1379 /* Vertex 0 is the flat shaded color source. */ 1380 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SHADEMODEL_FLAT_VERTEX0 \ 1381 (0x00000000U) 1382 1383 /* Vertex 1 is the flat shaded color source. */ 1384 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SHADEMODEL_FLAT_VERTEX1 \ 1385 (0x00000001U) 1386 1387 /* Vertex 2 is the flat shaded color source. */ 1388 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SHADEMODEL_FLAT_VERTEX2 \ 1389 (0x00000002U) 1390 1391 /* Gouraud shaded. */ 1392 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SHADEMODEL_GOURAUD (0x00000003U) 1393 1394 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SIZE_MASK (0x00000003U) 1395 1396 /* 1 Dimension (U) */ 1397 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SIZE_1D (0x00000000U) 1398 1399 /* 2 Dimension (UV) */ 1400 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SIZE_2D (0x00000001U) 1401 1402 /* 3 Dimension (UVS) */ 1403 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SIZE_3D (0x00000002U) 1404 1405 /* 4 Dimension (UVST) */ 1406 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SIZE_4D (0x00000003U) 1407 1408 /* This issue is perspective correct. */ 1409 1410 /* No W */ 1411 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_PERSPECTIVE_DISABLE (0x00000000U) 1412 1413 /* Use W */ 1414 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_PERSPECTIVE_ENABLE (0x00000001U) 1415 1416 /* The offset within the vertex if all data is treated as F32 (even if submitted 1417 * as F16). 1418 */ 1419 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_F32_OFFSET_MASK (0x000000FFU) 1420 1421 /* The offset within vertex taking into account the F16s and F32s present. */ 1422 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_F16_OFFSET_MASK (0x000000FFU) 1423 1424 /* TSP Parameter Fetch Interface DOutI, This command is only legal in a 1425 * coefficient loading program. 1426 */ 1427 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_MASK (0x1FFFFFFFU) 1428 1429 /* Apply depth bias to this layer. */ 1430 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_DEPTHBIAS_SHIFT (27U) 1431 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_DEPTHBIAS_CLRMSK (0xF7FFFFFFU) 1432 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_DEPTHBIAS_EN (0x08000000U) 1433 1434 /* Ignore the F16 and F32 offsets, and the WMODE and send the primitive id 1435 * instead. 1436 */ 1437 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_PRIMITIVEID_SHIFT (26U) 1438 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_PRIMITIVEID_CLRMSK (0xFBFFFFFFU) 1439 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_PRIMITIVEID_EN (0x04000000U) 1440 1441 /* Shade Model for Layer. */ 1442 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SHADEMODEL_SHIFT (24U) 1443 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SHADEMODEL_CLRMSK (0xFCFFFFFFU) 1444 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SHADEMODEL_FLAT_VERTEX0 \ 1445 (0x00000000U) 1446 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SHADEMODEL_FLAT_VERTEX1 \ 1447 (0x01000000U) 1448 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SHADEMODEL_FLAT_VERTEX2 \ 1449 (0x02000000U) 1450 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SHADEMODEL_GOURAUD (0x03000000U) 1451 1452 /* Point sprite Forced. */ 1453 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_POINTSPRITE_SHIFT (23U) 1454 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_POINTSPRITE_CLRMSK (0xFF7FFFFFU) 1455 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_POINTSPRITE_EN (0x00800000U) 1456 1457 /* Wrap S Coordinate. */ 1458 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_WRAPS_SHIFT (22U) 1459 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_WRAPS_CLRMSK (0xFFBFFFFFU) 1460 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_WRAPS_EN (0x00400000U) 1461 1462 /* Wrap V Coordinate. */ 1463 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_WRAPV_SHIFT (21U) 1464 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_WRAPV_CLRMSK (0xFFDFFFFFU) 1465 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_WRAPV_EN (0x00200000U) 1466 1467 /* Wrap U Coordinate. */ 1468 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_WRAPU_SHIFT (20U) 1469 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_WRAPU_CLRMSK (0xFFEFFFFFU) 1470 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_WRAPU_EN (0x00100000U) 1471 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SIZE_SHIFT (18U) 1472 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SIZE_CLRMSK (0xFFF3FFFFU) 1473 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SIZE_1D (0x00000000U) 1474 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SIZE_2D (0x00040000U) 1475 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SIZE_3D (0x00080000U) 1476 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_SIZE_4D (0x000C0000U) 1477 1478 /* Issue is for F16 precision values. */ 1479 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_F16_SHIFT (17U) 1480 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_F16_CLRMSK (0xFFFDFFFFU) 1481 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_F16_EN (0x00020000U) 1482 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_PERSPECTIVE_SHIFT (16U) 1483 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_PERSPECTIVE_CLRMSK (0xFFFEFFFFU) 1484 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_PERSPECTIVE_DISABLE \ 1485 (0x00000000U) 1486 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_PERSPECTIVE_ENABLE (0x00010000U) 1487 /* The offset within the vertex if all data is treated as F32 (even if submitted 1488 * as F16). 1489 */ 1490 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_F32_OFFSET_SHIFT (8U) 1491 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_F32_OFFSET_CLRMSK (0xFFFF00FFU) 1492 1493 /* The offset within vertex taking into account the F16s and F32s present. */ 1494 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_F16_OFFSET_SHIFT (0U) 1495 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_F16_OFFSET_CLRMSK (0xFFFFFF00U) 1496 1497 /* The starting address to write the data into the common store allocation, in 1498 * 128 bit words. Each 32 bit value consumes 128 bit words in the common store. 1499 * The issues are pack, Issue 0, followed by Issue 1. 1500 */ 1501 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_DEST_MASK (0x000000FFU) 1502 1503 /* TSP Parameter Fetch Interface DOutI : Src0 */ 1504 1505 /* This is the last issue for the triangle. */ 1506 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE_SHIFT (63U) 1507 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE_CLRMSK \ 1508 (UINT64_C(0x7FFFFFFFFFFFFFFF)) 1509 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE_EN \ 1510 (UINT64_C(0x8000000000000000)) 1511 1512 /* The starting address to write the data into the common store allocation, in 1513 * 128 bit words. Each 32 bit value consumes 128 bit words in the common store. 1514 * The issues are pack, Issue 0, followed by Issue 1. 1515 */ 1516 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_DEST_SHIFT (54U) 1517 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_DEST_CLRMSK \ 1518 (UINT64_C(0xC03FFFFFFFFFFFFF)) 1519 1520 /* Issue 0 */ 1521 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_SHIFT (0U) 1522 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_CLRMSK \ 1523 (UINT64_C(0xFFFFFFFFE0000000)) 1524 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_DEPTHBIAS_SHIFT (27U) 1525 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_DEPTHBIAS_CLRMSK \ 1526 (UINT64_C(0xfffffffff7ffffff)) 1527 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_PRIMITIVEID_SHIFT (26U) 1528 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_PRIMITIVEID_CLRMSK \ 1529 (UINT64_C(0xfffffffffbffffff)) 1530 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_SHADEMODEL_SHIFT (24U) 1531 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_SHADEMODEL_CLRMSK \ 1532 (UINT64_C(0xfffffffffcffffff)) 1533 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_POINTSPRITE_SHIFT (23U) 1534 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_POINTSPRITE_CLRMSK \ 1535 (UINT64_C(0xffffffffff7fffff)) 1536 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_WRAPS_SHIFT (22U) 1537 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_WRAPS_CLRMSK \ 1538 (UINT64_C(0xffffffffffbfffff)) 1539 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_WRAPV_SHIFT (21U) 1540 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_WRAPV_CLRMSK \ 1541 (UINT64_C(0xffffffffffdfffff)) 1542 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_WRAPU_SHIFT (20U) 1543 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_WRAPU_CLRMSK \ 1544 (UINT64_C(0xffffffffffefffff)) 1545 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_SIZE_SHIFT (18U) 1546 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_SIZE_CLRMSK \ 1547 (UINT64_C(0xfffffffffff3ffff)) 1548 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_F16_SHIFT (17U) 1549 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_F16_CLRMSK \ 1550 (UINT64_C(0xfffffffffffdffff)) 1551 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_PERSPECTIVE_SHIFT (16U) 1552 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_PERSPECTIVE_CLRMSK \ 1553 (UINT64_C(0xfffffffffffeffff)) 1554 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_F32_OFFSET_SHIFT (8U) 1555 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_F32_OFFSET_CLRMSK \ 1556 (UINT64_C(0xffffffffffff00ff)) 1557 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_F16_OFFSET_SHIFT (0U) 1558 #define PVR_ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC0_ISSUE0_F16_OFFSET_CLRMSK \ 1559 (UINT64_C(0xffffffffffffff00)) 1560 1561 /* TSP Parameter Fetch Interface DOutI : Src1 */ 1562 1563 /* 32-bit Temp or DOUT. */ 1564 #define PVR_ROGUE_PDSINST_DSTDOUT_MASK (0x00000007U) 1565 1566 /* DMA data from memory to the USC. */ 1567 #define PVR_ROGUE_PDSINST_DSTDOUT_DOUTD (0x00000000U) 1568 1569 /* Write a value directly to the USC. */ 1570 #define PVR_ROGUE_PDSINST_DSTDOUT_DOUTW (0x00000001U) 1571 1572 /* Start a USC program. */ 1573 #define PVR_ROGUE_PDSINST_DSTDOUT_DOUTU (0x00000002U) 1574 1575 /* Issue a fence back to the VDM (with value). */ 1576 #define PVR_ROGUE_PDSINST_DSTDOUT_DOUTV (0x00000003U) 1577 1578 /* Issue a command to the TSP Parameter Fetch and FPU to calculate and load 1579 * coefficients to USC. 1580 */ 1581 #define PVR_ROGUE_PDSINST_DSTDOUT_DOUTI (0x00000004U) 1582 1583 /* Issue a fence back to the CDM. Used if compute is enabled. */ 1584 #define PVR_ROGUE_PDSINST_DSTDOUT_DOUTC (0x00000005U) 1585 1586 /* Issue DOUT to external devices (Opcode SP) 1587 * 1588 * cc ? dst = src0, src1 1589 * 1590 * PDS programs have to send data somewhere. This is primary function of the 1591 * PDS. All programs must therefore execute some one of DOUT, DDMAD, STM 1592 * commands. There are the following program types 1593 * 1594 * Vertex Shader, Geometry Shader, Hull Shader Programs These programs load data 1595 * into memory. These will use the DOUTD or DDMAD commands. Ideally the DDMAD 1596 * command is used as the most typical operation Src Address = Index * Stride + 1597 * Base, and then DMA from this address. They also schedule the execution of the 1598 * USSE and will issue a DOUTU command. This would normally be the last 1599 * instruction in the program. 1600 * 1601 * Obviously the shader programs must not overflow their allocated memory. 1602 * However, the USC will do cache look-aheads and so could attempt to fetch 1603 * shader code from beyond the end of the program. This could cause a page fault 1604 * if the last program instructions are very close to the end of the last valid 1605 * memory page. 1606 * 1607 * To avoid this happening always ensure that the start address of the last 1608 * instruction of a shader program does not occur in the last 26 bytes of a 1609 * page. 1610 * 1611 * State/Uniform Loading Programs 1612 * These programs load data into memory. These will use the typically use the 1613 * DOUTD command 1614 * 1615 * Coefficient Loading Programs 1616 * These programs run once per triangle. They load the A,B,C Coefficient for the 1617 * iteration of the varyings into the USC. These programs issue DOUTI 1618 * commands. These programs must not do any other sort of DOUT command 1619 * (DOUTW/DOUTD/DOUTU). 1620 * 1621 * Pixel Shader Programs 1622 * These programs once per group of pixels, schedule the execution of a pixel 1623 * shader on the USC for a group of pixels. This program issues a DOUTU (and 1624 * that is all). 1625 */ 1626 1627 #define PVR_ROGUE_PDSINST_DOUT_OPCODE_SHIFT (28U) 1628 #define PVR_ROGUE_PDSINST_DOUT_OPCODE_CLRMSK (0x0FFFFFFFU) 1629 #define PVR_ROGUE_PDSINST_DOUT_OPCODE_DEFAULT (0xF0000000U) /* DOUT */ 1630 #define PVR_ROGUE_PDSINST_DOUT_CC_SHIFT (27U) 1631 #define PVR_ROGUE_PDSINST_DOUT_CC_CLRMSK (0xF7FFFFFFU) 1632 #define PVR_ROGUE_PDSINST_DOUT_CC_DISABLE (0x00000000U) 1633 #define PVR_ROGUE_PDSINST_DOUT_CC_ENABLE (0x08000000U) 1634 #define PVR_ROGUE_PDSINST_DOUT_END_SHIFT (26U) 1635 #define PVR_ROGUE_PDSINST_DOUT_END_CLRMSK (0xFBFFFFFFU) 1636 #define PVR_ROGUE_PDSINST_DOUT_END_DISABLE (0x00000000U) 1637 #define PVR_ROGUE_PDSINST_DOUT_END_ENABLE (0x04000000U) 1638 1639 /* 32-bit source */ 1640 #define PVR_ROGUE_PDSINST_DOUT_SRC1_SHIFT (16U) 1641 #define PVR_ROGUE_PDSINST_DOUT_SRC1_CLRMSK (0xFF00FFFFU) 1642 1643 /* 64-bit source */ 1644 #define PVR_ROGUE_PDSINST_DOUT_SRC0_SHIFT (8U) 1645 #define PVR_ROGUE_PDSINST_DOUT_SRC0_CLRMSK (0xFFFF80FFU) 1646 1647 /* DOUT Destination */ 1648 #define PVR_ROGUE_PDSINST_DOUT_DST_SHIFT (0U) 1649 #define PVR_ROGUE_PDSINST_DOUT_DST_CLRMSK (0xFFFFFFF8U) 1650 #define PVR_ROGUE_PDSINST_DOUT_DST_DOUTD (0x00000000U) 1651 #define PVR_ROGUE_PDSINST_DOUT_DST_DOUTW (0x00000001U) 1652 #define PVR_ROGUE_PDSINST_DOUT_DST_DOUTU (0x00000002U) 1653 #define PVR_ROGUE_PDSINST_DOUT_DST_DOUTV (0x00000003U) 1654 #define PVR_ROGUE_PDSINST_DOUT_DST_DOUTI (0x00000004U) 1655 #if defined(ROGUE_FEATURE_COMPUTE) 1656 # define PVR_ROGUE_PDSINST_DOUT_DST_DOUTC (0x00000005U) 1657 #endif /* ROGUE_FEATURE_COMPUTE */ 1658 1659 /* Shift */ 1660 1661 #endif /* PVR_ROGUE_PDS_DEFS_H */ 1662