| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 332 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank()
363 getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits, in getMinClassForRegBank()
1011 const RegisterBank &RB = *RBI.getRegBank(LHS, MRI, TRI); in selectCompareBranch() local
1442 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in select() local
1593 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select() local
1851 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select() local
1924 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select() local
1968 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select() local
2811 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI); in selectMergeValues() local
3208 getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) { in getInsertVecEltOpInfo()
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| D | AArch64RegisterBankInfo.cpp | 95 #define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \ in AArch64RegisterBankInfo() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 93 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getRegBank() local
140 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in constrainGenericRegister() local
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| D | CSEInfo.cpp | 347 auto *RB = MRI.getRegBankOrNull(Reg); in addNodeIDMachineOperand() local
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| /third_party/parse5/packages/parse5/lib/common/ |
| D | html.ts | 134 RB = 'rb', enumerator
306 RB, enumerator
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| /third_party/flutter/skia/gm/ |
| D | image.cpp | 115 RB = W * 4 + 8, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 87 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in isVCC() local
190 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in selectPHI() local
1311 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getArtifactRegBank() local
1433 const RegisterBank *RB = MRI->getRegBankOrNull(I.getOperand(0).getReg()); in selectG_CONSTANT() local
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| D | SIRegisterInfo.cpp | 1766 const RegisterBank &RB, in getRegClassForSizeOnBank()
1818 if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>()) in getConstrainedRegClassForOperand() local
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| D | AMDGPURegisterBankInfo.cpp | 51 MachineRegisterInfo &MRI_, const RegisterBank *RB) in ApplyRegBankMapping()
108 const RegisterBank *RB = NewBank; in applyBank() local
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| /third_party/skia/gm/ |
| D | image.cpp | 121 RB = W * 4 + 8, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 395 const RegisterBank &RB, in getLoadStoreOp()
509 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 473 const MachineOperand &RB = MI.getOperand(3); in computePhiCost() local
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| D | HexagonVLIWPacketizer.cpp | 251 MachineBasicBlock::iterator RB = Begin; in runOnMachineFunction() local
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| D | HexagonHardwareLoops.cpp | 1758 const RegisterBump &RB = I->second; in fixupInductionVariable() local
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| D | HexagonGenInsert.cpp | 627 void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB, in buildOrderingBT()
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| /third_party/skia/third_party/externals/swiftshader/src/Device/ |
| D | BC_Decoder.cpp | 1112 const int RB; // Rotation bits member
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