1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #ifndef _ROCKCHIP_DRM_VOP_H
8 #define _ROCKCHIP_DRM_VOP_H
9
10 /*
11 * major: IP major version, used for IP structure
12 * minor: big feature change under same structure
13 */
14 #define VOP_VERSION(major, minor) ((major) << 8 | (minor))
15 #define VOP_MAJOR(version) ((version) >> 8)
16 #define VOP_MINOR(version) ((version) & 0xff)
17
18 #define NUM_YUV2YUV_COEFFICIENTS 12
19
20 /* AFBC supports a number of configurable modes. Relevant to us is block size
21 * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like
22 * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode
23 * could be enabled via the hreg_block_split register, but is not currently
24 * handled. The colourspace transform is implicitly always assumed by the
25 * decoder, so consumers must use this transform as well.
26 *
27 * Failure to match modifiers will cause errors displaying AFBC buffers
28 * produced by conformant AFBC producers, including Mesa.
29 */
30 #define ROCKCHIP_AFBC_MOD \
31 DRM_FORMAT_MOD_ARM_AFBC( \
32 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \
33 | AFBC_FORMAT_MOD_YTR \
34 )
35
36 enum vop_data_format {
37 VOP_FMT_ARGB8888 = 0,
38 VOP_FMT_RGB888,
39 VOP_FMT_RGB565,
40 VOP_FMT_YUV420SP = 4,
41 VOP_FMT_YUV422SP,
42 VOP_FMT_YUV444SP,
43 };
44
45 struct vop_reg {
46 uint32_t mask;
47 uint16_t offset;
48 uint8_t shift;
49 bool write_mask;
50 bool relaxed;
51 };
52
53 struct vop_afbc {
54 struct vop_reg enable;
55 struct vop_reg win_sel;
56 struct vop_reg format;
57 struct vop_reg hreg_block_split;
58 struct vop_reg pic_size;
59 struct vop_reg hdr_ptr;
60 struct vop_reg rstn;
61 };
62
63 struct vop_modeset {
64 struct vop_reg htotal_pw;
65 struct vop_reg hact_st_end;
66 struct vop_reg hpost_st_end;
67 struct vop_reg vtotal_pw;
68 struct vop_reg vact_st_end;
69 struct vop_reg vpost_st_end;
70 };
71
72 struct vop_output {
73 struct vop_reg pin_pol;
74 struct vop_reg dp_pin_pol;
75 struct vop_reg dp_dclk_pol;
76 struct vop_reg edp_pin_pol;
77 struct vop_reg edp_dclk_pol;
78 struct vop_reg hdmi_pin_pol;
79 struct vop_reg hdmi_dclk_pol;
80 struct vop_reg mipi_pin_pol;
81 struct vop_reg mipi_dclk_pol;
82 struct vop_reg rgb_pin_pol;
83 struct vop_reg rgb_dclk_pol;
84 struct vop_reg dp_en;
85 struct vop_reg edp_en;
86 struct vop_reg hdmi_en;
87 struct vop_reg mipi_en;
88 struct vop_reg mipi_dual_channel_en;
89 struct vop_reg rgb_en;
90 };
91
92 struct vop_common {
93 struct vop_reg cfg_done;
94 struct vop_reg dsp_blank;
95 struct vop_reg data_blank;
96 struct vop_reg pre_dither_down;
97 struct vop_reg dither_down_sel;
98 struct vop_reg dither_down_mode;
99 struct vop_reg dither_down_en;
100 struct vop_reg dither_up;
101 struct vop_reg dsp_lut_en;
102 struct vop_reg gate_en;
103 struct vop_reg mmu_en;
104 struct vop_reg out_mode;
105 struct vop_reg standby;
106 };
107
108 struct vop_misc {
109 struct vop_reg global_regdone_en;
110 };
111
112 struct vop_intr {
113 const int *intrs;
114 uint32_t nintrs;
115
116 struct vop_reg line_flag_num[2];
117 struct vop_reg enable;
118 struct vop_reg clear;
119 struct vop_reg status;
120 };
121
122 struct vop_scl_extension {
123 struct vop_reg cbcr_vsd_mode;
124 struct vop_reg cbcr_vsu_mode;
125 struct vop_reg cbcr_hsd_mode;
126 struct vop_reg cbcr_ver_scl_mode;
127 struct vop_reg cbcr_hor_scl_mode;
128 struct vop_reg yrgb_vsd_mode;
129 struct vop_reg yrgb_vsu_mode;
130 struct vop_reg yrgb_hsd_mode;
131 struct vop_reg yrgb_ver_scl_mode;
132 struct vop_reg yrgb_hor_scl_mode;
133 struct vop_reg line_load_mode;
134 struct vop_reg cbcr_axi_gather_num;
135 struct vop_reg yrgb_axi_gather_num;
136 struct vop_reg vsd_cbcr_gt2;
137 struct vop_reg vsd_cbcr_gt4;
138 struct vop_reg vsd_yrgb_gt2;
139 struct vop_reg vsd_yrgb_gt4;
140 struct vop_reg bic_coe_sel;
141 struct vop_reg cbcr_axi_gather_en;
142 struct vop_reg yrgb_axi_gather_en;
143 struct vop_reg lb_mode;
144 };
145
146 struct vop_scl_regs {
147 const struct vop_scl_extension *ext;
148
149 struct vop_reg scale_yrgb_x;
150 struct vop_reg scale_yrgb_y;
151 struct vop_reg scale_cbcr_x;
152 struct vop_reg scale_cbcr_y;
153 };
154
155 struct vop_yuv2yuv_phy {
156 struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];
157 };
158
159 struct vop_win_phy {
160 const struct vop_scl_regs *scl;
161 const uint32_t *data_formats;
162 uint32_t nformats;
163 const uint64_t *format_modifiers;
164
165 struct vop_reg enable;
166 struct vop_reg gate;
167 struct vop_reg format;
168 struct vop_reg rb_swap;
169 struct vop_reg act_info;
170 struct vop_reg dsp_info;
171 struct vop_reg dsp_st;
172 struct vop_reg yrgb_mst;
173 struct vop_reg uv_mst;
174 struct vop_reg yrgb_vir;
175 struct vop_reg uv_vir;
176 struct vop_reg y_mir_en;
177 struct vop_reg x_mir_en;
178
179 struct vop_reg dst_alpha_ctl;
180 struct vop_reg src_alpha_ctl;
181 struct vop_reg alpha_pre_mul;
182 struct vop_reg alpha_mode;
183 struct vop_reg alpha_en;
184 struct vop_reg channel;
185 };
186
187 struct vop_win_yuv2yuv_data {
188 uint32_t base;
189 const struct vop_yuv2yuv_phy *phy;
190 struct vop_reg y2r_en;
191 };
192
193 struct vop_win_data {
194 uint32_t base;
195 const struct vop_win_phy *phy;
196 enum drm_plane_type type;
197 };
198
199 struct vop_data {
200 uint32_t version;
201 const struct vop_intr *intr;
202 const struct vop_common *common;
203 const struct vop_misc *misc;
204 const struct vop_modeset *modeset;
205 const struct vop_output *output;
206 const struct vop_afbc *afbc;
207 const struct vop_win_yuv2yuv_data *win_yuv2yuv;
208 const struct vop_win_data *win;
209 unsigned int win_size;
210 unsigned int lut_size;
211
212 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
213 #define VOP_FEATURE_INTERNAL_RGB BIT(1)
214 u64 feature;
215 };
216
217 /* interrupt define */
218 #define DSP_HOLD_VALID_INTR (1 << 0)
219 #define FS_INTR (1 << 1)
220 #define LINE_FLAG_INTR (1 << 2)
221 #define BUS_ERROR_INTR (1 << 3)
222
223 #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
224 LINE_FLAG_INTR | BUS_ERROR_INTR)
225
226 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
227 #define FS_INTR_EN(x) ((x) << 5)
228 #define LINE_FLAG_INTR_EN(x) ((x) << 6)
229 #define BUS_ERROR_INTR_EN(x) ((x) << 7)
230 #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
231 #define FS_INTR_MASK (1 << 5)
232 #define LINE_FLAG_INTR_MASK (1 << 6)
233 #define BUS_ERROR_INTR_MASK (1 << 7)
234
235 #define INTR_CLR_SHIFT 8
236 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
237 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
238 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
239 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
240
241 #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
242 #define DSP_LINE_NUM_MASK (0x1fff << 12)
243
244 /* src alpha ctrl define */
245 #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
246 #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
247 #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
248 #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
249 #define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
250 #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
251 #define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
252 #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
253 /* dst alpha ctrl define */
254 #define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
255
256 /*
257 * display output interface supported by rockchip lcdc
258 */
259 #define ROCKCHIP_OUT_MODE_P888 0
260 #define ROCKCHIP_OUT_MODE_P666 1
261 #define ROCKCHIP_OUT_MODE_P565 2
262 /* for use special outface */
263 #define ROCKCHIP_OUT_MODE_AAAA 15
264
265 /* output flags */
266 #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0)
267
268 enum alpha_mode {
269 ALPHA_STRAIGHT,
270 ALPHA_INVERSE,
271 };
272
273 enum global_blend_mode {
274 ALPHA_GLOBAL,
275 ALPHA_PER_PIX,
276 ALPHA_PER_PIX_GLOBAL,
277 };
278
279 enum alpha_cal_mode {
280 ALPHA_SATURATION,
281 ALPHA_NO_SATURATION,
282 };
283
284 enum color_mode {
285 ALPHA_SRC_PRE_MUL,
286 ALPHA_SRC_NO_PRE_MUL,
287 };
288
289 enum factor_mode {
290 ALPHA_ZERO,
291 ALPHA_ONE,
292 ALPHA_SRC,
293 ALPHA_SRC_INVERSE,
294 ALPHA_SRC_GLOBAL,
295 };
296
297 enum scale_mode {
298 SCALE_NONE = 0x0,
299 SCALE_UP = 0x1,
300 SCALE_DOWN = 0x2
301 };
302
303 enum lb_mode {
304 LB_YUV_3840X5 = 0x0,
305 LB_YUV_2560X8 = 0x1,
306 LB_RGB_3840X2 = 0x2,
307 LB_RGB_2560X4 = 0x3,
308 LB_RGB_1920X5 = 0x4,
309 LB_RGB_1280X8 = 0x5
310 };
311
312 enum sacle_up_mode {
313 SCALE_UP_BIL = 0x0,
314 SCALE_UP_BIC = 0x1
315 };
316
317 enum scale_down_mode {
318 SCALE_DOWN_BIL = 0x0,
319 SCALE_DOWN_AVG = 0x1
320 };
321
322 enum dither_down_mode {
323 RGB888_TO_RGB565 = 0x0,
324 RGB888_TO_RGB666 = 0x1
325 };
326
327 enum dither_down_mode_sel {
328 DITHER_DOWN_ALLEGRO = 0x0,
329 DITHER_DOWN_FRC = 0x1
330 };
331
332 enum vop_pol {
333 HSYNC_POSITIVE = 0,
334 VSYNC_POSITIVE = 1,
335 DEN_NEGATIVE = 2
336 };
337
338 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
339 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
340 #define SCL_MAX_VSKIPLINES 4
341 #define MIN_SCL_FT_AFTER_VSKIP 1
342
scl_cal_scale(int src,int dst,int shift)343 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
344 {
345 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
346 }
347
scl_cal_scale2(int src,int dst)348 static inline uint16_t scl_cal_scale2(int src, int dst)
349 {
350 return ((src - 1) << 12) / (dst - 1);
351 }
352
353 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
354 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
355 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
356
scl_get_bili_dn_vskip(int src_h,int dst_h,int vskiplines)357 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
358 int vskiplines)
359 {
360 int act_height;
361
362 act_height = DIV_ROUND_UP(src_h, vskiplines);
363
364 if (act_height == dst_h)
365 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
366
367 return GET_SCL_FT_BILI_DN(act_height, dst_h);
368 }
369
scl_get_scl_mode(int src,int dst)370 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
371 {
372 if (src < dst)
373 return SCALE_UP;
374 else if (src > dst)
375 return SCALE_DOWN;
376
377 return SCALE_NONE;
378 }
379
scl_get_vskiplines(uint32_t srch,uint32_t dsth)380 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
381 {
382 uint32_t vskiplines;
383
384 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
385 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
386 break;
387
388 return vskiplines;
389 }
390
scl_vop_cal_lb_mode(int width,bool is_yuv)391 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
392 {
393 int lb_mode;
394
395 if (is_yuv) {
396 if (width > 1280)
397 lb_mode = LB_YUV_3840X5;
398 else
399 lb_mode = LB_YUV_2560X8;
400 } else {
401 if (width > 2560)
402 lb_mode = LB_RGB_3840X2;
403 else if (width > 1920)
404 lb_mode = LB_RGB_2560X4;
405 else
406 lb_mode = LB_RGB_1920X5;
407 }
408
409 return lb_mode;
410 }
411
412 extern const struct component_ops vop_component_ops;
413 #endif /* _ROCKCHIP_DRM_VOP_H */
414