1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
4 #define _ASM_X86_NOSPEC_BRANCH_H_
5
6 #include <linux/static_key.h>
7 #include <linux/objtool.h>
8 #include <linux/linkage.h>
9
10 #include <asm/alternative.h>
11 #include <asm/cpufeatures.h>
12 #include <asm/msr-index.h>
13 #include <asm/unwind_hints.h>
14 #include <asm/percpu.h>
15
16 #define RETPOLINE_THUNK_SIZE 32
17
18 /*
19 * Fill the CPU return stack buffer.
20 *
21 * Each entry in the RSB, if used for a speculative 'ret', contains an
22 * infinite 'pause; lfence; jmp' loop to capture speculative execution.
23 *
24 * This is required in various cases for retpoline and IBRS-based
25 * mitigations for the Spectre variant 2 vulnerability. Sometimes to
26 * eliminate potentially bogus entries from the RSB, and sometimes
27 * purely to ensure that it doesn't get empty, which on some CPUs would
28 * allow predictions from other (unwanted!) sources to be used.
29 *
30 * We define a CPP macro such that it can be used from both .S files and
31 * inline assembly. It's possible to do a .macro and then include that
32 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
33 */
34
35 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
36
37 /*
38 * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN.
39 */
40 #define __FILL_RETURN_SLOT \
41 ANNOTATE_INTRA_FUNCTION_CALL; \
42 call 772f; \
43 int3; \
44 772:
45
46 /*
47 * Stuff the entire RSB.
48 *
49 * Google experimented with loop-unrolling and this turned out to be
50 * the optimal version — two calls, each with their own speculation
51 * trap should their return address end up getting used, in a loop.
52 */
53 #ifdef CONFIG_X86_64
54 #define __FILL_RETURN_BUFFER(reg, nr) \
55 mov $(nr/2), reg; \
56 771: \
57 __FILL_RETURN_SLOT \
58 __FILL_RETURN_SLOT \
59 add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \
60 dec reg; \
61 jnz 771b; \
62 /* barrier for jnz misprediction */ \
63 lfence;
64 #else
65 /*
66 * i386 doesn't unconditionally have LFENCE, as such it can't
67 * do a loop.
68 */
69 #define __FILL_RETURN_BUFFER(reg, nr) \
70 .rept nr; \
71 __FILL_RETURN_SLOT; \
72 .endr; \
73 add $(BITS_PER_LONG/8) * nr, %_ASM_SP;
74 #endif
75
76 /*
77 * Stuff a single RSB slot.
78 *
79 * To mitigate Post-Barrier RSB speculation, one CALL instruction must be
80 * forced to retire before letting a RET instruction execute.
81 *
82 * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed
83 * before this point.
84 */
85 #define __FILL_ONE_RETURN \
86 __FILL_RETURN_SLOT \
87 add $(BITS_PER_LONG/8), %_ASM_SP; \
88 lfence;
89
90 #ifdef __ASSEMBLY__
91
92 /*
93 * This should be used immediately before an indirect jump/call. It tells
94 * objtool the subsequent indirect jump/call is vouched safe for retpoline
95 * builds.
96 */
97 .macro ANNOTATE_RETPOLINE_SAFE
98 .Lannotate_\@:
99 .pushsection .discard.retpoline_safe
100 _ASM_PTR .Lannotate_\@
101 .popsection
102 .endm
103
104 /*
105 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
106 * vs RETBleed validation.
107 */
108 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
109
110 /*
111 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
112 * eventually turn into it's own annotation.
113 */
114 .macro ANNOTATE_UNRET_END
115 #ifdef CONFIG_DEBUG_ENTRY
116 ANNOTATE_RETPOLINE_SAFE
117 nop
118 #endif
119 .endm
120
121 /*
122 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
123 * indirect jmp/call which may be susceptible to the Spectre variant 2
124 * attack.
125 */
126 .macro JMP_NOSPEC reg:req
127 #ifdef CONFIG_RETPOLINE
128 ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \
129 __stringify(jmp __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
130 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_LFENCE
131 #else
132 jmp *%\reg
133 #endif
134 .endm
135
136 .macro CALL_NOSPEC reg:req
137 #ifdef CONFIG_RETPOLINE
138 ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *%\reg), \
139 __stringify(call __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
140 __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_LFENCE
141 #else
142 call *%\reg
143 #endif
144 .endm
145
146 /*
147 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
148 * monstrosity above, manually.
149 */
150 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS)
151 ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \
152 __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \
153 __stringify(__FILL_ONE_RETURN), \ftr2
154
155 .Lskip_rsb_\@:
156 .endm
157
158 #ifdef CONFIG_CPU_UNRET_ENTRY
159 #define CALL_ZEN_UNTRAIN_RET "call zen_untrain_ret"
160 #else
161 #define CALL_ZEN_UNTRAIN_RET ""
162 #endif
163
164 /*
165 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
166 * return thunk isn't mapped into the userspace tables (then again, AMD
167 * typically has NO_MELTDOWN).
168 *
169 * While zen_untrain_ret() doesn't clobber anything but requires stack,
170 * entry_ibpb() will clobber AX, CX, DX.
171 *
172 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
173 * where we have a stack but before any RET instruction.
174 */
175 .macro UNTRAIN_RET
176 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY)
177 ANNOTATE_UNRET_END
178 ALTERNATIVE_2 "", \
179 CALL_ZEN_UNTRAIN_RET, X86_FEATURE_UNRET, \
180 "call entry_ibpb", X86_FEATURE_ENTRY_IBPB
181 #endif
182 .endm
183
184 #else /* __ASSEMBLY__ */
185
186 #define ANNOTATE_RETPOLINE_SAFE \
187 "999:\n\t" \
188 ".pushsection .discard.retpoline_safe\n\t" \
189 _ASM_PTR " 999b\n\t" \
190 ".popsection\n\t"
191
192 extern void __x86_return_thunk(void);
193 extern void zen_untrain_ret(void);
194 extern void entry_ibpb(void);
195
196 #ifdef CONFIG_RETPOLINE
197
198 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
199
200 #define GEN(reg) \
201 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
202 #include <asm/GEN-for-each-reg.h>
203 #undef GEN
204
205 extern retpoline_thunk_t __x86_indirect_thunk_array[];
206
207 #ifdef CONFIG_X86_64
208
209 /*
210 * Inline asm uses the %V modifier which is only in newer GCC
211 * which is ensured when CONFIG_RETPOLINE is defined.
212 */
213 # define CALL_NOSPEC \
214 ALTERNATIVE_2( \
215 ANNOTATE_RETPOLINE_SAFE \
216 "call *%[thunk_target]\n", \
217 "call __x86_indirect_thunk_%V[thunk_target]\n", \
218 X86_FEATURE_RETPOLINE, \
219 "lfence;\n" \
220 ANNOTATE_RETPOLINE_SAFE \
221 "call *%[thunk_target]\n", \
222 X86_FEATURE_RETPOLINE_LFENCE)
223
224 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
225
226 #else /* CONFIG_X86_32 */
227 /*
228 * For i386 we use the original ret-equivalent retpoline, because
229 * otherwise we'll run out of registers. We don't care about CET
230 * here, anyway.
231 */
232 # define CALL_NOSPEC \
233 ALTERNATIVE_2( \
234 ANNOTATE_RETPOLINE_SAFE \
235 "call *%[thunk_target]\n", \
236 " jmp 904f;\n" \
237 " .align 16\n" \
238 "901: call 903f;\n" \
239 "902: pause;\n" \
240 " lfence;\n" \
241 " jmp 902b;\n" \
242 " .align 16\n" \
243 "903: lea 4(%%esp), %%esp;\n" \
244 " pushl %[thunk_target];\n" \
245 " ret;\n" \
246 " .align 16\n" \
247 "904: call 901b;\n", \
248 X86_FEATURE_RETPOLINE, \
249 "lfence;\n" \
250 ANNOTATE_RETPOLINE_SAFE \
251 "call *%[thunk_target]\n", \
252 X86_FEATURE_RETPOLINE_LFENCE)
253
254 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
255 #endif
256 #else /* No retpoline for C / inline asm */
257 # define CALL_NOSPEC "call *%[thunk_target]\n"
258 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
259 #endif
260
261 /* The Spectre V2 mitigation variants */
262 enum spectre_v2_mitigation {
263 SPECTRE_V2_NONE,
264 SPECTRE_V2_RETPOLINE,
265 SPECTRE_V2_LFENCE,
266 SPECTRE_V2_EIBRS,
267 SPECTRE_V2_EIBRS_RETPOLINE,
268 SPECTRE_V2_EIBRS_LFENCE,
269 SPECTRE_V2_IBRS,
270 };
271
272 /* The indirect branch speculation control variants */
273 enum spectre_v2_user_mitigation {
274 SPECTRE_V2_USER_NONE,
275 SPECTRE_V2_USER_STRICT,
276 SPECTRE_V2_USER_STRICT_PREFERRED,
277 SPECTRE_V2_USER_PRCTL,
278 SPECTRE_V2_USER_SECCOMP,
279 };
280
281 /* The Speculative Store Bypass disable variants */
282 enum ssb_mitigation {
283 SPEC_STORE_BYPASS_NONE,
284 SPEC_STORE_BYPASS_DISABLE,
285 SPEC_STORE_BYPASS_PRCTL,
286 SPEC_STORE_BYPASS_SECCOMP,
287 };
288
289 extern char __indirect_thunk_start[];
290 extern char __indirect_thunk_end[];
291
292 static __always_inline
alternative_msr_write(unsigned int msr,u64 val,unsigned int feature)293 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
294 {
295 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
296 : : "c" (msr),
297 "a" ((u32)val),
298 "d" ((u32)(val >> 32)),
299 [feature] "i" (feature)
300 : "memory");
301 }
302
indirect_branch_prediction_barrier(void)303 static inline void indirect_branch_prediction_barrier(void)
304 {
305 u64 val = PRED_CMD_IBPB;
306
307 alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
308 }
309
310 /* The Intel SPEC CTRL MSR base value cache */
311 extern u64 x86_spec_ctrl_base;
312 DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
313 extern void update_spec_ctrl_cond(u64 val);
314 extern u64 spec_ctrl_current(void);
315
316 /*
317 * With retpoline, we must use IBRS to restrict branch prediction
318 * before calling into firmware.
319 *
320 * (Implemented as CPP macros due to header hell.)
321 */
322 #define firmware_restrict_branch_speculation_start() \
323 do { \
324 preempt_disable(); \
325 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
326 spec_ctrl_current() | SPEC_CTRL_IBRS, \
327 X86_FEATURE_USE_IBRS_FW); \
328 alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \
329 X86_FEATURE_USE_IBPB_FW); \
330 } while (0)
331
332 #define firmware_restrict_branch_speculation_end() \
333 do { \
334 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
335 spec_ctrl_current(), \
336 X86_FEATURE_USE_IBRS_FW); \
337 preempt_enable(); \
338 } while (0)
339
340 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
341 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
342 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
343
344 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
345 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
346
347 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
348
349 #include <asm/segment.h>
350
351 /**
352 * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
353 *
354 * This uses the otherwise unused and obsolete VERW instruction in
355 * combination with microcode which triggers a CPU buffer flush when the
356 * instruction is executed.
357 */
mds_clear_cpu_buffers(void)358 static __always_inline void mds_clear_cpu_buffers(void)
359 {
360 static const u16 ds = __KERNEL_DS;
361
362 /*
363 * Has to be the memory-operand variant because only that
364 * guarantees the CPU buffer flush functionality according to
365 * documentation. The register-operand variant does not.
366 * Works with any segment selector, but a valid writable
367 * data segment is the fastest variant.
368 *
369 * "cc" clobber is required because VERW modifies ZF.
370 */
371 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
372 }
373
374 /**
375 * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
376 *
377 * Clear CPU buffers if the corresponding static key is enabled
378 */
mds_user_clear_cpu_buffers(void)379 static __always_inline void mds_user_clear_cpu_buffers(void)
380 {
381 if (static_branch_likely(&mds_user_clear))
382 mds_clear_cpu_buffers();
383 }
384
385 /**
386 * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
387 *
388 * Clear CPU buffers if the corresponding static key is enabled
389 */
mds_idle_clear_cpu_buffers(void)390 static inline void mds_idle_clear_cpu_buffers(void)
391 {
392 if (static_branch_likely(&mds_idle_clear))
393 mds_clear_cpu_buffers();
394 }
395
396 #endif /* __ASSEMBLY__ */
397
398 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
399