| /third_party/skia/third_party/externals/oboe/samples/RhythmGame/third_party/glm/simd/ |
| D | integer.h | 16 glm_uvec4 Reg1; in glm_i128_interleave() local
70 glm_uvec4 Reg1; in glm_i128_interleave2() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | Locked.cpp | 89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | Locked.cpp | 86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 506 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
519 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
557 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
568 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1867 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing()
1890 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing()
1906 unsigned Reg1 = AArch64::NoRegister; member
2131 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
2239 unsigned Reg1 = RPI.Reg1; in restoreCalleeSavedRegisters() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
243 unsigned Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
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| D | MipsAsmPrinter.cpp | 875 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg()
895 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg()
906 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair()
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| D | MipsSEFrameLowering.cpp | 465 unsigned Reg1 = in emitPrologue() local
482 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
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| D | Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 165 unsigned Reg1, bool isKill1, in addRegReg()
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| D | X86MCInstLower.cpp | 2056 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1); in EmitInstruction() local
2087 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1); in EmitInstruction() local
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| D | X86AvoidStoreForwardingBlocks.cpp | 395 Register Reg1 = MRI->createVirtualRegister( in buildCopy() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 668 unsigned Reg1 = Reg; in lowerCRSpilling() local
713 unsigned Reg1 = Reg; in lowerCRRestore() local
817 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
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| D | PPCVSXSwapRemoval.cpp | 872 Register Reg1 = MI->getOperand(1).getReg(); in handleSpecialSwappables() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 402 unsigned Reg1, in getOperandGatherWeight()
540 unsigned Reg1 = OperandMasks[I].Reg; in collectCandidates() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 77 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains()
740 uint16_t Reg1 = 0; variable
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1382 StringRef Reg1(R1); in processInstruction() local
1397 StringRef Reg1(R1); in processInstruction() local
1413 StringRef Reg1(R1); in processInstruction() local
1745 StringRef Reg1(R1); in processInstruction() local
1889 StringRef Reg1(R1); in processInstruction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 835 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress()
900 Register Reg1, Reg2; in parseAddress() local
1214 Register Reg1, Reg2; in parseOperand() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 1438 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1451 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1506 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1553 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 449 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence()
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| D | Thumb2SizeReduction.cpp | 747 Register Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 633 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 94 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 98 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
|