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Searched defs:RegClass (Results 1 – 25 of 31) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp33 const TargetRegisterClass &RegClass) { in constrainRegToClass()
44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO, in constrainOperandRegClass()
79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; variable
/third_party/mesa3d/src/amd/compiler/
Daco_ir.h308 struct RegClass { struct
310 enum RC : uint8_t {
339 constexpr RegClass(RC rc_) : rc(rc_) {} in RegClass() argument
340 constexpr RegClass(RegType type, unsigned size) in RegClass() function
354 constexpr RegClass as_linear() const { return RegClass((RC)(rc | (1 << 6))); } in as_linear() argument
355 constexpr RegClass as_subdword() const { return RegClass((RC)(rc | 1 << 7)); } in as_subdword() argument
357 static constexpr RegClass get(RegType type, unsigned bytes) in get() argument
366 constexpr RegClass resize(unsigned bytes) const in resize() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyPeephole.cpp97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
DWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
609 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceTypes.h36 enum RegClass : uint8_t { enum
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DRDFRegisters.h136 const TargetRegisterClass *RegClass = nullptr; member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
DMachineRegisterInfo.cpp158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister()
DTargetInstrInfo.cpp52 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
DLiveIntervals.cpp1671 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in splitSeparateComponents() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUMachineCFGStructurizer.cpp1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2176 const TargetRegisterClass *RegClass = in createEntryPHI() local
2314 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2451 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
DAMDGPUISelDAGToDAG.cpp588 int RegClass = Desc.OpInfo[OpIdx].RegClass; in getOperandRegClass() local
686 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp483 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
DARMISelDAGToDAG.cpp1778 SDValue RegClass = in createGPRPairNode() local
1789 SDValue RegClass = in createSRegPairNode() local
1800 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1811 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1823 SDValue RegClass = in createQuadSRegsNode() local
1838 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1853 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
DARMBaseRegisterInfo.cpp814 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
DARMFrameLowering.cpp1533 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); in estimateRSStackSizeLimit() local
DARMLoadStoreOptimizer.cpp581 unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) { in findFreeReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp1286 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef() local
1416 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename() local
DAArch64AsmPrinter.cpp706 const TargetRegisterClass *RegClass; in PrintAsmOperand() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FrameLowering.cpp586 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInline() local
2744 auto &RegClass = in adjustStackWithPops() local
DX86ISelDAGToDAG.cpp4315 unsigned RegClass = getMaskRC(MaskVT); in tryVPTESTM() local
4353 unsigned RegClass = getMaskRC(ResVT); in tryVPTESTM() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp119 #define DECODE_OPERAND_REG(RegClass) \ argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp2026 const TargetRegisterClass *RegClass = in constrainOperandRegClass() local
DScheduleDAGRRList.cpp313 unsigned &RegClass, unsigned &Cost, in GetCostForDef()

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