1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
5 */
6
7 #ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H
8 #define __LINUX_MTD_SPI_NOR_INTERNAL_H
9
10 #include "sfdp.h"
11
12 #define SPI_NOR_MAX_ID_LEN 6
13
14 enum spi_nor_option_flags {
15 SNOR_F_USE_FSR = BIT(0),
16 SNOR_F_HAS_SR_TB = BIT(1),
17 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
18 SNOR_F_READY_XSR_RDY = BIT(3),
19 SNOR_F_USE_CLSR = BIT(4),
20 SNOR_F_BROKEN_RESET = BIT(5),
21 SNOR_F_4B_OPCODES = BIT(6),
22 SNOR_F_HAS_4BAIT = BIT(7),
23 SNOR_F_HAS_LOCK = BIT(8),
24 SNOR_F_HAS_16BIT_SR = BIT(9),
25 SNOR_F_NO_READ_CR = BIT(10),
26 SNOR_F_HAS_SR_TB_BIT6 = BIT(11),
27 SNOR_F_HAS_4BIT_BP = BIT(12),
28 SNOR_F_HAS_SR_BP3_BIT6 = BIT(13),
29 };
30
31 struct spi_nor_read_command {
32 u8 num_mode_clocks;
33 u8 num_wait_states;
34 u8 opcode;
35 enum spi_nor_protocol proto;
36 };
37
38 struct spi_nor_pp_command {
39 u8 opcode;
40 enum spi_nor_protocol proto;
41 };
42
43 enum spi_nor_read_command_index {
44 SNOR_CMD_READ,
45 SNOR_CMD_READ_FAST,
46 SNOR_CMD_READ_1_1_1_DTR,
47
48 /* Dual SPI */
49 SNOR_CMD_READ_1_1_2,
50 SNOR_CMD_READ_1_2_2,
51 SNOR_CMD_READ_2_2_2,
52 SNOR_CMD_READ_1_2_2_DTR,
53
54 /* Quad SPI */
55 SNOR_CMD_READ_1_1_4,
56 SNOR_CMD_READ_1_4_4,
57 SNOR_CMD_READ_4_4_4,
58 SNOR_CMD_READ_1_4_4_DTR,
59
60 /* Octal SPI */
61 SNOR_CMD_READ_1_1_8,
62 SNOR_CMD_READ_1_8_8,
63 SNOR_CMD_READ_8_8_8,
64 SNOR_CMD_READ_1_8_8_DTR,
65
66 SNOR_CMD_READ_MAX
67 };
68
69 enum spi_nor_pp_command_index {
70 SNOR_CMD_PP,
71
72 /* Quad SPI */
73 SNOR_CMD_PP_1_1_4,
74 SNOR_CMD_PP_1_4_4,
75 SNOR_CMD_PP_4_4_4,
76
77 /* Octal SPI */
78 SNOR_CMD_PP_1_1_8,
79 SNOR_CMD_PP_1_8_8,
80 SNOR_CMD_PP_8_8_8,
81
82 SNOR_CMD_PP_MAX
83 };
84
85 /**
86 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
87 * @size: the size of the sector/block erased by the erase type.
88 * JEDEC JESD216B imposes erase sizes to be a power of 2.
89 * @size_shift: @size is a power of 2, the shift is stored in
90 * @size_shift.
91 * @size_mask: the size mask based on @size_shift.
92 * @opcode: the SPI command op code to erase the sector/block.
93 * @idx: Erase Type index as sorted in the Basic Flash Parameter
94 * Table. It will be used to synchronize the supported
95 * Erase Types with the ones identified in the SFDP
96 * optional tables.
97 */
98 struct spi_nor_erase_type {
99 u32 size;
100 u32 size_shift;
101 u32 size_mask;
102 u8 opcode;
103 u8 idx;
104 };
105
106 /**
107 * struct spi_nor_erase_command - Used for non-uniform erases
108 * The structure is used to describe a list of erase commands to be executed
109 * once we validate that the erase can be performed. The elements in the list
110 * are run-length encoded.
111 * @list: for inclusion into the list of erase commands.
112 * @count: how many times the same erase command should be
113 * consecutively used.
114 * @size: the size of the sector/block erased by the command.
115 * @opcode: the SPI command op code to erase the sector/block.
116 */
117 struct spi_nor_erase_command {
118 struct list_head list;
119 u32 count;
120 u32 size;
121 u8 opcode;
122 };
123
124 /**
125 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
126 * @offset: the offset in the data array of erase region start.
127 * LSB bits are used as a bitmask encoding flags to
128 * determine if this region is overlaid, if this region is
129 * the last in the SPI NOR flash memory and to indicate
130 * all the supported erase commands inside this region.
131 * The erase types are sorted in ascending order with the
132 * smallest Erase Type size being at BIT(0).
133 * @size: the size of the region in bytes.
134 */
135 struct spi_nor_erase_region {
136 u64 offset;
137 u64 size;
138 };
139
140 #define SNOR_ERASE_TYPE_MAX 4
141 #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
142
143 #define SNOR_LAST_REGION BIT(4)
144 #define SNOR_OVERLAID_REGION BIT(5)
145
146 #define SNOR_ERASE_FLAGS_MAX 6
147 #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
148
149 /**
150 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
151 * @regions: array of erase regions. The regions are consecutive in
152 * address space. Walking through the regions is done
153 * incrementally.
154 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
155 * sector size (legacy implementation).
156 * @erase_type: an array of erase types shared by all the regions.
157 * The erase types are sorted in ascending order, with the
158 * smallest Erase Type size being the first member in the
159 * erase_type array.
160 * @uniform_erase_type: bitmask encoding erase types that can erase the
161 * entire memory. This member is completed at init by
162 * uniform and non-uniform SPI NOR flash memories if they
163 * support at least one erase type that can erase the
164 * entire memory.
165 */
166 struct spi_nor_erase_map {
167 struct spi_nor_erase_region *regions;
168 struct spi_nor_erase_region uniform_region;
169 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
170 u8 uniform_erase_type;
171 };
172
173 /**
174 * struct spi_nor_locking_ops - SPI NOR locking methods
175 * @lock: lock a region of the SPI NOR.
176 * @unlock: unlock a region of the SPI NOR.
177 * @is_locked: check if a region of the SPI NOR is completely locked
178 */
179 struct spi_nor_locking_ops {
180 int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
181 int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
182 int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
183 };
184
185 /**
186 * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
187 * Includes legacy flash parameters and settings that can be overwritten
188 * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
189 * Serial Flash Discoverable Parameters (SFDP) tables.
190 *
191 * @size: the flash memory density in bytes.
192 * @page_size: the page size of the SPI NOR flash memory.
193 * @hwcaps: describes the read and page program hardware
194 * capabilities.
195 * @reads: read capabilities ordered by priority: the higher index
196 * in the array, the higher priority.
197 * @page_programs: page program capabilities ordered by priority: the
198 * higher index in the array, the higher priority.
199 * @erase_map: the erase map parsed from the SFDP Sector Map Parameter
200 * Table.
201 * @quad_enable: enables SPI NOR quad mode.
202 * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
203 * @convert_addr: converts an absolute address into something the flash
204 * will understand. Particularly useful when pagesize is
205 * not a power-of-2.
206 * @setup: configures the SPI NOR memory. Useful for SPI NOR
207 * flashes that have peculiarities to the SPI NOR standard
208 * e.g. different opcodes, specific address calculation,
209 * page size, etc.
210 * @locking_ops: SPI NOR locking methods.
211 */
212 struct spi_nor_flash_parameter {
213 u64 size;
214 u32 page_size;
215
216 struct spi_nor_hwcaps hwcaps;
217 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
218 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
219
220 struct spi_nor_erase_map erase_map;
221
222 int (*quad_enable)(struct spi_nor *nor);
223 int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
224 u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
225 int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
226
227 const struct spi_nor_locking_ops *locking_ops;
228 };
229
230 /**
231 * struct spi_nor_fixups - SPI NOR fixup hooks
232 * @default_init: called after default flash parameters init. Used to tweak
233 * flash parameters when information provided by the flash_info
234 * table is incomplete or wrong.
235 * @post_bfpt: called after the BFPT table has been parsed
236 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
237 * that do not support RDSFDP). Typically used to tweak various
238 * parameters that could not be extracted by other means (i.e.
239 * when information provided by the SFDP/flash_info tables are
240 * incomplete or wrong).
241 *
242 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
243 * table is broken or not available.
244 */
245 struct spi_nor_fixups {
246 void (*default_init)(struct spi_nor *nor);
247 int (*post_bfpt)(struct spi_nor *nor,
248 const struct sfdp_parameter_header *bfpt_header,
249 const struct sfdp_bfpt *bfpt,
250 struct spi_nor_flash_parameter *params);
251 void (*post_sfdp)(struct spi_nor *nor);
252 };
253
254 struct flash_info {
255 char *name;
256
257 /*
258 * This array stores the ID bytes.
259 * The first three bytes are the JEDIC ID.
260 * JEDEC ID zero means "no ID" (mostly older chips).
261 */
262 u8 id[SPI_NOR_MAX_ID_LEN];
263 u8 id_len;
264
265 /* The size listed here is what works with SPINOR_OP_SE, which isn't
266 * necessarily called a "sector" by the vendor.
267 */
268 unsigned sector_size;
269 u16 n_sectors;
270
271 u16 page_size;
272 u16 addr_width;
273
274 u32 flags;
275 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
276 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
277 #define SST_WRITE BIT(2) /* use SST byte programming */
278 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
279 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
280 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
281 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
282 #define USE_FSR BIT(7) /* use flag status register */
283 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
284 #define SPI_NOR_HAS_TB BIT(9) /*
285 * Flash SR has Top/Bottom (TB) protect
286 * bit. Must be used with
287 * SPI_NOR_HAS_LOCK.
288 */
289 #define SPI_NOR_XSR_RDY BIT(10) /*
290 * S3AN flashes have specific opcode to
291 * read the status register.
292 */
293 #define SPI_NOR_4B_OPCODES BIT(11) /*
294 * Use dedicated 4byte address op codes
295 * to support memory size above 128Mib.
296 */
297 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
298 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
299 #define USE_CLSR BIT(14) /* use CLSR command */
300 #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
301 #define SPI_NOR_TB_SR_BIT6 BIT(16) /*
302 * Top/Bottom (TB) is bit 6 of
303 * status register. Must be used with
304 * SPI_NOR_HAS_TB.
305 */
306 #define SPI_NOR_4BIT_BP BIT(17) /*
307 * Flash SR has 4 bit fields (BP0-3)
308 * for block protection.
309 */
310 #define SPI_NOR_BP3_SR_BIT6 BIT(18) /*
311 * BP3 is bit 6 of status register.
312 * Must be used with SPI_NOR_4BIT_BP.
313 */
314
315 /* Part specific fixup hooks. */
316 const struct spi_nor_fixups *fixups;
317 };
318
319 /* Used when the "_ext_id" is two bytes at most */
320 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
321 .id = { \
322 ((_jedec_id) >> 16) & 0xff, \
323 ((_jedec_id) >> 8) & 0xff, \
324 (_jedec_id) & 0xff, \
325 ((_ext_id) >> 8) & 0xff, \
326 (_ext_id) & 0xff, \
327 }, \
328 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
329 .sector_size = (_sector_size), \
330 .n_sectors = (_n_sectors), \
331 .page_size = 256, \
332 .flags = (_flags),
333
334 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
335 .id = { \
336 ((_jedec_id) >> 16) & 0xff, \
337 ((_jedec_id) >> 8) & 0xff, \
338 (_jedec_id) & 0xff, \
339 ((_ext_id) >> 16) & 0xff, \
340 ((_ext_id) >> 8) & 0xff, \
341 (_ext_id) & 0xff, \
342 }, \
343 .id_len = 6, \
344 .sector_size = (_sector_size), \
345 .n_sectors = (_n_sectors), \
346 .page_size = 256, \
347 .flags = (_flags),
348
349 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
350 .sector_size = (_sector_size), \
351 .n_sectors = (_n_sectors), \
352 .page_size = (_page_size), \
353 .addr_width = (_addr_width), \
354 .flags = (_flags),
355
356 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
357 .id = { \
358 ((_jedec_id) >> 16) & 0xff, \
359 ((_jedec_id) >> 8) & 0xff, \
360 (_jedec_id) & 0xff \
361 }, \
362 .id_len = 3, \
363 .sector_size = (8*_page_size), \
364 .n_sectors = (_n_sectors), \
365 .page_size = _page_size, \
366 .addr_width = 3, \
367 .flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY,
368
369 /**
370 * struct spi_nor_manufacturer - SPI NOR manufacturer object
371 * @name: manufacturer name
372 * @parts: array of parts supported by this manufacturer
373 * @nparts: number of entries in the parts array
374 * @fixups: hooks called at various points in time during spi_nor_scan()
375 */
376 struct spi_nor_manufacturer {
377 const char *name;
378 const struct flash_info *parts;
379 unsigned int nparts;
380 const struct spi_nor_fixups *fixups;
381 };
382
383 /* Manufacturer drivers. */
384 extern const struct spi_nor_manufacturer spi_nor_atmel;
385 extern const struct spi_nor_manufacturer spi_nor_catalyst;
386 extern const struct spi_nor_manufacturer spi_nor_eon;
387 extern const struct spi_nor_manufacturer spi_nor_esmt;
388 extern const struct spi_nor_manufacturer spi_nor_everspin;
389 extern const struct spi_nor_manufacturer spi_nor_fujitsu;
390 extern const struct spi_nor_manufacturer spi_nor_gigadevice;
391 extern const struct spi_nor_manufacturer spi_nor_intel;
392 extern const struct spi_nor_manufacturer spi_nor_issi;
393 extern const struct spi_nor_manufacturer spi_nor_macronix;
394 extern const struct spi_nor_manufacturer spi_nor_micron;
395 extern const struct spi_nor_manufacturer spi_nor_st;
396 extern const struct spi_nor_manufacturer spi_nor_spansion;
397 extern const struct spi_nor_manufacturer spi_nor_sst;
398 extern const struct spi_nor_manufacturer spi_nor_winbond;
399 extern const struct spi_nor_manufacturer spi_nor_xilinx;
400 extern const struct spi_nor_manufacturer spi_nor_xmc;
401
402 int spi_nor_write_enable(struct spi_nor *nor);
403 int spi_nor_write_disable(struct spi_nor *nor);
404 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable);
405 int spi_nor_write_ear(struct spi_nor *nor, u8 ear);
406 int spi_nor_wait_till_ready(struct spi_nor *nor);
407 int spi_nor_lock_and_prep(struct spi_nor *nor);
408 void spi_nor_unlock_and_unprep(struct spi_nor *nor);
409 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
410 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
411 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
412 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
413
414 int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr);
415 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
416 u8 *buf);
417 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
418 const u8 *buf);
419
420 int spi_nor_hwcaps_read2cmd(u32 hwcaps);
421 u8 spi_nor_convert_3to4_read(u8 opcode);
422 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
423 enum spi_nor_protocol proto);
424
425 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
426 u8 opcode);
427 struct spi_nor_erase_region *
428 spi_nor_region_next(struct spi_nor_erase_region *region);
429 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
430 u8 erase_mask, u64 flash_size);
431
432 int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
433 const struct sfdp_parameter_header *bfpt_header,
434 const struct sfdp_bfpt *bfpt,
435 struct spi_nor_flash_parameter *params);
436
mtd_to_spi_nor(struct mtd_info * mtd)437 static struct spi_nor __maybe_unused *mtd_to_spi_nor(struct mtd_info *mtd)
438 {
439 return mtd->priv;
440 }
441
442 #endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */
443