1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*******************************************************************************
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
4
5
6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7 *******************************************************************************/
8
9 #ifndef __STMMAC_H__
10 #define __STMMAC_H__
11
12 #define STMMAC_RESOURCE_NAME "stmmaceth"
13 #define DRV_MODULE_VERSION "Jan_2016"
14
15 #include <linux/clk.h>
16 #include <linux/if_vlan.h>
17 #include <linux/stmmac.h>
18 #include <linux/phylink.h>
19 #include <linux/pci.h>
20 #include "common.h"
21 #include <linux/ptp_clock_kernel.h>
22 #include <linux/net_tstamp.h>
23 #include <linux/reset.h>
24 #include <net/page_pool.h>
25
26 struct stmmac_resources {
27 void __iomem *addr;
28 const char *mac;
29 int wol_irq;
30 int lpi_irq;
31 int irq;
32 };
33
34 struct stmmac_tx_info {
35 dma_addr_t buf;
36 bool map_as_page;
37 unsigned len;
38 bool last_segment;
39 bool is_jumbo;
40 };
41
42 #define STMMAC_TBS_AVAIL BIT(0)
43 #define STMMAC_TBS_EN BIT(1)
44
45 /* Frequently used values are kept adjacent for cache effect */
46 struct stmmac_tx_queue {
47 u32 tx_count_frames;
48 int tbs;
49 struct timer_list txtimer;
50 u32 queue_index;
51 struct stmmac_priv *priv_data;
52 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
53 struct dma_edesc *dma_entx;
54 struct dma_desc *dma_tx;
55 struct sk_buff **tx_skbuff;
56 struct stmmac_tx_info *tx_skbuff_dma;
57 unsigned int cur_tx;
58 unsigned int dirty_tx;
59 dma_addr_t dma_tx_phy;
60 u32 tx_tail_addr;
61 u32 mss;
62 };
63
64 struct stmmac_rx_buffer {
65 struct page *page;
66 struct page *sec_page;
67 dma_addr_t addr;
68 dma_addr_t sec_addr;
69 };
70
71 struct stmmac_rx_queue {
72 u32 rx_count_frames;
73 u32 queue_index;
74 struct page_pool *page_pool;
75 struct stmmac_rx_buffer *buf_pool;
76 struct stmmac_priv *priv_data;
77 struct dma_extended_desc *dma_erx;
78 struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
79 unsigned int cur_rx;
80 unsigned int dirty_rx;
81 u32 rx_zeroc_thresh;
82 dma_addr_t dma_rx_phy;
83 u32 rx_tail_addr;
84 unsigned int state_saved;
85 struct {
86 struct sk_buff *skb;
87 unsigned int len;
88 unsigned int error;
89 } state;
90 };
91
92 struct stmmac_channel {
93 struct napi_struct rx_napi ____cacheline_aligned_in_smp;
94 struct napi_struct tx_napi ____cacheline_aligned_in_smp;
95 struct stmmac_priv *priv_data;
96 spinlock_t lock;
97 u32 index;
98 };
99
100 struct stmmac_tc_entry {
101 bool in_use;
102 bool in_hw;
103 bool is_last;
104 bool is_frag;
105 void *frag_ptr;
106 unsigned int table_pos;
107 u32 handle;
108 u32 prio;
109 struct {
110 u32 match_data;
111 u32 match_en;
112 u8 af:1;
113 u8 rf:1;
114 u8 im:1;
115 u8 nc:1;
116 u8 res1:4;
117 u8 frame_offset;
118 u8 ok_index;
119 u8 dma_ch_no;
120 u32 res2;
121 } __packed val;
122 };
123
124 #define STMMAC_PPS_MAX 4
125 struct stmmac_pps_cfg {
126 bool available;
127 struct timespec64 start;
128 struct timespec64 period;
129 };
130
131 struct stmmac_rss {
132 int enable;
133 u8 key[STMMAC_RSS_HASH_KEY_SIZE];
134 u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
135 };
136
137 #define STMMAC_FLOW_ACTION_DROP BIT(0)
138 struct stmmac_flow_entry {
139 unsigned long cookie;
140 unsigned long action;
141 u8 ip_proto;
142 int in_use;
143 int idx;
144 int is_l4;
145 };
146
147 struct stmmac_priv {
148 /* Frequently used values are kept adjacent for cache effect */
149 u32 tx_coal_frames;
150 u32 tx_coal_timer;
151 u32 rx_coal_frames;
152
153 int tx_coalesce;
154 int hwts_tx_en;
155 bool tx_path_in_lpi_mode;
156 bool tso;
157 int sph;
158 u32 sarc_type;
159
160 unsigned int dma_buf_sz;
161 unsigned int rx_copybreak;
162 u32 rx_riwt;
163 int hwts_rx_en;
164
165 void __iomem *ioaddr;
166 struct net_device *dev;
167 struct device *device;
168 struct mac_device_info *hw;
169 int (*hwif_quirks)(struct stmmac_priv *priv);
170 struct mutex lock;
171
172 /* RX Queue */
173 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
174 unsigned int dma_rx_size;
175
176 /* TX Queue */
177 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
178 unsigned int dma_tx_size;
179
180 /* Generic channel for NAPI */
181 struct stmmac_channel channel[STMMAC_CH_MAX];
182
183 int speed;
184 unsigned int flow_ctrl;
185 unsigned int pause;
186 struct mii_bus *mii;
187 int mii_irq[PHY_MAX_ADDR];
188
189 struct phylink_config phylink_config;
190 struct phylink *phylink;
191
192 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
193 struct stmmac_safety_stats sstats;
194 struct plat_stmmacenet_data *plat;
195 struct dma_features dma_cap;
196 struct stmmac_counters mmc;
197 int hw_cap_support;
198 int synopsys_id;
199 u32 msg_enable;
200 int wolopts;
201 int wol_irq;
202 int clk_csr;
203 struct timer_list eee_ctrl_timer;
204 int lpi_irq;
205 int eee_enabled;
206 int eee_active;
207 int tx_lpi_timer;
208 int tx_lpi_enabled;
209 int eee_tw_timer;
210 unsigned int mode;
211 unsigned int chain_mode;
212 int extend_desc;
213 struct hwtstamp_config tstamp_config;
214 struct ptp_clock *ptp_clock;
215 struct ptp_clock_info ptp_clock_ops;
216 unsigned int default_addend;
217 u32 sub_second_inc;
218 u32 systime_flags;
219 u32 adv_ts;
220 int use_riwt;
221 int irq_wake;
222 spinlock_t ptp_lock;
223 void __iomem *mmcaddr;
224 void __iomem *ptpaddr;
225 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
226
227 #ifdef CONFIG_DEBUG_FS
228 struct dentry *dbgfs_dir;
229 #endif
230
231 unsigned long state;
232 struct workqueue_struct *wq;
233 struct work_struct service_task;
234
235 /* TC Handling */
236 unsigned int tc_entries_max;
237 unsigned int tc_off_max;
238 struct stmmac_tc_entry *tc_entries;
239 unsigned int flow_entries_max;
240 struct stmmac_flow_entry *flow_entries;
241
242 /* Pulse Per Second output */
243 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
244
245 /* Receive Side Scaling */
246 struct stmmac_rss rss;
247 };
248
249 enum stmmac_state {
250 STMMAC_DOWN,
251 STMMAC_RESET_REQUESTED,
252 STMMAC_RESETING,
253 STMMAC_SERVICE_SCHED,
254 };
255
256 int stmmac_mdio_unregister(struct net_device *ndev);
257 int stmmac_mdio_register(struct net_device *ndev);
258 int stmmac_mdio_reset(struct mii_bus *mii);
259 void stmmac_set_ethtool_ops(struct net_device *netdev);
260
261 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags);
262 void stmmac_ptp_register(struct stmmac_priv *priv);
263 void stmmac_ptp_unregister(struct stmmac_priv *priv);
264 int stmmac_resume(struct device *dev);
265 int stmmac_suspend(struct device *dev);
266 int stmmac_dvr_remove(struct device *dev);
267 int stmmac_dvr_probe(struct device *device,
268 struct plat_stmmacenet_data *plat_dat,
269 struct stmmac_resources *res);
270 void stmmac_disable_eee_mode(struct stmmac_priv *priv);
271 bool stmmac_eee_init(struct stmmac_priv *priv);
272 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
273 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
274 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
275
276 #if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
277 void stmmac_selftest_run(struct net_device *dev,
278 struct ethtool_test *etest, u64 *buf);
279 void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
280 int stmmac_selftest_get_count(struct stmmac_priv *priv);
281 #else
stmmac_selftest_run(struct net_device * dev,struct ethtool_test * etest,u64 * buf)282 static inline void stmmac_selftest_run(struct net_device *dev,
283 struct ethtool_test *etest, u64 *buf)
284 {
285 /* Not enabled */
286 }
stmmac_selftest_get_strings(struct stmmac_priv * priv,u8 * data)287 static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
288 u8 *data)
289 {
290 /* Not enabled */
291 }
stmmac_selftest_get_count(struct stmmac_priv * priv)292 static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
293 {
294 return -EOPNOTSUPP;
295 }
296 #endif /* CONFIG_STMMAC_SELFTESTS */
297
298 #endif /* __STMMAC_H__ */
299